Relevant bibliographies by topics / CMOS interface

Academic literature on the topic 'CMOS interface'

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Published: 14 March 2023

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Journal articles on the topic "CMOS interface"

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Lau, K. T., W. Y. Wang, and K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit." International Journal of Electronics 87, no. 1 (January 2000): 27–32. http://dx.doi.org/10.1080/002072100132417.

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Ghoshal, U., S. V. Kishore, A. R. Feldman, Luong Huynh, and T. Van Duzer. "CMOS amplifier designs for Josephson-CMOS interface circuits." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 2640–43. http://dx.doi.org/10.1109/77.403132.

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Wei, Daniel, Stephen R. Whiteley, Lizhen Zheng, Heejoung Park, Hoki Kim, and Theodore Van Duzer. "New Josephson-CMOS Interface Amplifier." IEEE Transactions on Applied Superconductivity 21, no. 3 (June 2011): 805–8. http://dx.doi.org/10.1109/tasc.2010.2088358.

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Takagi, Shinichi, Sanjeewa Dissanayake, and Mitsuru Takenaka. "High Mobility Ge-Based CMOS Device Technologies." Key Engineering Materials 470 (February 2011): 1–7. http://dx.doi.org/10.4028/www.scientific.net/kem.470.1.

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In this paper, we report on critical issues and possible solutions for realizing Ge MOSFETs on the Si platform. The main critical objectives in regard to Ge MOSFETs are (1) formation of high quality Ge channel layers on Si substrates (2) MIS gate stacks with much smaller EOT and interface defects (3) superior source/drain junction technology (4) combination of mobility booster technologies such as surface orientation and strain. We demonstrate that GeO2/Ge MOS interfaces can provide superior interface properties, leading to high hole and electron mobility. It is also shown that a gas phase doping technique is promising for forming superior n+/p junctions, which is critical for obtaining Ge nMOSFETs. Also, the importance of surface orientation engineering on the further mobility enhancement of Ge CMOS is addressed.
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Wu, Xiang, and Fang Ming Deng. "A Capacitive Humidity Sensor for Low-Cost Low-Power Application." Applied Mechanics and Materials 556-562 (May 2014): 1847–51. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1847.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface employs a fully-digital architecture based on phase locked loop, which results in low pow dissipation. The proposed humidity sensor is fabricated in TSMC 0.18μm CMOS process and the chip occupies an area of 0.05mm2. The measurement result shows that the sensor value exhibits good linearity within the range of 10-90%RH and the interface circuit consumes only 1.05μW at 0.5V supply voltage.
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Chen, Wei Ping, Chang Chun Dong, Xiao Wei Liu, and Zhi Ping Zhou. "A Miniature Fluxgate Sensor with CMOS Interface Circuitry." Key Engineering Materials 483 (June 2011): 164–68. http://dx.doi.org/10.4028/www.scientific.net/kem.483.164.

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In this paper, the writers reported on a fluxgate sensor and a CMOS-ASIC for sensor supply. The design method and principle of the interface circuit of the fluxgate sensor was also presented, which was based on second-harmonic detection of the output voltage. This circuit has been simulated and realized through 0.5μm DPDM P-sub CMOS Process. The size of this circuit is 2mm×2mm. The circuit exhibited a sensitivity of 16.5mV/μT and a linear range of ±90μT. With 5V of voltage supply, the total power consumption of the circuit was as low as 35 mW.
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Civardi, L., U. Gatti, F. Maloberti, and G. Torelli. "An integrated CMOS interface for lambda sensor." IEEE Transactions on Vehicular Technology 43, no. 1 (1994): 40–46. http://dx.doi.org/10.1109/25.282264.

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Schubert, M. "70V-to-5V differential CMOS input interface." Electronics Letters 30, no. 4 (February 17, 1994): 296–97. http://dx.doi.org/10.1049/el:19940235.

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Obaid, Abdulmalik, Mina-Elraheb Hanna, Yu-Wei Wu, Mihaly Kollo, Romeo Racz, Matthew R. Angle, Jan Müller, et al. "Massively parallel microwire arrays integrated with CMOS chips for neural recording." Science Advances 6, no. 12 (March 2020): eaay2789. http://dx.doi.org/10.1126/sciadv.aay2789.

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Multi-channel electrical recordings of neural activity in the brain is an increasingly powerful method revealing new aspects of neural communication, computation, and prosthetics. However, while planar silicon-based CMOS devices in conventional electronics scale rapidly, neural interface devices have not kept pace. Here, we present a new strategy to interface silicon-based chips with three-dimensional microwire arrays, providing the link between rapidly-developing electronics and high density neural interfaces. The system consists of a bundle of microwires mated to large-scale microelectrode arrays, such as camera chips. This system has excellent recording performance, demonstrated via single unit and local-field potential recordings in isolated retina and in the motor cortex or striatum of awake moving mice. The modular design enables a variety of microwire types and sizes to be integrated with different types of pixel arrays, connecting the rapid progress of commercial multiplexing, digitisation and data acquisition hardware together with a three-dimensional neural interface.
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Deng, Fang Ming, and Yi Gang He. "A Low-Cost Low-Power Capacitive Humidity Sensor in CMOS Technology." Applied Mechanics and Materials 556-562 (May 2014): 1842–46. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1842.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface is based on a delta-sigma converter and can be easily reconfigured to compensate for process variation of the sensing element. The proposed humidity sensor is fabricated in 0.16μm standard CMOS process and the chip occupies 0.25mm2. The measurement result shows that this humidity sensor acquires a resolution of 0.1%RH in the range of 20%RH to 90%RH. The interface achieves a 12.5-bits capacitance-to-digital conversion and consumes only 9.6μW power at 1.2V supply voltage.
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Dissertations / Theses on the topic "CMOS interface"

1

Berber, Feyza. "CMOS temperature sensor utilizing interface-trap charge pumping." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4157.

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The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface–trap charge pumping phenomenon and the temperature sensitivity of generation current is proposed. This thesis presents the design and characterization of the proposed temperature sensor fabricated in 0.18µm CMOS technology. The prototype sensor is characterized for the temperature range of 27oC–120oC. It has frequency output and exhibits linear transfer characteristics, high sensitivity, and high resolution. This temperature sensor is proposed for microprocessor thermal management applications.
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Zhao, Dongning. "A low-noise CMOS interface for capacitive microaccelerometers." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31715.

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The high-performance accelerometers with micro-gravity resolution and large dynamic range at very low frequencies are not only used in GPS-augmented inertial navigation, monitoring of aircrafts and space station, but also used in monitoring wind turbines for green energy. This dissertation presents the design and development of a mixed-signal, low-noise, and fourth-order sigma-delta interface circuit for the MEMS capacitive micro-gravity accelerometer. A fully-differential switched-capacitor (SC) amplifier architecture is developed with the low-frequency noise reduction through the integration of chopper-stabilization technique with lateral BJT at input stage. The effectiveness of different noise reduction techniques is also compared and verified. The application of fourth-order SC sigma-delta modulation concept to the inertial-grade accelerometer is to achieve the benefits of the digitization of the accelerometer output without compromising the resolution of the analog front-end. This open-loop interface provides 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power dissipation and maximum dynamic range. The micromechanical accelerometers are fabricated in thick silicon-on-insulator (SOI) substrates. The accelerometer operates in air and is designed for non-peaking response with a bandwidth of 500 Hz.
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Hafizović, Sadik. "Neural interface and atomic-force microscope in CMOS technology /." Zürich : Physical Electronics Laboratory, ETH Zürich, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16806.

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Silay, Kanber Mithat. "High Performance Cmos Capacitive Interface Circuits For Mems Gyroscopes." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/2/12607518/index.pdf.

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This thesis reports the development and analysis of high performance CMOS readout electronics for increasing the performance of MEMS gyroscopes developed at Middle East Technical University (METU). These readout electronics are based on unity gain buffers implemented with source followers. High impedance node biasing problem present in capacitive interfaces is solved with the implementation of a transistor operating in the subthreshold region. A generalized fully differential gyroscope model with force feedback electrodes has been developed in order to simulate the capacitive interfaces with the model of the gyroscope. This model is simplified for the single ended gyroscopes fabricated at METU, and simulations of resonance characteristics are done. Three gyroscope interfaces are designed by considering the problems faced in previous interface architectures. The first design is implemented using a single ended source follower biased with a subthreshold transistor. From the simulations, it is observed that biasing impedances up to several gigaohms can be achieved. The second design is the fully differential version of the first design with the addition of a self biasing scheme. In another interface, the second design is modified with an instrumentation amplifier which is used for fully differential to single ended conversion. All of these interfaces are fabricated in a standard 0.6 µ
m CMOS process. Fabricated interfaces are characterized by measuring their ac responses, noise response and transient characteristics for a sinusoidal input. It is observed that, biasing impedances up to 60 gigaohms can be obtained with subthreshold transistors. Self biasing architecture eliminates the need for biasing the source of the subthreshold transistor to set the output dc point to 0 V. Single ended SOG gyroscopes are characterized with the single ended capacitive interfaces, and a 45 dB gain improvement is observed with the addition of capacitive interface to the drive mode. Minimum resolvable capacitance change and displacement that can be measured are found to be 58.31 zF and 38.87 Fermi, respectively. The scale factor of the gyroscope is found to be 1.97 mV/(°
/sec) with a nonlinearity of only 0.001% in ±
100 °
/sec measurement range. The bias instability and angle random walk of the gyroscope are determined using Allan variance method as 2.158 °
/&
#8730
hr and 124.7 °
/hr, respectively.
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Cho, Taeg Sang. "An energy efficient CMOS interface to carbon nanotube sensor arrays." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40519.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 95-98).
A carbon nanotube is considered as a candidate for a next-generation chemical sensor. CNT sensors are attractive as they allow room-temperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major sources of power dissipation in other types of sensor systems. Nevertheless, a poor control of the CNT resistance poses a constraint on the attainable energy efficiency of the sensor platform. An investigation on the CNT sensors shows that the dynamic range of the interface should be 17 bits, while the resolution at each base resistance should be 7 bits. The proposed CMOS interface extends upon the previously published work to optimize the energy performance through both the architecture and circuit level innovations. The 17-bit dynamic range is attained by distributing the requirement into a 10-bit Analog-to-Digital Converter (ADC) and a 8-bit Digital-to-Analog Converter (DAC). An extra 1-bit leaves room for any unaccounted subblock performance error. Several system-level all-digital calibration schemes are proposed to account for DAC nonlinearity, ADC offset voltage, and a large variation in CNT base resistance. Circuit level techniques are employed to decrease the leakage current in the sensitive frontend node, to decrease the energy consumption of the ADC, and to efficiently control the DAC. The interface circuit is fabricated in 0.18 /m CMOS technology, and can operate at 1.83 kS/s sampling rate at 32 pW worst case power. The resistance measurement error across the whole dynamic range is less than 1.34% after calibration. A functionality of the full chemical sensor system has been demonstrated to validate the concepts introduced in this thesis.
by Taeg Sang Cho.
S.M.
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Zhang, Tan Tan. "Nano-watt class CMOS interface circuits for wireless sensor nodes." Thesis, University of Macau, 2018. http://umaclib3.umac.mo/record=b3952097.

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Hehn, Thorsten [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "A CMOS Integrated Interface Circuit for Piezoelectric Energy Harvesters = Eine CMOS-Integrierte Schnittstellenschaltung für Piezoelektrische Energy Harvester." Freiburg : Universität, 2014. http://d-nb.info/1123479119/34.

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Frey, Urs. "High-density neural interface and microhotplate gas sensor in CMOS technology /." Zürich : Physical Electronics Laboratory, ETH Zürich, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=17460.

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Leung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.

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With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.
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BARTESELLI, EDOARDO. "Accurate Voltage Reference Generator for Audio Interface in 65/55nm CMOS Technology." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/364988.

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Negli ultimi anni i dispositivi mobili sono molto complessi e ricchi di funzionalità che consumano molta energia. Per questo motivo, l'industria elettronica sta spingendo verso la riduzione del consumo di energia e corrente nei dispositivi elettronici per aumentare la durata della batteria. Tutto va fatto mantenendo le stesse prestazioni o migliorandole. Questa tesi presenta un accurato generatore di riferimento di tensione per interfaccia audio in tecnologia CMOS a 65/55nm e particolare attenzione è stata posta al consumo di corrente. Il riferimento è costituito da un riferimento di tensione Bandgap e da un regolatore Low Dropout. La topologia scelta per il bandgap è un bandgap in modalità di corrente con resistore di uscita regolabile. Ciò garantisce una tensione di riferimento inferiore a 1.2V grazie alla somma di due correnti invece di due tensioni. È stato scelto un doppio circuito per il regolatore LDO per garantire una rapida risposta ai transitori. Innanzitutto, il generatore di riferimento di tensione è stato simulato in tecnologia CMOS a 65nm. Nelle simulazioni a 65 nm tutte le specifiche mirate sono state raggiunte con successo. Per BG, il consumo di corrente è inferiore a 5uA, DC PSR inferiore a -60dB e un coefficiente di temperatura di circa 5ppm/°C. L'LDO ha un tempo di assestamento inferiore a 150ns, un PSR inferiore a -70dB nella banda audio ([20, 20K]Hz) e un consumo energetico inferiore a 10uA. Quindi, è stato simulato e misurato con la tecnologia CMOS a 55nm e sono stati sviluppati e testati tre diversi prototipi. I risultati non sono buoni come quelli a 65nm perché questa è stata la prima volta che la tecnologia è stata utilizzata. Quindi, i tre chip di test sviluppati sono stati utilizzati per comprendere il comportamento della tecnologia e per confrontare le simulazioni con le misurazioni, ma ogni chip di test rappresenta un miglioramento rispetto al precedente. L'ultimo chip di prova presenta un PSR molto vicino alle specifiche sia per il BG che per l’LDO e un consumo di corrente di 5uA per il BG, 10uA per l’LDO NM e 5uA per l’LDO LP.
In recent years, mobile devices are very complex and feature-rich that consume a lot of energy. For this reason, the electronics industry is pushing towards reducing power and current consumption in electronic devices to increase battery life. Everything has to be done while maintaining the same performance or improving it. This thesis presents an accurate voltage reference generator for audio interface in CMOS technology at 65/55nm and particular attention has been paid to current consumption. The reference is made up of a Bandgap voltage reference and a Low Dropout regulator. The topology chosen for the bandgap is a current mode bandgap with adjustable output resistor. This guarantees a reference voltage of less than 1.2V thanks to the sum of two currents instead of two voltages. A double loop was chosen for the LDO regulator to ensure rapid transient response. First, the voltage reference generator was simulated in CMOS technology at 65nm. In the 65nm simulations all targeted specifications were successfully achieved. For BG, power consumption is less than 5uA, DC PSR lower than -60dB and a temperature coefficient around 5ppm/°C. The LDO has a fast settling time lower 150ns, a PSR of less than -70dB in the audio band ([20, 20K]Hz) and a power consumption of less than 10uA. Then, it was simulated and measured with 55nm CMOS technology and three different prototypes were developed and tested. The results are not as good as the 65 nm results because this was the first time the technology was used. Then, the three developed test chips were used to understand the behavior of the technology and to compare simulations with measurements, but each test chip is an improvement on the previous one. The latest test chip features PSR very close to specifications for BG and LDO and power consumption of 5uA for the BG, 10uA for the LDO NM and 5uA for the LDO LP.
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Books on the topic "CMOS interface"

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Incorporated, Advanced Micro Devices. High performance CMOS bus interface products data book. Sunnyvale, Calif: Advanced Micro Devices, 1989.

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Carrara, Sandro. Bio/CMOS Interfaces and Co-Design. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4690-3.

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Design of custom CMOS amplifiers for nanoscale bio-interfaces. [New York, N.Y.?]: [publisher not identified], 2019.

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Low, P. F., J. K. Mitchell, G. Sposito, and H. van Olphen. Clay-Water Interface and its Rheological Implications. Edited by N. Güven and R. M. Pollastro. Boulder, Colorado: Clay Minerals Society, 1992. http://dx.doi.org/10.1346/cms-wls-4.

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Institute, SAS, ed. Getting started with the SAS System in the CMS environment. 6th ed. Cary, NC: SAS Institute, 1997.

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Meeting, Materials Research Society, and Symposium C, "CMOS Gate-Stack Scaling-- Materials, Interfaces and Reliability Implications" (2009 : San Francisco, Calif.), eds. CMOS gate-stack scaling-- materials, interfaces and reliability implications: Symposium held April 14-16, 2009, San Francisco, california, U.S.A. Warrendale, Pa: Materials Research Society, 2009.

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Manoli, Yiannos, and Thorsten Hehn. CMOS Circuits for Piezoelectric Energy Harvesters: Efficient Power Extraction, Interface Modeling and Loss Analysis. Springer, 2014.

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Manoli, Yiannos, and Thorsten Hehn. CMOS Circuits for Piezoelectric Energy Harvesters: Efficient Power Extraction, Interface Modeling and Loss Analysis. Springer London, Limited, 2015.

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Manoli, Yiannos, and Thorsten Hehn. CMOS Circuits for Piezoelectric Energy Harvesters: Efficient Power Extraction, Interface Modeling and Loss Analysis. Springer, 2016.

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Benson, Niels. Organic CMOS technology by dielectric interface engineering: Chemically functionalized dielectrics for the control of OFET polarity / charge carrier transport properties. Suedwestdeutscher Verlag fuer Hochschulschriften, 2009.

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Book chapters on the topic "CMOS interface"

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Hurley, P., O. Engström, D. Bauza, and G. Ghibaudo. "Characterization of Interface Defects." In Nanoscale CMOS, 545–73. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch15.

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Bernstein, Kerry, Keith M. Carrig, Christopher M. Durham, Patrick R. Hansen, David Hogenmiller, Edward J. Nowak, and Norman J. Rohrer. "Interface Techniques." In High Speed CMOS Design Styles, 207–46. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4615-5573-5_6.

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Maurath, Dominic, and Yiannos Manoli. "Switched-Inductor Capacitive Interface." In CMOS Circuits for Electromagnetic Vibration Transducers, 215–40. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9272-1_8.

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Bindal, Ahmet. "TTL Logic and CMOS-TTL Interface." In Electronics for Embedded Systems, 89–122. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-39439-8_4.

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Hehn, Thorsten, and Yiannos Manoli. "Analysis of Different Interface Circuits." In CMOS Circuits for Piezoelectric Energy Harvesters, 41–56. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9288-2_3.

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Maurath, Dominic, and Yiannos Manoli. "Input Load Adapting Charge Pump Interface." In CMOS Circuits for Electromagnetic Vibration Transducers, 159–97. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9272-1_6.

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Tokuda, Takashi, Toshihiko Noda, Kiyotaka Sasagawa, and Jun Ohta. "CMOS-Based Neural Interface Device for Optogenetics." In Optogenetics, 375–89. Tokyo: Springer Japan, 2015. http://dx.doi.org/10.1007/978-4-431-55516-2_27.

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Tokuda, Takashi, Makito Haruta, Kiyotaka Sasagawa, and Jun Ohta. "CMOS-Based Neural Interface Device for Optogenetics." In Advances in Experimental Medicine and Biology, 585–600. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8763-4_41.

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Thewes, Roland, Alexander Frey, Meinrad Schienle, Christian Paulus, Birgit Holzapfl, Martin Jenkner, Petra Schindler-Bauer, and Franz Hofmann. "CMOS Sensor Interface Arrays for DNA Detection." In Analog Circuit Design, 65–89. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-2805-2_4.

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Khadouri, Saleh H., Gerard C. M. Meijer, and Frank M. L. Van Der Goes. "A CMOS Interface for Thermocouples with Reference-Junction Compensation." In Smart Sensor Interfaces, 73–86. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6061-6_7.

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Conference papers on the topic "CMOS interface"

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Hei Wong, Hiroshi Iwai, and Kuniyuki Kakushima. "Material and interface instabilities of high-κ MOS gate dielectric films." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570990.

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Velayudhan, V., J. Martin-Martinez, R. Rodriguez, M. Porti, M. Nafria, X. Aymerich, C. Medina, and F. Gamiz. "TCAD simulation of interface traps related variability in bulk decananometer mosfets." In 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957078.

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Shiraishi, K., Y. Akasaka, K. Torii, T. Nakayama, S. Miyazaki, T. Nakaoka, H. Watanabe, et al. "New findings in nano-scale interface physics and their relations to nano-CMOS technologies." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570992.

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Aya Seike, Itsutaku Sano, Keisaku Yamada, and Iwao Ohdomari. "Evaluation of phosphorus diffusion in the confined nano-wire under the influence of Si/SiO2 interface." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570985.

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Benson, Niels, Marcus Ahles, Martin Schidleja, Andrea Gassmann, Eric Mankel, Thomas Mayer, Christian Melzer, Roland Schmechel, and Heinz von Seggern. "Organic CMOS technology by interface treatment." In SPIE Optics + Photonics, edited by Zhenan Bao and David J. Gundlach. SPIE, 2006. http://dx.doi.org/10.1117/12.680049.

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Abbott, Jeffrey, Tianyang Ye, Hongkun Park, and Donhee Ham. "CMOS interface with biological molecules and cells." In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC). IEEE, 2019. http://dx.doi.org/10.1109/esscirc.2019.8902832.

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Tokuda, Takashi, Jiawen Li, Mizuki Takeuchi, Masato Fukamachi, and Yasufumi Yokoshiki. "CMOS-based distributed implantable brain interface device." In 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS). IEEE, 2022. http://dx.doi.org/10.1109/newcas52662.2022.9842281.

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Waeny, Martin, and Peter Schwider. "CMOS megapixel digital camera with CameraLink interface." In Electronic Imaging 2002, edited by Morley M. Blouke, John Canosa, and Nitin Sampat. SPIE, 2002. http://dx.doi.org/10.1117/12.463420.

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Rifaan, Mochammad, and Robert Rieger. "Attenuating CMOS low-frequency capacitive sensor interface." In 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2017. http://dx.doi.org/10.1109/edssc.2017.8126408.

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Morell, William, and Ashok Srivastava. "Novel, Low-power ECRL-CMOS Interface Circuit." In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2019. http://dx.doi.org/10.1109/mwscas.2019.8885081.

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Reports on the topic "CMOS interface"

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Lim, Chee. High-performance Input/Output Circuit for CMOS Integrated Circuit Interface. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.7186.

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Sainudeen, Zuhail, and Navid Yazdi. Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem. Fort Belvoir, VA: Defense Technical Information Center, July 2001. http://dx.doi.org/10.21236/ada402437.

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Saripalli, Ganesh. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories. Office of Scientific and Technical Information (OSTI), January 2002. http://dx.doi.org/10.2172/806590.

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Li, Honghai, Lihwa Lin, Cody Johnson, Yan Ding, Mitchell Brown, Tanya Beck, Alejandro Sánchez, and Weiming Wu. A revisit and update on the verification and validation of the Coastal Modeling System (CMS) : report 1--hydrodynamics and waves. Engineer Research and Development Center (U.S.), September 2022. http://dx.doi.org/10.21079/11681/45444.

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This is the first part of a two-part report that revisits and updates the verification and validation (V&V) of the Coastal Modeling System (CMS). The V&V study in this part of the report focuses on hydrodynamic and wave modeling. With the updated CMS code (Version 5) and its latest graphical user interface, the Surface-water Modeling System (Version 13), the goal of this study is to revisit some early CMS V&V cases and assess some new cases on model performance in coastal applications. The V&V process includes the comparison and evaluation of the CMS output against analytical solutions, laboratory experiments in prototype cases, and field cases in and around coastal inlets and navigation projects. The V&V results prove that the basic physics incorporated are represented well, the computational algorithms implemented are accurate, and the coastal processes are reproduced well. This report provides the detailed descriptions of those test simulations, which include the model configuration, the selection of model parameters, the determination of model forcing, and the quantitative assessment of the model and data comparisons. It is to be hoped that, through the V&V process, the CMS users will better understand the model’s capability and limitation as a tool to solve real-world problems.
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Izhar, Shamay, Maureen Hanson, and Nurit Firon. Expression of the Mitochondrial Locus Associated with Cytoplasmic Male Sterility in Petunia. United States Department of Agriculture, February 1996. http://dx.doi.org/10.32747/1996.7604933.bard.

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The main goal of the proposed research was to continue the mutual investigations into the molecular basis of CMS and male fertility restoration [MRF], with the ultimate goal of understanding these phenomena in higher plants. The experiments focused on: (1) dissecting apart the complex CMS - specific mitochondrial S-Pcf locus, in order to distinguish its essential parts which cause sterility from other parts and study its molecular evolution. (2) Studying the expression of the various regions of the S-Pcf locus in fertile and sterile lines and comparing the structure and ultrastructure of sterile and fertile tissues. (3) Determine whether alteration in respiration is genetically associated with CMS. Our mutual investigations further substantiated the association between the S-Pcf locus and CMS by the findings that the fertile phenotype of a population of unstable petunia somatic hybrids which contain the S-Pcf locus, is due to the presence of multiple muclear fertility restoration genes in this group of progenies. The information obtained by our studies indicate that homologous recombination played a major role in the molecular evolution of the S-Pcf locus and the CMS trait and in the generation of mitochondrial mutations in general. Our data suggest that the CMS cytoplasm evolved by introduction of a urs-s containing sublimon into the main mitochondrial genome via homologous recombination. We have also found that the first mutation detected so far in S-Pcf is a consequence of a homologous recombination mechanism involving part of the cox2 coding sequence. In all the cases studied by us, at the molecular level, we found that fusion of two different cells caused mitochondrial DNA recombination followed by sorting out of a specific mtDNA population or sequences. This sequence of events suggested as a mechanism for the generation of novel mitochondrial genomes and the creation of new traits. The present research also provides data concerning the expression of the recombined and complex CMS-specific S-Pcf locus as compared with the expression of additional mitochondrial proteins as well as comparative histological and ultrastructural studies of CMS and fertile Petunia. Evidence is provided for differential localization of mitochondrially encoded proteins in situ at the tissue level. The similar localization patterns of Pcf and atpA may indicate that Pcf product could interfere with the functioning of the mitochondrial ATPase in a tissue undergoing meiosis and microsporogenesis. Studies of respiration in CMS and fertile Petunia lines indicate that they differe in the partitioning of electron transport through the cytochrome oxidase and alternative oxidase pathways. The data indicate that the electron flux through the two oxidase pathways differs between mitochondria from fertile and sterile Petunia lines at certain redox states of the ubiquinone pool. In summary, extensive data concerning the CMS-specific S-Pcf locus of Petunia at the DNA and protein levels as well as information concerning different biochemical activity in CMS as compared to male fertile lines have been accumulated during the three years of this project. In addition, the involvement of the homologous recombination mechanism in the evolution of mt encoded traits is emphasized.
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Chapman, Ray, Phu Luong, Sung-Chan Kim, and Earl Hayter. Development of three-dimensional wetting and drying algorithm for the Geophysical Scale Transport Multi-Block Hydrodynamic Sediment and Water Quality Transport Modeling System (GSMB). Engineer Research and Development Center (U.S.), July 2021. http://dx.doi.org/10.21079/11681/41085.

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The Environmental Laboratory (EL) and the Coastal and Hydraulics Laboratory (CHL) have jointly completed a number of large-scale hydrodynamic, sediment and water quality transport studies. EL and CHL have successfully executed these studies utilizing the Geophysical Scale Transport Modeling System (GSMB). The model framework of GSMB is composed of multiple process models as shown in Figure 1. Figure 1 shows that the United States Army Corps of Engineers (USACE) accepted wave, hydrodynamic, sediment and water quality transport models are directly and indirectly linked within the GSMB framework. The components of GSMB are the two-dimensional (2D) deep-water wave action model (WAM) (Komen et al. 1994, Jensen et al. 2012), data from meteorological model (MET) (e.g., Saha et al. 2010 - http://journals.ametsoc.org/doi/pdf/10.1175/2010BAMS3001.1), shallow water wave models (STWAVE) (Smith et al. 1999), Coastal Modeling System wave (CMS-WAVE) (Lin et al. 2008), the large-scale, unstructured two-dimensional Advanced Circulation (2D ADCIRC) hydrodynamic model (http://www.adcirc.org), and the regional scale models, Curvilinear Hydrodynamics in three dimensions-Multi-Block (CH3D-MB) (Luong and Chapman 2009), which is the multi-block (MB) version of Curvilinear Hydrodynamics in three-dimensions-Waterways Experiments Station (CH3D-WES) (Chapman et al. 1996, Chapman et al. 2009), MB CH3D-SEDZLJ sediment transport model (Hayter et al. 2012), and CE-QUAL Management - ICM water quality model (Bunch et al. 2003, Cerco and Cole 1994). Task 1 of the DOER project, “Modeling Transport in Wetting/Drying and Vegetated Regions,” is to implement and test three-dimensional (3D) wetting and drying (W/D) within GSMB. This technical note describes the methods and results of Task 1. The original W/D routines were restricted to a single vertical layer or depth-averaged simulations. In order to retain the required 3D or multi-layer capability of MB-CH3D, a multi-block version with variable block layers was developed (Chapman and Luong 2009). This approach requires a combination of grid decomposition, MB, and Message Passing Interface (MPI) communication (Snir et al. 1998). The MB single layer W/D has demonstrated itself as an effective tool in hyper-tide environments, such as Cook Inlet, Alaska (Hayter et al. 2012). The code modifications, implementation, and testing of a fully 3D W/D are described in the following sections of this technical note.
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