Journal articles on the topic 'CMOS Device and Integration'
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1
Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.
Abstract:
A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.
2
Krupar, Joerg, Heiko Hauswald, and Ronny Naumann. "A Substrate Current Less Control Method for CMOS Integration of Power Bridges." Advances in Power Electronics 2010 (September 23, 2010): 1–11. http://dx.doi.org/10.1155/2010/909612.
Abstract:
Modern electronical devices use high integration to decrease device size and cost and to increase reliability. More and more devices appear that integrate even power devices into VLSI circuits. When driving inductive loads, this is a critical step because freewheeling at a power device appears. In these applications usually special technologies with extra wells for the power devices, SOI technologies, or BiCMOS technologies are required to suppress any substrate current. However, the use of these technologies results in higher production cost for the device. We present a method to control the freewheeling actively. Using this approach we are able to integrate the power devices using a normal CMOS technology.
3
Kogut, Igor T., Victor I. Holota, Anatoly Druzhinin, and V. V. Dovhij. "The Device-Technological Simulation of Local 3D SOI-Structures." Journal of Nano Research 39 (February 2016): 228–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.39.228.
Abstract:
This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.
4
Leenheer, Andrew, Connor Halsey, Daniel Ward, Deanna Campbell, John S. Mincey, Evan M. Anderson, Scott W. Schmucker, et al. "Atomic-scale Dopant Integration During CMOS Device Fabrication." ECS Meeting Abstracts MA2021-02, no. 30 (October 19, 2021): 918. http://dx.doi.org/10.1149/ma2021-0230918mtgabs.
5
Huey, Sidney, Balaji Chandrasekaran, Doyle Bennett, Stan Tsai, Kun Xu, Jun Qian, Siva Dhandapani, Jeff David, Bogdan Swedek, and Lakshmanan Karuppiah. "CMP Process Control for Advanced CMOS Device Integration." ECS Transactions 44, no. 1 (December 15, 2019): 543–52. http://dx.doi.org/10.1149/1.3694367.
6
Perez-Bosch Quesada, E., E. Perez, M. Kalishettyhalli Mahadevaiah, and C. Wenger. "Memristive-based in-memory computing: from device to large-scale CMOS integration." Neuromorphic Computing and Engineering 1, no. 2 (November 18, 2021): 024006. http://dx.doi.org/10.1088/2634-4386/ac2cd4.
Abstract:
Abstract With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO 2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal–insulator–metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.
7
Kitchen, Jennifer, Soroush Moallemi, and Sumit Bhardwaj. "Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000339–82. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_010.
Abstract:
Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.
8
Tabata, Toshiyuki, Fabien Rozé, Louis Thuries, Sébastien Halty, Pierre-Edouard Raynal, Imen Karmous, and Karim Huet. "Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices." Electronics 11, no. 17 (August 23, 2022): 2636. http://dx.doi.org/10.3390/electronics11172636.
Abstract:
The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.
9
Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.
Abstract:
AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.
10
Ostling, Mikael, and Per-Erik Hellstrom. "(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS." ECS Meeting Abstracts MA2023-02, no. 30 (December 22, 2023): 1511. http://dx.doi.org/10.1149/ma2023-02301511mtgabs.
Abstract:
In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors. In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers. A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistors Fully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices. 3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type. 3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.
11
Jacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.
Abstract:
The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.
12
Alexandru, Mihaela, Viorel Banu, Matthieu Florentin, Xavier Jordá, Miguel Vellvehi, and Dominique Tournier. "High Temperature Electrical Characterization of 4H-SiC MESFET Basic Logic Gates." Materials Science Forum 778-780 (February 2014): 1130–34. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.1130.
Abstract:
Due to our demonstrated stable Tungsten-Schottky barrier at elevated temperatures, and also thanks to our technological process maturity regarding SiC-Schottky contact fabrication, we have implemented the digital logic gates library adopting a normally-on MESFET topology. In this paper we present new experimental results showing the thermal behavior up to 300oC of 4H-SiC logic gates library, monolithically integrating normally-on MESFETs and epitaxial resistors. The implemented SiC devices are based on important CMOS features and are specially designed for large ICs device integration density.
13
Takenaka, Mitsuru, and Shinichi Takagi. "III-V/Ge Device Engineering for CMOS Photonics." Materials Science Forum 783-786 (May 2014): 2028–33. http://dx.doi.org/10.4028/www.scientific.net/msf.783-786.2028.
Abstract:
Heterogeneous integration of III-V compound semiconductors and Ge on the Si platform is one of the promising technologies for enhancing the performance of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 10-nm technology node because of their high carrier mobilities. In addition, the III-Vs and Ge are also promising materials for photonic devices. Thus, we have investigated III-V/Ge device engineering for CMOS photonics, enabling monolithic integration of high-performance III-V/Ge CMOS transistors and III-V/Ge photonics on Si. The direct wafer bonding of III-V on Si has been investigated to form III-V on Insulator for III-V CMOS photonics. Extremely-thin-body InGaAs MOSFETs with the gate length of approximately 55 nm have successfully been demonstrated by using the wafer bonding. InP-based photonic-wire waveguide devices including micro bends, arrayed waveguide gratings, grating couplers, optical switches, and InGaAs photodetectors have also been demonstrated on the III-V-OI wafer. The gate stack formation on Ge is one of the critical issues for Ge MOSFETs. Recently, we have successfully demonstrated high-quality GeOx/Ge MOS interfaces formed by thermal oxidation and plasma oxidation. High-performance Ge pMOSFET and nMOSFET with thin EOT have been obtained using the GeOx/Ge MOS interfaces. We have also demonstrated that GeOx surface passivation is effective to reduce the dark current of Ge photodetectors in conjunction with gas-phase doped junction. We have also investigated strained SiGe optical modulators. We expect that compressive strain in SiGe enhances modulation efficiency, and an extremely small VπL of 0.033 V-cm is predicted. III-V/Ge heterogeneous integration is one of the promising ways for achieving ultrahigh performance electronic-photonic integrated circuits.
14
Kim, Hyejin, Geonhui Han, Seojin Cho, Jiyong Woo, and Daeseok Lee. "Internal Resistor Effect of Multilayer-Structured Synaptic Device for Low-Power Operation." Nanomaterials 14, no. 2 (January 16, 2024): 201. http://dx.doi.org/10.3390/nano14020201.
Abstract:
A synaptic device with a multilayer structure is proposed to reduce the operating power of neuromorphic computing systems while maintaining a high-density integration. A simple metal–insulator–metal (MIM)-structured multilayer synaptic device is developed using an 8-inch wafer-based and complementary metal–oxide–semiconductor (CMOS) fabrication process. The three types of MIM-structured synaptic devices are compared to assess their effects on reducing the operating power. The obtained results exhibited low-power operation owing to the inserted layers acting as an internal resistor. The modulated operational conductance level and simple MIM structure demonstrate the feasibility of implementing both low-power operation and high-density integration in multilayer synaptic devices.
15
Mols, Yves, Abhitosh Vais, Sachin Yadav, Liesbeth Witters, Komal Vondkar, Reynald Alcotte, Marina Baryshnikova, et al. "Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate." Materials 14, no. 19 (September 29, 2021): 5682. http://dx.doi.org/10.3390/ma14195682.
Abstract:
Nano-ridge engineering (NRE) is a novel method to monolithically integrate III–V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 106∙cm−2 in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices—consisting of several nano-ridges in parallel—were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency ft of ~17 GHz was achieved. These results show the potential of NRE III–V devices for hybrid III–V/CMOS technology for emerging RF applications.
16
Sebaai, Farid, Jose Ignacio Del Agua Borniquel, Rita Vos, Philippe Absil, Thomas Chiarella, Christa Vrancken, Pieter Boelen, and Evans Baiya. "Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme." Solid State Phenomena 145-146 (January 2009): 207–10. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.207.
Abstract:
With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].
17
Smith, A., Qi Li, Agin Vyas, Mohammad Haque, Kejian Wang, Andres Velasco, Xiaoyan Zhang, et al. "Carbon-Based Electrode Materials for Microsupercapacitors in Self-Powering Sensor Networks: Present and Future Development." Sensors 19, no. 19 (September 29, 2019): 4231. http://dx.doi.org/10.3390/s19194231.
Abstract:
There is an urgent need to fulfill future energy demands for micro and nanoelectronics. This work outlines a number of important design features for carbon-based microsupercapacitors, which enhance both their performance and integration potential and are critical for complimentary metal oxide semiconductor (CMOS) compatibility. Based on these design features, we present CMOS-compatible, graphene-based microsupercapacitors that can be integrated at the back end of the line of the integrated circuit fabrication. Electrode materials and their interfaces play a crucial role for the device characteristics. As such, different carbon-based materials are discussed and the importance of careful design of current collector/electrode interfaces is emphasized. Electrode adhesion is an important factor to improve device performance and uniformity. Additionally, doping of the electrodes can greatly improve the energy density of the devices. As microsupercapacitors are engineered for targeted applications, device scaling is critically important, and we present the first steps toward general scaling trends. Last, we outline a potential future integration scheme for a complete microsystem on a chip, containing sensors, logic, power generation, power management, and power storage. Such a system would be self-powering.
18
Wada, Kazumi. "A New Approach of Electronics and Photonics Convergence on Si CMOS Platform: How to Reduce Device Diversity of Photonics for Integration." Advances in Optical Technologies 2008 (July 7, 2008): 1–7. http://dx.doi.org/10.1155/2008/807457.
Abstract:
Integrated photonics via Si CMOS technology has been a strategic area since electronics and photonics convergence should be the next platform for information technology. The platform is recently referred to as “Si photonics” that attracts much interest of researchers in industries as well as academia in the world. The main goal of Si Photonics is currently to reduce material diversity of photonic devices to pursuing CMOS-compatibility. In contrast, the present paper proposes another route of Si Photonics, reducing diversity of photonic devices. The proposed device unifying functionality of photonics is a microresonator with a pin diode structure that enables the Purcell effect and Franz-Keldysh effect to emit and to modulate light from SiGe alloys.
19
Köck, Anton, Marco Deluca, Florentyna Sosada-Ludwikowska, Günther Maier, Robert Wimmer Teubenbacher, Martin Sagmeister, Karl Rohracher, et al. "Heterogeneous Integration of Metal Oxides—Towards a CMOS Based Multi Gas Sensor Device." Proceedings 14, no. 1 (June 19, 2019): 5. http://dx.doi.org/10.3390/proceedings2019014005.
20
Ostling, Mikael, and Per-Erik Hellstrom. "(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS." ECS Transactions 112, no. 1 (September 29, 2023): 13–24. http://dx.doi.org/10.1149/11201.0013ecst.
Abstract:
To keep the scaling progress going, we must go three dimensional (3D). This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connecting them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature than today’s Si CMOS technology. Here, we have focused on Ge based transistors, which have an inherently lower process temperature compared to Si transistors. Several technological and design breakthroughs towards realizing Ge based sequential 3D circuits are discussed.
21
Mulberry, Geoffrey, Kevin A. White, Matthew A. Crocker, and Brian N. Kim. "A 512-Ch Dual-Mode Microchip for Simultaneous Measurements of Electrophysiological and Neurochemical Activities." Biosensors 13, no. 5 (April 26, 2023): 502. http://dx.doi.org/10.3390/bios13050502.
Abstract:
In the study of the brain, large and high-density microelectrode arrays have been widely used to study the behavior of neurotransmission. CMOS technology has facilitated these devices by enabling the integration of high-performance amplifiers directly on-chip. Usually, these large arrays measure only the voltage spikes resulting from action potentials traveling along firing neuronal cells. However, at synapses, communication between neurons occurs by the release of neurotransmitters, which cannot be measured on typical CMOS electrophysiology devices. Development of electrochemical amplifiers has resulted in the measurement of neurotransmitter exocytosis down to the level of a single vesicle. To effectively monitor the complete picture of neurotransmission, measurement of both action potentials and neurotransmitter activity is needed. Current efforts have not resulted in a device that is capable of the simultaneous measurement of action potential and neurotransmitter release at the same spatiotemporal resolution needed for a comprehensive study of neurotransmission. In this paper, we present a true dual-mode CMOS device that fully integrates 256-ch electrophysiology amplifiers and 256-ch electrochemical amplifiers, along with an on-chip 512 electrode microelectrode array capable of simultaneous measurement from all 512 channels.
22
Dunai, L., G. Peris-Fajarnés, E. Lluna, and B. Defez. "Sensory Navigation Device for Blind People." Journal of Navigation 66, no. 3 (January 25, 2013): 349–62. http://dx.doi.org/10.1017/s0373463312000574.
Abstract:
This paper presents a new Electronic Travel Aid (ETA) ‘Acoustic Prototype’ which is especially suited to facilitate the navigation of visually impaired users. The device consists of a set of 3-Dimensional Complementary Metal Oxide Semiconductor (3-D CMOS) image sensors based on the three-dimensional integration and Complementary Metal-Oxide Semiconductor (CMOS) processing techniques implemented into a pair of glasses, stereo headphones as well as a Field-Programmable Gate Array (FPGA) used as processing unit. The device is intended to be used as a complementary device to navigation through both open known and unknown environments. The FPGA and the 3D-CMOS image sensor electronics control object detection. Distance measurement is achieved by using chip-integrated technology based on the Multiple Short Time Integration method. The processed information of the object distance is presented to the user via acoustic sounds through stereophonic headphones. The user interprets the information as an acoustic image of the surrounding environment. The Acoustic Prototype transforms the surface of the objects of the real environment into acoustical sounds. The method used is similar to a bat's acoustic orientation. Having good hearing ability, with few weeks training the users are able to perceive not only the presence of an object but also the object form (that is, if the object is round, if it has corners, if it is a car or a box, if it is a cardboard object or if it is an iron or cement object, a tree, a person, a static or moving object). The information is continuously delivered to the user in a few nanoseconds until the device is shut down, helping the end user to perceive the information in real time.
23
Wan Muhamad Hatta, Sharifah Fatmadiana, Dayanasari Abdul Hadi, and Norhayati Soin. "Laser Anneal-Induced Effects on the NBTI Degradation of Advanced-Process 45nm High-K PMOS." Advanced Materials Research 189-193 (February 2011): 1862–66. http://dx.doi.org/10.4028/www.scientific.net/amr.189-193.1862.
Abstract:
This paper presents the effects imposed on the reliability of advanced-process CMOS devices, specifically the NBTI degradation, subsequent to the integration of laser annealing (LA) in the process flow of a 45nm HfO2/TiN gate stack PMOS device. The laser annealing temperatures were varied from 900°C to 1350°C. The effects imposed on the NBTI degradation of the device were comprehensively analyzed in which the shifts of the threshold voltage and drain current degradation were observed. The analysis was extended to the effects of the conventional RTA as opposed to the advanced laser annealing process. It was observed that the incorporation of laser annealing in the process flow of the device enhances the NBTI degradation rate of the device, in contrast to the integration of the conventional RTA. Laser annealing subsequent to spike-anneal is observed to improve the reliability performance of the transistor at high negative biases.
24
WANG, YANGYUAN, RU HUANG, JINFENG KANG, and SHENGDONG ZHANG. "HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 147–73. http://dx.doi.org/10.1142/s012915640600359x.
Abstract:
In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.
25
Thomas, Dave, Jean Michailos, Nicolas Hotellier, Gilles Metellus, Francois Guyader, Alain Inard, Keith Buchanan, Dorleta Cortaberria Sanz, Yiping Song, and Tony Wilby. "Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 000539–56. http://dx.doi.org/10.4071/2010dpc-ta14.
Abstract:
One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at <200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage >8 MVcm−1 and leakage current <1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls. Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.
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Takagi, Shinichi, Masafumi Yokoyama, Sang-Hyeon Kim, Rui Zhang, and Mitsuru Takenaka. "(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS." ECS Transactions 41, no. 7 (December 16, 2019): 203–18. http://dx.doi.org/10.1149/1.3633300.
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Song, Boxin. "Metal Oxide Neural Devices and Their Applications." Highlights in Science, Engineering and Technology 87 (March 26, 2024): 226–31. http://dx.doi.org/10.54097/zwgj1t76.
Abstract:
Metallic oxide neurons are a potential candidate for future applications in neuroscience and neuroscience, where they can be used as a model for simulating synaptic functions in biology. This paper mainly introduces two kinds of oxide-based memristors: memristor and neural transistor, as well as briefly discuss their integration. Because of the two devices’ simple structure, similar to synaptic structure, high efficiency, low power consumption, high-density integration, compatibility with CMOS process conditions, and continuous control of conductance, it is considered to be the first choice for brain-like computing hardware. And the memristor can realize the integration of computing and storage functions in a single device. However, some problems and challenges still exist in memristor application. In the process of the device, there is a problem of insufficient miniaturization, because of the influence of leakage current, which limits the integration of the array and increases the operation energy consumption. In conclusion, despite their significant barriers before becoming commercially viable, their promising future is certain.
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Hall, Steve, and Bill Eccleston. "Silicon-germanium for ULSI." Journal of Telecommunications and Information Technology, no. 3-4 (December 30, 2000): 3–9. http://dx.doi.org/10.26636/jtit.2000.3-4.33.
Abstract:
The paper describes recent progress for the introduction of silicon-germanium, bipolar and field effect heterostructure transistors into mainstream integrated circuit application. Basic underlying concepts and device architectures which give rise to the desired performance advantages are described together with the latest state-of the-art results for HBT and MOSFET devices. The integration of such devices into viable HBT, BiCMOS and CMOS is reviewed. Other contributions that SiGe can make to enhance the performance of ULSI circuits are mentioned also.
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Sánchez-Chiva, Josep Maria, Juan Valle, Daniel Fernández, and Jordi Madrenas. "A CMOS-MEMS BEOL 2-axis Lorentz-Force Magnetometer with Device-Level Offset Cancellation." Sensors 20, no. 20 (October 19, 2020): 5899. http://dx.doi.org/10.3390/s20205899.
Abstract:
Lorentz-force Microelectromechanical Systems (MEMS) magnetometers have been proposed as a replacement for magnetometers currently used in consumer electronics market. Being MEMS devices, they can be manufactured in the same die as accelerometers and gyroscopes, greatly reducing current solutions volume and costs. However, they still present low sensitivities and large offsets that hinder their performance. In this article, a 2-axis out-of-plane, lateral field sensing, CMOS-MEMS magnetometer designed using the Back-End-Of-Line (BEOL) metal and oxide layers of a standard CMOS (Complementary Metal–Oxide–Semiconductor) process is proposed. As a result, its integration in the same die area, side-by-side, not only with other MEMS devices, but with the readout electronics is possible. A shielding structure is proposed that cancels out the offset frequently reported in this kind of sensors. Full-wafer device characterization has been performed, which provides valuable information on device yield and performance. The proposed device has a minimum yield of 85.7% with a good uniformity of the resonance frequency fr¯=56.8 kHz, σfr=5.1 kHz and quality factor Q¯=7.3, σQ=1.6 at ambient pressure. Device sensitivity to magnetic field is 37.6fA·μT−1 at P=1130 Pa when driven with I=1mApp.
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Zhang, Zhao Yun, Zhi Gui Shi, Zhen Chuan Yang, and Bo Peng. "MEMS Monolithic Integration Technology." Key Engineering Materials 562-565 (July 2013): 1387–92. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.1387.
Abstract:
The monolithic integrated technology of MEMS was discussed. First discussed the advantages and difficulties faced by the MEMS monolithic integration technology. Second the features and the process of the mainstream MEMS monolithic integration technology was introduced. And finally put forward a SOI MEMS monolithic integration technology, the technology with no high-temperature process, Post-CMOS integrated solution, compatible with the CMOS process. This technology can achieve high aspect ratio, high-performance micro-inertial devices..
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Soh, Mei, T. Teo, S. Selvaraj, Lulu Peng, Don Disney, and Kiat Yeo. "Heterogeneous Integration of GaN and BCD Technologies." Electronics 8, no. 3 (March 22, 2019): 351. http://dx.doi.org/10.3390/electronics8030351.
Abstract:
Light-emitting diodes (LEDs) are solid-state devices that are highly energy efficient, fast switching, have a small form factor, and can emit a specific wavelength of light. The ability to precisely control the wavelength of light emitted with the fabrication process enables LEDs to not only provide illumination, but also find applications in biology and life science research. To enable the new generation of LED devices, methods to improve the energy efficiency for possible battery operation and integration level for miniaturized lighting devices should be explored. This paper presents the first case of the heterogeneous integration of gallium nitride (GaN) power devices, both GaN LED and GaN transistor, with bipolar CMOS DMOS (BCD) circuits that can achieve this. To validate this concept, an LED driver was designed, implemented and verified experimentally. It features an output electrical power of 1.36 W and compact size of 2.4 × 4.4 mm2. The designed fully integrated LED lighting device emits visible light at a wavelength of approximately 454 nm and can therefore be adopted for biology research and life science applications.
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Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.
Abstract:
AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.
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Joubert, James, and Deepak Sharma. "Using CMOS Cameras for Light Microscopy." Microscopy Today 19, no. 4 (July 2011): 22–28. http://dx.doi.org/10.1017/s155192951100054x.
Abstract:
The push in consumer electronics over past decades has been toward smaller, faster, and cheaper products but with same or improved capabilities. The consumer imaging world has been no exception with the integration, for example, of functional complementary metal-oxide-semiconductor (CMOS) cameras into ever smaller cellular phones. The CMOS sensors have continued to develop and improve with increasing numbers of smaller, more sensitive pixels with larger photo-response capacity providing higher dynamic range. This technological expansion has inevitably spilled over into even the scientific imaging world, such as in biological light microscopy. This advancement of consumer CMOS digital camera technology invites comparison of CMOS cameras with the current standard charge coupled device (CCD) cameras in scientific imaging.
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Kumar, K. R. Lakshmi, R. A. Hadaway, M. A. Copeland, and M. I. H. King. "A precision design technique for analog very large scale integration." Canadian Journal of Physics 63, no. 6 (June 1, 1985): 702–6. http://dx.doi.org/10.1139/p85-109.
Abstract:
A study of the matching characteristics of components available in a CMOS VLSI technology is reported. This examination has been extended to produce a design methodology for precision analog functions in VLSI by choosing a digital-to-analog converter as an example. The major emphasis of the paper will be on the device and technological aspects of the design approach.
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Hadizadeh, Rameen, Anssi Laitinen, Niko Kuusniemi, Volker Blaschke, David Molinero, Eoin O'Toole, and Márcio Pinheiro. "Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000051–55. http://dx.doi.org/10.4071/2380-4505-2019.1.000051.
Abstract:
Abstract Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on 180nm high-voltage CMOS silicon was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). The primary objective of this study was to determine the manufacturability of this System-in-Package (SiP) design, which is proven at time zero through survival of the MEMS device based on acceptable MEMS performance metrics. In addition, the RF SOI switch provides high-voltage electrostatic discharge (ESD) protection for the MEMS device. Capacitive MEMS structures are particularly sensitive to unpredictable electrostatic charging scenarios, such as handling after package assembly and printed circuit board (PCB) surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only enables the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity.
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Khaja, Fareen Adeni. "Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations." MRS Advances 4, no. 48 (2019): 2559–76. http://dx.doi.org/10.1557/adv.2019.416.
Abstract:
ABSTRACTAs advanced CMOS scaling with FinFETs continues beyond the 10/7nm nodes, contact resistance (Rc) remains a dominant component affecting device performance. The FinFET Source/Drain (S/D) contact area has become smaller with fin pitch scaling, resulting in drastically increased Rc. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes, it is critical to continue to reduce contact resistivity (ρc) < 1.0x10-9 Ω.cm2 for both NMOS and PMOS. In this paper, we review the recent trends for ρc reduction for advanced CMOS devices and discuss approaches that have demonstrated reduction in ρc, such as in-situ heavily doped epitaxial films for S/D, advanced ion implantation and laser anneals. The implant techniques include pre-amorphization implants (PAI), dopant boosting implants, cryogenic (-100°C) implants for damage engineering and plasma doping (PLAD) for conformal doping of high aspect ratio (HAR) contacts. With such high levels of doping from epi and implants, advanced laser anneals are key for epitaxial regrowth and formation of metastable alloys for dopant supersaturation or segregation in top layers. Millisecond laser anneal (MSA) improves dopant activation and nanosecond laser anneal (NLA) permits superactivation, and both have become key enablers for ρc reduction. This paper also reviews two alternative contact approaches: dual silicide scheme and wrap-around contact (WAC), as potential pathways to further reduce Rc for advanced CMOS nodes.
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Fan, Zhihua, Qinling Deng, Xiaoyu Ma, and Shaolin Zhou. "Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration." Materials 14, no. 5 (March 7, 2021): 1272. http://dx.doi.org/10.3390/ma14051272.
Abstract:
In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.
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Li, Zhichao, Shiheng Yang, Samuel B. S. Lee, and Kiat Seng Yeo. "A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology." Electronics 9, no. 12 (December 20, 2020): 2198. http://dx.doi.org/10.3390/electronics9122198.
Abstract:
For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.
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Deshpande, V. V., V. Djara, D. Caimi, E. O'Connor, M. Sousa, L. Czornomaz, and J. Fompeyrine. "(Invited) Material and Device Integration for Hybrid III-V/SiGe CMOS Technology." ECS Transactions 69, no. 10 (October 2, 2015): 131–42. http://dx.doi.org/10.1149/06910.0131ecst.
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Filipovic, Lado, and Siegfried Selberherr. "Thermo-Electro-Mechanical Simulation of Semiconductor Metal Oxide Gas Sensors." Materials 12, no. 15 (July 28, 2019): 2410. http://dx.doi.org/10.3390/ma12152410.
Abstract:
There is a growing demand in the semiconductor industry to integrate many functionalities on a single portable device. The integration of sensor fabrication with the mature CMOS technology has made this level of integration a reality. However, sensors still require calibration and optimization before full integration. For this, modeling and simulation is essential, since attempting new, innovative designs in a laboratory requires a long time and expensive tests. In this manuscript we address aspects for the modeling and simulation of semiconductor metal oxide gas sensors, devices which have the highest potential for integration because of their CMOS-friendly fabrication capability and low operating power. We analyze recent advancements using FEM models to simulate the thermo-electro-mechanical behavior of the sensors. These simulations are essentials to calibrate the design choices and ensure low operating power and improve reliability. The primary consumer of power is a microheater which is essential to heat the sensing film to appropriately high temperatures in order to initiate the sensing mechanism. Electro-thermal models to simulate its operation are presented here, using FEM and the Cauer network model. We show that the simpler Cauer model, which uses an electrical circuit to model the thermo-electrical behavior, can efficiently reproduce experimental observations.
41
Zhang, Yinxing, Ziliang Fang, and Xiaobing Yan. "HfO2-based memristor-CMOS hybrid implementation of artificial neuron model." Applied Physics Letters 120, no. 21 (May 23, 2022): 213502. http://dx.doi.org/10.1063/5.0091286.
Abstract:
Memristors with threshold switching behavior are increasingly used in the study of neuromorphic computing, which are frequently used to simulate synaptic functions due to their high integration and simple structure. However, building a neuron circuit to simulate the characteristics of biological neurons is still a challenge. In this work, we demonstrate a leaky integrate-and-fire model of neurons, which is presented by a memristor-CMOS hybrid circuit based on a threshold device of a TiN/HfO2/InGaZnO4/Si structure. Moreover, we achieve multiple neural functions based on the neuron model, including leaky integration, threshold-driven fire, and strength-modulated spike frequency characteristics. This work shows that HfO2-based threshold devices can realize the basic functions of spiking neurons and have great potential in artificial neural networks.
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Belhassen, Jérémy, Zeev Zalevsky, and Avi Karsenty. "Optical Polarization Sensitive Ultra-Fast Switching and Photo-Electrical Device." Nanomaterials 9, no. 12 (December 7, 2019): 1743. http://dx.doi.org/10.3390/nano9121743.
Abstract:
Ultra-fast electrical switches activated with an optical-polarized light trigger, also called photo-polarized activated electrical switches, are presented. A set of new transistor circuits is switched by light from above, illuminating deep V-grooves, whose angle is sensitive to the polarization of the incident. Thus, this application may serve for encryption/decryption devices since the strongest electrical responsivity is only obtained for very specific spatial polarization directions of the illumination beam. When this V-groove is sufficiently narrow, the device mainly responds to one polarization and not to the other. In such a way, electrons are generated only for one specific polarization. While the nature of the data remains electronic, the modulation control is optic, creating a photo-induced current depending on the polarization direction. This coupled device acts as a polarization modulator as well as an intensity modulator. The article focuses on the integration of several devices in different configurations of circuitry: dual, triple, and multi-element. Case studies of several adjacent devices are presented with varying critical variables, such as the V-groove aperture dimensions. Analytical models and complementary numerical analyses are presented for the future smooth integration into Complementary Metal-Oxide-Semiconductor (CMOS) technology.
43
Mori, Takahiro. "(Invited, Digital Presentation) Silicon Compatible Quantum Computers: Challenges in Devices, Integration, and Circuits." ECS Meeting Abstracts MA2022-01, no. 29 (July 7, 2022): 1297. http://dx.doi.org/10.1149/ma2022-01291297mtgabs.
Abstract:
Quantum computers have been attractive because they could realize large-scale and highly complicated calculations that conventional computers cannot solve within a finite time. The large-scale integration of qubits, which are the building block of quantum computers, is required to realize their practical application. Indeed, fault-tolerant quantum computers require the integration of one million qubits. Therefore, silicon qubits is a high-profile candidate because they have advanced process and miniaturization technologies developed with VLSI. In addition, silicon qubits are advantageous in operation temperature. Superconductor qubits operate at the cryogenic temperature at around a few tens mK; in contrast, the operation principle of silicon qubits can operate at a much higher temperature over 1 K. The high-temperature operation can realize quantum computers with small and high-power refrigerators; therefore, we can expect desktop quantum computers instead of ongoing supercomputer-size ones. We must promote integration technology development for silicon qubits; however, the silicon qubit research was mainly in the physics field. Then, nowadays, the integration technology development is accelerated in the world. The challenges are in all conventional research fields: devices, integration, and circuits. We must re-develop the silicon technologies for quantum. For example, on the device design, now we do not have a good tool to design the qubits like TCAD; therefore, we must re-develop the TCAD technologies for quantum [1]. Actually, this is the starting point of our recent research activities; we are going to develop a quantum device simulator, clarify the requirements on the fabrication process of silicon qubits, and propose new technologies to reduce the variability to realize large-scale integration [2]. As for the integration, the quantum calculation circuits require several integrated items: qubits, qubit couplers, micro-magnets, and readout systems. The situation is quite different from the conventional VLSI case for which only the transistors should be integrated. Therefore, we must go re-developing new technologies to integrate all these items. Regarding the circuits, we must use CMOS circuits to generate input signals for qubits and readout the results of quantum calculation, which should be operated at cryogenic temperature. This is so-called “cryo-CMOS.” We must explore a new side of the transistor technologies, which is not investigated so far, because the physics of the MOSFET operation is quite different from the conventional room-temperature operation, hampering the circuit design due to the lack of the device operation model. In this situation, despite the long history of MOSFETs, new phenomena of transistor operation are discovered. For example, the low-frequency current noise increases at a low temperature. The origin of the noise is on the interface traps, instead of the fixed charges in the gate oxides as is the case for room temperature operation [3]. Therefore, we must re-developing CMOS circuit technologies from the bottom of the technologies, device physics. In this presentation, I’m going to overview the status of silicon technology developments for quantum from the viewpoints of devices, integration, and circuits. Also, we introduce some of our recent results to contribute to the developments. Acknowledgment: Our work is supported by MEXT Quantum Leap Flagship Program (Q-LEAP) JPMXS0118069228. [1] H. Asai et al., IEEE Electron Devices Technology and Manufacturing Conference 2021. [2] S. Iizuka et al., Tech. Dig. Symp. VLSI Technology 2021. [3] H. Oka et al., Tech. Dig. Symp. VLSI Technology 2020.
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Kluba, Marta, Bruno Morana, Angel Savov, Henk van Zeijl, Gregory Pandraud, and Ronald Dekker. "Wafer-Scale Integration for Semi-Flexible Neural Implant Miniaturization." Proceedings 2, no. 13 (December 10, 2018): 941. http://dx.doi.org/10.3390/proceedings2130941.
Abstract:
We present a novel, wafer-based fabrication process that enables integration and assembly of electronic components, such as ASICs and decoupling capacitors, with flexible interconnects. The electronic components are fabricated in, or placed on precisely defined and closely-spaced silicon islands that are connected by interconnects embedded in parylene-based flexible thin film. This fully CMOS compatible approach uses optimized DRIE processes and an SiO2 mesh-shaped mask, allowing for the simultaneous definition of micrometer- to millimeter-sized structures without compromising the flexibility of the device. In a single fabrication flow a unique freedom in dimensions of both the flexible film and the silicon islands can be achieved making this new technique ideal for the realization of semi-flexible/foldable implantable devices, where structures of different sizes have to be combined together for the ultimate miniaturization.
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Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.
Abstract:
Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.
46
Buchbinder, Miryam, Ora Eli, Sagie Rozental, Yami Bouhnik, Shimon Greenberg, Krish Mani, Yifat Cohen, Ken Mackay, Jeremy Pereira, and Jeremy Alvarez Herault. "Integrating MTJ Devices into a 130nm CMOS Process Flow." Advances in Science and Technology 99 (October 2016): 81–89. http://dx.doi.org/10.4028/www.scientific.net/ast.99.81.
Abstract:
A Magnetic Random Access Memory (MRAM) device was successfully embedded into TowerJazz’s 130nm CMOS platform. The fabricated devices are stand-alone 4Mbit and 1Mbit MRAM memories and Multi-MLU magnetic sensors. This paper will describe the process development challenges in adapting a standard 130nm Cu BEOL to incorporate the magnetic cell element, and the device sensitivities to processing.The main process challenges to be discussed are 1) formation of shallow damascene Cu contacts to the lower electrode; 2) patterning of the 150nm magnetic cell both lithography and etching of the magnetic stack; 3) planarization of the topography from the magnetic cell; 4) formation of dual damascene VIA’s to both the magnetic cell upper electrode and to the CMOS. Some electrical yield results of the stand-alone MRAM memory and magnetic sensors will be presented. This project was a collaborative effort between TowerJazz and Crocus Technology
47
Sebaai, Farid, Liesbeth Witters, Frank Holsteyns, Yoshida Yukifumi, Paul W. Mertens, and Stefan De Gendt. "Nickel Selective Etch for Contacts on Ge Based Devices." Solid State Phenomena 219 (September 2014): 105–8. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.105.
Abstract:
of high mobility channels materials like Ge. The introduction of Ge as channel material has already shown significant interests in term of device performance enhancement [1,2]. However, the use of Ge in CMOS integration has raised new challenges in terms of clean or wet etch steps since significant Ge loss occurs when it oxidizes in aqueous media.
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Mansour, Raafat R. "RF MEMS-CMOS Device Integration: An Overview of the Potential for RF Researchers." IEEE Microwave Magazine 14, no. 1 (January 2013): 39–56. http://dx.doi.org/10.1109/mmm.2012.2226539.
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FUKAISHI, MUNEO, KAZUYUKI NAKAMURA, and MICHIO YOTSUYANAGI. "HIGH-SPEED AND HIGH-DATA-BANDWIDTH TRANSMITTER AND RECEIVER FOR MULTI-CHANNEL SERIAL DATA COMMUNICATION WITH CMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 1–33. http://dx.doi.org/10.1142/s0129156401000770.
Abstract:
This paper briefly reviews recent research on CMOS gigahertz-rate communication circuits and design innovations for overcoming device performance limitations. A multi-channel transmitter and receiver chip set operating at 5 Gb/s has been developed using 0.25-μm CMOS technology. To achieve high-speed operation, the chip set features: (1) a tree-type demultiplexer and frequency conversion architecture, (2) a self-aligning phase detector for clock and data recovery circuit, and (3) a fully pipelined 8-bit to 10-bit encoder. The features contributing to the achievement of high-data bandwidth for multi-channel transmission include circuits for compensating for the phase difference between multiple receiver chips and for the frequency difference between the system clocks of the transmitter and receiver chips. These techniques for high-speed operation and multi-channel transmission are supported by the high level of integration possible with CMOS technology compared with non-CMOS technology.
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Carta, Fabio, Htay Hlaing, Hassan Edrees, Shyuan Yang, Mingoo Seok, and Ioannis Kymissis. "Co-development of complementary technology and modified-CPL family for organic digital integrated circuits." MRS Proceedings 1795 (2015): 19–25. http://dx.doi.org/10.1557/opl.2015.564.
Abstract:
ABSTRACTWe present a novel logic family alternative to classic CMOS logic and its experimental demonstration for digital application of organic electronics. The proposed logic family is a modified version of the complementary pass-transistor logic (mCPL), which allows use of a stronger transistor (in our case the p-FET) to provide more of the current required to switch the capacitance in the device. We report the integration and characterization of this new class of gates and compare them with the equivalent CMOS structures. The characterization of inverters shows improved tolerance to process variation, up to 2.5× better delay, and 1.7× smaller area for the mCPL devices. Comparison of NOR and NAND gates shows 1.8× and 4.1× reduced gate delay. A 3× reduced energy consumption per operation is also simulated. The improved performance of the mCPL design makes it an alternative architecture for logic application of organic electronics.