Relevant bibliographies by topics / CMOS Device and Integration

Academic literature on the topic 'CMOS Device and Integration'

Author: Grafiati
Published: 7 July 2024

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Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Journal articles on the topic "CMOS Device and Integration":

1

Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.

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A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.
2

Krupar, Joerg, Heiko Hauswald, and Ronny Naumann. "A Substrate Current Less Control Method for CMOS Integration of Power Bridges." Advances in Power Electronics 2010 (September 23, 2010): 1–11. http://dx.doi.org/10.1155/2010/909612.

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Modern electronical devices use high integration to decrease device size and cost and to increase reliability. More and more devices appear that integrate even power devices into VLSI circuits. When driving inductive loads, this is a critical step because freewheeling at a power device appears. In these applications usually special technologies with extra wells for the power devices, SOI technologies, or BiCMOS technologies are required to suppress any substrate current. However, the use of these technologies results in higher production cost for the device. We present a method to control the freewheeling actively. Using this approach we are able to integrate the power devices using a normal CMOS technology.
3

Kogut, Igor T., Victor I. Holota, Anatoly Druzhinin, and V. V. Dovhij. "The Device-Technological Simulation of Local 3D SOI-Structures." Journal of Nano Research 39 (February 2016): 228–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.39.228.

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This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.
4

Leenheer, Andrew, Connor Halsey, Daniel Ward, Deanna Campbell, John S. Mincey, Evan M. Anderson, Scott W. Schmucker, et al. "Atomic-scale Dopant Integration During CMOS Device Fabrication." ECS Meeting Abstracts MA2021-02, no. 30 (October 19, 2021): 918. http://dx.doi.org/10.1149/ma2021-0230918mtgabs.

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Huey, Sidney, Balaji Chandrasekaran, Doyle Bennett, Stan Tsai, Kun Xu, Jun Qian, Siva Dhandapani, Jeff David, Bogdan Swedek, and Lakshmanan Karuppiah. "CMP Process Control for Advanced CMOS Device Integration." ECS Transactions 44, no. 1 (December 15, 2019): 543–52. http://dx.doi.org/10.1149/1.3694367.

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Perez-Bosch Quesada, E., E. Perez, M. Kalishettyhalli Mahadevaiah, and C. Wenger. "Memristive-based in-memory computing: from device to large-scale CMOS integration." Neuromorphic Computing and Engineering 1, no. 2 (November 18, 2021): 024006. http://dx.doi.org/10.1088/2634-4386/ac2cd4.

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Abstract With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO 2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal–insulator–metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.
7

Kitchen, Jennifer, Soroush Moallemi, and Sumit Bhardwaj. "Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000339–82. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_010.

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Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.
8

Tabata, Toshiyuki, Fabien Rozé, Louis Thuries, Sébastien Halty, Pierre-Edouard Raynal, Imen Karmous, and Karim Huet. "Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices." Electronics 11, no. 17 (August 23, 2022): 2636. http://dx.doi.org/10.3390/electronics11172636.

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The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.
9

Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.

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AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.
10

Ostling, Mikael, and Per-Erik Hellstrom. "(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS." ECS Meeting Abstracts MA2023-02, no. 30 (December 22, 2023): 1511. http://dx.doi.org/10.1149/ma2023-02301511mtgabs.

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In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors. In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers. A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistors Fully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices. 3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type. 3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.
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Journal articles Dissertations / Theses Books

Dissertations / Theses on the topic "CMOS Device and Integration":

1

Darwish, Mohamed. "Graphene Devices for Beyond-CMOS Heterogeneous Integration." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1072.

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Semiconductor manufacturing is the workhorse for a wide range of industries. It lies at the heart of consumer electronics, telecommunication equipment and medical devices. Most semiconductor electronics are made from Silicon, and are fabricated using CMOS technology. The versatility of semiconductor electronics stems from the ever-reducing cost of integrating more computing and memory functions on chip. The small cost for adding extra functions has been maintained in the past 50 years through transistor scaling. Transistor scaling focuses on shrinking the size of transistors integrated on chip. This reduction in transistor size, while keeping the overall cost of the chip fixed allowed us to reduce the cost per function with scaling, and is what is celebrated as Moore’s law. Scaling has been working gracefully up to the last decade, where the exponential rise in manufacturing cost and diminishing gains of scaling on device performance reduce its economic benefit. To revive the cost reduction trend, different techniques were proposed such as augmenting CMOS manufacturing with new materials (Beyond-CMOS), 3D integration, and integrating more non-transistor elements on-chip (More than Moore). In this work, we focus on the efficient implementation of several circuit functions using an allotropy of carbon known as graphene. Graphene, a single layer of carbon atoms arranged in a hexagonal lattice, has unique electronic properties that has been taken the solid-state electronics community by a storm since its first experimental conception in 2004. Despite its promising electronic properties, namely the very high charge-carrier mobility and reduced scattering by impurities, graphene circuits has been held back by a plethora of nonidealities and technological roadblocks that hamper its use in traditional transistor-based circuits. In this work, we attempt to leverage the unique physical properties of graphene to implement non von-Neumann neuromorphic computing architectures, low-loss diodes and evaluate the behavior of diffusive-transport graphene couplers. We focus on the the design, fabrication and characterization of graphene devices in the presence of the current performance-limiting technological nonidealities in heterogeneous graphene-CMOS systems. We present the design, fabrication and characterization of all-graphene resistive data converters devices and diodes, discussing their performance and application as building elements of all-graphene brain-inspired computing architectures. We evaluate the performance of graphene couplers operating in the diffusive transport regime, which serve as a method to analyze the cross-coupling between adjacent graphene interconnects. We also discuss the current technological limitations hampering the performance of graphene devices, and the roles of different processing non-idealities on the characteristics of graphene devices.
2

Hållstedt, Julius. "Integration of epitaxial SiGe(C) layers in advanced CMOS devices /." Stockholm : Kungliga Tekniska högskolan, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4498.

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3

Hållstedt, Julius. "Integration of epitaxial SiGe(C) layers in advanced CMOS devices." Doctoral thesis, KTH, Mikroelektronik och tillämpad fysik, MAP, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4498.

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Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices. Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained. Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe. The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer. Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer. Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm. SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices. Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

QC 20100715

4

Pacella, Nan Yang. "Platform for monolithic integration of III-V devices with Si CMOS technology." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/76119.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 169-165).
Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures.
by Nan Yang Pacella.
Ph.D.
5

London, Joanna M. 1974. "Wafer bonding for monolithic integration of Si CMOS VLSI electronics with III-V optoelectronic devices." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/45498.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 1999.
Includes bibliographical references (p. 90-91).
GaAs-on-silicon epitaxy techniques as well as wafer bonding GaAs to Si, have been developed to overcome lattice mismatch in order to integrate optoelectronic and Si devices. However, the thermal expansion differences between these materials continues to be a limitation in using either of these approaches. After recognizing that Si devices, such as MOSFETs, are intrinsically thin and relatively strain tolerant, while optoelectronic devices, such as LEDs and lasers, are thick and very strain sensitive, this research was based on developing a better approach which involved bonding thin Si layers to thick GaAs substrates with various dielectric layers as the interface, to produce silicon-on-gallium arsenide (SonG) wafers. Such wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. With the successful development of SonG techniques for monolithic integration, it will be possible to use full-wafer and batch processing techniques for the production of sophisticated economically viable optoelectronic integrated circuits.
by Joanna M. London.
S.M.
6

Riverola, Borreguero Martín. "Micro and Nano-electro-mechanical devices in the CMOS back end and their applications." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/458694.

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Recentment, l'escalat de la tecnologia complementaria metall-òxid-semiconductor (CMOS) està arribant a límits fonamentals, principalment degut a les fuites de corrent no nul·les que el transistor presenta. És per això que s’està investigant una nova branca que va més enllà dels límits de la llei de Moore la qual s’anomena “Més que Moore” i està atraient l’interès per nous dispositius de processat de la informació i memòries, noves tecnologies per integració heterogènia de múltiples funcions, i nous paradigmes d'arquitectures de sistemes. Una d'aquestes tecnologies prometedores per processat de la informació és la tecnologia de relés micro- i nano electromecànica, perquè presenta fuites de corrent pràcticament nul·les i una commutació entre dos estats molt abrupta. Aquesta tesi proposa explorar les possibilitats d'aprofitar les capes disponibles de la tecnologia CMOS comercial AMS 0.35 µm per implementar relés micro i nano electromecànics. En concret, s’exploren dos conceptes diferents: un són relés actuats en el pla i definits usant solament la capa d’interconnexió anomenada via, i l’altre són relés actuats torsionalment i formats amb metalls i vies (sovint anomenat com compost) a la vegada que suportat per vies. Ambdós conceptes es basen en la capa de tungstè VIA3, la qual inclou característiques claus tals com gran duresa, alt punt de fusió, poc estrès, i gran resistència a l’àcid fluorhídric (HF), ja que les estructures mecàniques s'alliberen mitjançant un procés post-CMOS sense màscares basat en una solució d'HF. Gràcies a les característiques excepcionals de la plataforma de VIA3, també s’han fabricat ressonadors MEMS basats en l'esmenada plataforma, el que ha permès contribuir al disseny i la caracterització d'un oscil·lador de doble freqüència que consisteix en ressonadors torsionals de tungstè i en un amplificador de transimpedància ultra-compacte, de baix consum i amb un alt guany. Finalment i paral·lel al principal fil de la tesi, també s’han desenvolupat capacitats commutables en col·laboració amb l’empresa SilTerra Malaysia Sdn. Bhd. Aquests dispositius es caracteritzen per estar totalment integrats en el procés d'una tecnologia comercial CMOS de 180 nm de baix cost (usant la plataforma SilTerra MEMS-on-CMOS).
Recently, several new emerging devices are starting to be explored because the traditional down-scaling approach of the complementary metal-oxide-semiconductor (CMOS) technology (often called “More Moore”) is reaching fundamental limits; mainly due to non-zero transistor off-state leakage. This brand-new domain that goes beyond the boundaries of Moore’s law is commonly named ``More than Moore'' and is driving interest in new devices for information processing and memory, new technologies for heterogeneous integration of multiple functions, and new paradigms for system architecture. One of these new promising technologies for logic and information processing is the micro- and nanoelectromechanical (M/NEM) relay technology, because of its immeasurably low off-state leakage current and super-steep switching behavior. This dissertation proposes to explore the possibilities of leveraging the available layers of the commercial CMOS technology AMS 0.35 µm to implement M/NEM relays. Specifically, two different approaches are explored: in-plane actuated relays defined using solely the via layer, and torsional actuated relays formed with metal and via layers (usually named composite) while supported by vias. Both approaches are supported by the tungsten VIA3 layer, which includes key features such as high hardness, high melting point, low stress and resistance to hydrofluoric (HF) acid, since the mechanical structures are released in a maskless post-CMOS process based on a wet HF enchant. Based on the key structural features that the developed relays showed, MEMS resonators based on the VIA3 platform were also fabricated. In this dissertation, we also present a particular contribution involving the design and characterization of a dual-frequency oscillator that consist of such reliable torsional tungsten resonators and a high gain, low power and ultra-compact transimpedance amplifier (TIA). Finally and parallel to the main thread of this dissertation, RF MEMS switched capacitors are developed as a result of the collaboration with the semiconductor manufacturing enterprise SilTerra Malaysia Sdn. Bhd. These devices have the particularity of being fully integrated into the process flow of a low cost, commercial 180 nm CMOS technology (using the SilTerra MEMS-on-CMOS process platform).
7

Pearson, Brian (Brian Sung-Il). "Large grain Ge growth on amorphous substrates for CMOS back-end-of-line integration of active optoelectronic devices." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78240.

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Abstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 97-104).
The electronic-photonic integrated circuit (EPIC) has emerged as a leading technology to surpass the interconnect bottlenecks that threaten to limit the progress of Moore's Law in microprocessors. Compared to conventional metal interconnects, photonic interconnects have the potential to increase bandwidth density while simultaneously reducing power consumption. However, photonic devices are orders of magnitude larger than electronic devices and therefore consume valuable substrate real estate. The ideal solution, in order to take advantage of optical interconnects without decreasing transistor counts, is to monolithically implement dense threedimensional integration of electronics and photonics. This involves moving the photonic devices off the substrate, and into the metal interconnect stack. Moving photonic devices into the interconnect stack imposes two fabrication limitations. First, the available thermal budget allowed for photonic device processing is limited to 450 °C. Second, the metal interconnects are embedded within amorphous dielectrics and therefore there is no crystalline seed to initiate epitaxial growth. This thesis addresses two major barriers for integration of photonics in the back end: (1) how to fabricate high quality Ge for active regions of optoelectronic devices while adhering to back-end processing constraints, and (2) how to couple optical power to these devices. First, an approach was developed to fabricate the active region of Ge-based optoelectronic devices. A new technique, known as two-dimensional geometrically confined lateral growth (2D GCLG), has demonstrated single crystalline Ge on an amorphous substrate. This thesis presents the first application of the 2D GCLG technique to fill a lithographically defined Si0 2 trench with large grain Ge, while adhering to back-end processing constraints. A modified design is then proposed to increases the yield of 2D GCLG structures. This trench filling technique is an integral step towards fabricating Ge-based optoelectronic devices that are capable of being integrated into the back-end of a microprocessor. Once it was established that high quality Ge trenches could be fabricated in the back-end, optical coupling to devices was addressed. For dense three-dimensional integration of photonic devices, vertical coupling between photonic planes is necessary. Therefore, this thesis begins with the design and simulation of vertical couplers. These couplers utilize evanescent coupling between two overlapping inversely tapered waveguides, which ensure efficient coupling due to optical impedance matching. These couplers are designed to exhibit coupling efficiencies in excess of 98.4%, equivalent to a 0.07 dB coupling loss. The technique of evanescent coupling between overlapping inverse tapers is then applied to electro-absorption modulators (EAMs). A design for low-loss evanescent coupling from a waveguide to a Ge EAM is modeled and optimized. The design implements lateral evanescent coupling from overlapping inverse taper structures. Simulation results show that the coupling efficiency into and out of the modulator can be as high as 99%, equivalent to a 0.04 dB coupling loss.
by Brian Pearson.
S.M.
8

Smith, Anderson. "Graphene-based Devices for More than Moore Applications." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188134.

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Moore's law has defined the semiconductor industry for the past 50 years. Devices continue to become smaller and increasingly integrated into the world around us. Beginning with personal computers, devices have become integrated into watches, phones, cars, clothing and tablets among other things. These devices have expanded in their functionality as well as their ability to communicate with each other through the internet. Further, devices have increasingly been required to have diverse of functionality. This combination of smaller devices coupled with diversification of device functionality has become known as more than Moore. In this thesis, more than Moore applications of graphene are explored in-depth. Graphene was discovered experimentally in 2004 and since then has fueled tremendous research into its various potential applications. Graphene is a desirable candidate for many applications because of its impressive electronic and mechanical properties. It is stronger than steel, the thinnest known material, and has high electrical conductivity and mobility. In this thesis, the potentials of graphene are examined for pressure sensors, humidity sensors and transistors. Through the course of this work, high sensitivity graphene pressure sensors are developed. These sensors are orders of magnitude more sensitive than competing technologies such as silicon nanowires and carbon nanotubes. Further, these devices are small and can be scaled aggressively. Research into these pressure sensors is then expanded to an exploration of graphene's gas sensing properties -- culminating in a comprehensive investigation of graphene-based humidity sensors. These sensors have rapid response and recovery times over a wide humidity range. Further, these devices can be integrated into CMOS processes back end of the line. In addition to CMOS Integration of these devices, a wafer scale fabrication process flow is established. Both humidity sensors and graphene-based transistors are successfully fabricated on wafer scale in a CMOS compatible process. This is an important step toward both industrialization of graphene as well as heterogeneous integration of graphene devices with diverse functionality. Furthermore, fabrication of graphene transistors on wafer scale provides a framework for the development of statistical analysis software tailored to graphene devices. In summary, graphene-based pressure sensors, humidity sensors, and transistors are developed for potential more than Moore applications. Further, a wafer scale fabrication process flow is established which can incorporate graphene devices into CMOS compatible process flows back end of the line.

QC 20160610

9

Bari, Mohammad Rezaul. "Fabrication, Characterization, and Modelling of Self-Assembled Silicon Nanostructure Vacuum Field Emission Devices." Thesis, University of Canterbury. Electrical and Computer Engineering, 2011. http://hdl.handle.net/10092/6601.

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The foundation of vacuum nanoelectronics was laid as early as in 1961 when Kenneth Shoulders proposed the development of vertical field-emission micro-triodes. After years of conspicuous stagnancy in the field much interest has reemerged for the vacuum nanoelectronics in recent years. Electron field emission under high electric field from conventional and exotic nanoemitters, which have now been made possible with the use of modern day technology, has been the driving force behind this renewal of interest in vacuum nanoelectronics. In the research reported in this thesis self-assembled silicon nanostructures were studied as a potential source of field emission for vacuum nanoelectronic device applications. Whiskerlike protruding silicon nanostructures were grown on untreated n- and p-type silicon surfaces using electron-beam annealing under high vacuum. The electrical transport characteristics of the silicon nanostructures were investigated using conductive atomic force microscopy (C-AFM). Higher electrical conductivities for the nanostructured surface compared to that for the surrounding planar silicon substrate region were observed. Non-ideal diode behaviour with high ideality factors were reported for the individual nanostructure-AFM tip Schottky nanocontacts. This demonstration, indicative of the presence of a significant field emission component in the analysed current transport phenomena was also detailed. Field emission from these nanostructures was demonstrated qualitatively in a lift-mode interleave C-AFM study. A technique to fabricate integrated field emission diodes using silicon nanostructures in a CMOS process technology was developed. The process incorporated the nanostructure growth phase at the closing steps in the process flow. Turn-on voltages as low as ~ 0.6 V were reported for these devices, which make them good candidates for incorporation into standard CMOS circuit applications. Reproducible I V characteristics exhibited by these fabricated devices were further studied and field emission parameters were extracted. A new consistent and reliable method to extract field emission parameters such as effective barrier height, field conversion factor, and total emitting area at the onset of the field emission regime was developed and is reported herein. The developed parameter extraction method used a unified electron emission approach in the transition region of the device operation. The existence of an electron-supply limited current saturation region at very high electric field was also confirmed. Both the C-AFM and the device characterization studies were modelled and simulated using the finite element method in COMSOL Multiphysics. The experimental results – the field developed at various operating environments – are explained in relation to these finite element analyses. Field enhancements at the atomically sharp nanostructure apexes as suggested in the experimental studies were confirmed. The nanostructure tip radius effect and sensitivity to small nanostructure height variation were investigated and mathematical relations for the nanostructure regime of our interest were established. A technique to optimize the cathode-opening area was also demonstrated. Suggestions related to further research on field emission from silicon nanostructures, optimization of the field emission device fabrication process, and fabrication of field emission triodes are elaborated in the final chapter of this thesis. The experimental, modelling, and simulation works of this thesis indicate that silicon field emission devices could be integrated into the existing CMOS process technology. This integration would offer goods from both the worlds of vacuum and solid-sate nanoelectronics – fast ballistic electron transport, temperature insensitivity, radiation hardness, high packing density, mature technological backing, and economies of scale among other features.
10

Dubreuil, Théophile. "Architecture 3D 1T1R innovante à base de RRAMs pour le calcul hyperdimensionnel." Electronic Thesis or Diss., Université Grenoble Alpes, 2023. http://www.theses.fr/2023GRALT085.

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Dans les prochaines années, en raison des besoins toujours plus grands des applications d'apprentissage machine dans le domaine de l'intelligence artificielle, une augmentation soutenue de la capacité de calcul est nécessaire pour faire face à un véritable "déluge de données". Pour relever ce défi, les architectures de calcul immergé en mémoire (IMC) à haute performance nécessitent le développement de nouvelles technologies adaptées à la fois au calcul local et au stockage. Dans ce contexte, ce travail de thèse présente de nouvelles matrices mémoire 3D 1T1R qui sont dérivées des transistors à nanofeuillés empilés. Cette nouvelle technologie est associée au calcul hyperdimensionnel (HDC), un paradigme inspiré du cerveau qui est à la fois résistant à l’erreur et facilement parallélisable. Tout d’abord, nous montrons que l’IMC peut largement bénéficier des architectures 3D basées sur les mémoires non volatiles (NVM) pour augmenter la densité et les performances de calcul. Toutefois, les difficultés de fabrication et les résistances et capacités parasites inhérentes aux structures 3D limitent parfois considérablement les performances de ces architectures pour l’IMC. Grâce à la technologie 3D 1T1R proposée dans ce travail, qui combine des nanofeuillés empilés comportant des grilles indépendantes avec une RRAM insérée dans le drain des transistors, nous montrons qu’il est possible de s’affranchir, en partie, de ces problèmes. Nous présentons, fabriquons et caractérisons électriquement plusieurs modules technologiques essentiels à la fabrication de structures 1T1R 3D. Nous démontrons également la fonctionnalité de cellules mémoires 1T1R pour lesquelles le point RRAM est intégré dans le drain de différents types de sélecteurs avec une électrode inférieure faite de Si dopé. Enfin, nous proposons d’implémenter l’algorithme HDC en mémoire pour tirer profit de notre structure 3D 1T1R. Différentes implémentations sont explorées et leurs performances sont évaluées à l’aide de simulations SPICE. Nous montrons également à l'aide de simulations logicielles que la classification de langages et la reconnaissance de gestes, basées sur le calcul hyperdimensionnel, peuvent être implémentées à l’aide de notre structure 3D 1T1R de façon réaliste
In the years to come, due to the insatiable need for data-intensive machine learning applications, a drastic expansion of computing power is required to confront a veritable “data deluge”. To meet this challenge, high-performance In-Memory-Computing (IMC) architectures require the development of novel storage devices that are also suited for local computations. In this context, this thesis work presents a novel 3D 1T1R memory array derived from vertically stacked-nanosheet technology, which is used for Hyperdimensional Computing (HDC), an error-resilient and highly parallel brain-inspired computing paradigm. Firstly, the IMC paradigm can greatly benefit from novel 3D non-volatile memory (NVM) architectures which increase the density and the computing performances. However, the fabrication challenges and parasitics can greatly limit the potential benefits of these architectures. With the 3D 1T1R technology, made by coupling new disruptive gate-independent stacked-nanosheets with drain-based RRAM cells, we show that some of these issues can be overcome, thus leading to high-density 3D NVM arrays. We demonstrate various technological modules necessary for the fabrication of 3D 1T1R structures. Devices are fabricated and electrically characterized for both storage and computing applications. In particular, functional MEOL drain-based RRAM cells are demonstrated with a doped-Si bottom electrode for various types of selector technologies. Finally, we propose a full-IMC architecture of HDC to take advantage of the 3D 1T1R structure. Different hardware implementations are proposed and compared with SPICE simulations. We also show with software-based simulations that language and gesture recognition can be realistically performed with our 3D 1T1R implementation
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Books on the topic "CMOS Device and Integration":

1

Chen, John Y. CMOS devices and technology for VLSI. Englewood Cliffs, N.J: Prentice Hall, 1990.

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Madrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Reading, Mass: Addison-Wesley, 1992.

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Laconte, J. Micromachined thin-film sensors for SOI-CMOS co-integration. New York: Springer, 2011.

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Taur, Yuan. Fundamentals of modern VLSI devices. 2nd ed. Cambridge: Cambridge University Press, 2009.

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Taur, Yuan. Fundamentals of modern VLSI devices. Cambrige, UK: Cambridge University Press, 1998.

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Incorporated, Advanced Micro Devices. PAL device data book: Bipolar and CMOS. [Sunnyvale, CA]: Advanced Micro Devices Inc., 1990.

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7

Simon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.

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Simon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.

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9

V, Heinbuch Dennis, ed. CMOS 3 cell library. Reading, Mass: Addison-Wesley Pub. Co., 1988.

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10

Ytterdal, Trond, Yuhua Cheng, and Tor A. Fjeldly. Device Modeling for Analog and RF CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2003. http://dx.doi.org/10.1002/0470863803.

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Book chapters on the topic "CMOS Device and Integration":

1

Mahadevaiah, Mamathamba Kalishettyhalli, Marco Lisker, Mirko Fraschke, Steffen Marschmeyer, Eduardo Perez, Emilio Perez-Bosch Quesada, Christian Wenger, and Andreas Mai. "Integration of Memristive Devices into a 130 nm CMOS Baseline Technology." In Springer Series on Bio- and Neurosystems, 177–90. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-36705-2_7.

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AbstractThe two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results.
2

Dubois, E., G. Larrieu, R. Valentin, N. Breil, and F. Danneville. "Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration." In Nanoscale CMOS, 157–204. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch5.

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Xia, Qiangfei. "Memristor Device Engineering and CMOS Integration for Reconfigurable Logic Applications." In Memristors and Memristive Systems, 327–51. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-9068-5_11.

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Wang, Guilei. "SiGe S/D Integration and Device Verification." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 49–92. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_4.

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5

Götzlich, J., R. Kircher, K. Giesen, and G. Pöschl. "Characterization and Simulation of SOI-CMOS Devices for 3D-integration." In ESSDERC ’89, 873–76. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_180.

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Nourbakhsh, Amirhasan, Lili Yu, Yuxuan Lin, Marek Hempel, Ren-Jye Shiue, Dirk Englund, and Tomás Palacios. "Heterogeneous Integration of 2D Materials and Devices on a Si Platform." In Beyond-CMOS Technologies for Next Generation Computer Design, 43–84. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-90385-9_3.

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Liu, Ming, Hua Yu, and Wei Wang. "FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 44–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-02427-6_9.

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Xie, Huikai, and Ying Zhou. "CMOS-CNT Integration." In Encyclopedia of Nanotechnology, 549–57. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-9780-1_196.

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9

Peroulis, Dimitrios, Prashant R. Waghmare, Sushanta K. Mitra, Supone Manakasettharn, J. Ashley Taylor, Tom N. Krupenkin, Wenguang Zhu, et al. "CMOS-CNT Integration." In Encyclopedia of Nanotechnology, 449–56. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-90-481-9751-4_196.

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Thejas and Navakanta Bhat. "CMOS MEMS Integration." In Materials and Failures in MEMS and NEMS, 361–80. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2015. http://dx.doi.org/10.1002/9781119083887.ch12.

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Conference papers on the topic "CMOS Device and Integration":

1

Xu, Kaikai, Beiju Huang, Kingsley A. Ogudo, Lukas W. Snyman, Hongda Chen, and G. P. Li. "Silicon Light-emitting Device in Standard CMOS technology." In Optoelectronic Devices and Integration. Washington, D.C.: OSA, 2015. http://dx.doi.org/10.1364/oedi.2015.ot1c.3.

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Hussain, Muhammad M., Sohail F. Shaikh, Galo A. Torres Sevilla, Joanna M. Nassar, Aftab M. Hussain, Rabab R. Bahabry, Sherjeel M. Khan, et al. "Manufacturable Heterogeneous Integration for Flexible CMOS Electronics." In 2018 76th Device Research Conference (DRC). IEEE, 2018. http://dx.doi.org/10.1109/drc.2018.8442163.

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Ohno, Hideo. "Three-terminal spintronics devices for CMOS integration." In 2017 75th Device Research Conference (DRC). IEEE, 2017. http://dx.doi.org/10.1109/drc.2017.7999490.

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4

Salimy, S., S. Toutain, D. Averty, F. Challali, A. Goullet, M.-P. Besland, A. Rhallabi, J.-P. Landesman, J.-C. Saubat, and A. Charpentier. "Passive components integration in CMOS technology." In ESSDERC 2010 - 40th European Solid State Device Research Conference. IEEE, 2010. http://dx.doi.org/10.1109/essderc.2010.5618467.

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5

Fulbert, Laurent, and Jean-Marc Fedeli. "Photonics — Electronics integration on CMOS." In ESSDERC 2011 - 41st European Solid State Device Research Conference. IEEE, 2011. http://dx.doi.org/10.1109/essderc.2011.6044241.

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6

Pi, Shuang, Peng Lin, Hao Jiang, Can Li, and Qiangfei Xia. "Device engineering and CMOS integration of nanoscale memristors." In 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2014. http://dx.doi.org/10.1109/iscas.2014.6865156.

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7

Holz, J., I. Koren, and U. Ramacher. "Technology and System Integration of CMOS Image Sensors." In 30th European Solid-State Device Research Conference. IEEE, 2000. http://dx.doi.org/10.1109/essderc.2000.194724.

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8

Waldo, Whitson G., Ibrahim Turkman, and Rickey Brownson. "Device and process integration for a 0.55-um channel length CMOS device." In Microelectronic Manufacturing 1996, edited by Ih-Chin Chen, Nobuo Sasaki, Divyesh N. Patel, and Girish A. Dixit. SPIE, 1996. http://dx.doi.org/10.1117/12.250858.

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9

Beals, Mark, J. Michel, J. F. Liu, D. H. Ahn, D. Sparacin, R. Sun, C. Y. Hong, et al. "Process flow innovations for photonic device integration in CMOS." In Integrated Optoelectronic Devices 2008, edited by Joel A. Kubby and Graham T. Reed. SPIE, 2008. http://dx.doi.org/10.1117/12.774576.

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10

Matsushita, K., N. Takayama, Ning Li, S. Ito, K. Okada, and A. Matsuzawa. "CMOS device modeling for millimeter-wave power amplifiers." In 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2009). IEEE, 2009. http://dx.doi.org/10.1109/rfit.2009.5383690.

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Reports on the topic "CMOS Device and Integration":

1

Smith, J. H., S. Montague, J. J. Sniegowski, and J. R. Murray. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS. Office of Scientific and Technical Information (OSTI), October 1996. http://dx.doi.org/10.2172/380312.

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Smith, J. H., S. Montague, J. J. Sniegowski, and P. J. McWhorter. Embedded micromechanical devices for the monolithic integration of MEMS and CMOS. Office of Scientific and Technical Information (OSTI), July 1995. http://dx.doi.org/10.2172/114489.

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3

Fonstad, Clifton G. Monolithic Integration of Optoelectronic Devices and Si-CMOS on Gallium Arsenide. Fort Belvoir, VA: Defense Technical Information Center, November 2000. http://dx.doi.org/10.21236/ada391141.

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4

MYERS, DAVID R., JEFFREY R. JESSING, OLGA B. SPAHN, and MARTY R. SHANEYFELT. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99). Office of Scientific and Technical Information (OSTI), January 2000. http://dx.doi.org/10.2172/750886.

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5

James F. Christian, PhD, and PhD Christopher Stapels. Next-Generation Active Pixel Sensor Device With CMOS APDs. Office of Scientific and Technical Information (OSTI), March 2007. http://dx.doi.org/10.2172/900308.

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6

Xie, Y. H. A Quantum Dot Optical Modulator for Integration With Si CMOS. Fort Belvoir, VA: Defense Technical Information Center, August 2005. http://dx.doi.org/10.21236/ada459498.

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7

Xu, Xiaodong, Mark Mirotznik, Michael Hochberg, and David Castner. Optoelectronic Device Integration in Silicon (OpSIS). Fort Belvoir, VA: Defense Technical Information Center, October 2015. http://dx.doi.org/10.21236/ad1003428.

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8

Cerjan, C. J., and T. W. Sigmon. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs. Office of Scientific and Technical Information (OSTI), February 2000. http://dx.doi.org/10.2172/792430.

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9

Brotman, Susan. The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6585.

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10

Martinez, Carlos J., Amit Goyal, Alberto Saiani, David Gracias, and Rajesh R. Naik. Integrated Miniaturized Materials - From Self-Assembly to Device Integration. Volume 1272. Fort Belvoir, VA: Defense Technical Information Center, January 2011. http://dx.doi.org/10.21236/ada537907.

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