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Journal articles on the topic 'CMOS compatible fabrication'

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Author: Grafiati

Published: 6 September 2023

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1

Buyong, Muhamad Ramdzan, Norazreen Abd Aziz, and Burhanuddin Yeop Majlis. "Characterization and Optimization of Seals-Off for Very Low Pressure Sensors (VLPS) Fabricated by CMOS MEMS Process." Advanced Materials Research 74 (June 2009): 231–34. http://dx.doi.org/10.4028/www.scientific.net/amr.74.231.

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In the world of MEMS processing today, fabrications of membrane are performed using bulk micromachining (BMM). However these techniques not easiest to integrate with CMOS standard process due to not compatible of the processing flow. An attractive alternative deployment of surface micromachining (SMM). There is a trend to use surface micromachining to their advantage of simplicity in design and fabrication process compatibility. This paper presents process development of thin layer membrane for very low capacitive pressure sensor application. The structure of the membrane consists of parallel plate which both top and bottom electrodes were fixed at both sides. Utilizing CMOS MEMS process compatible fabrication of the thin layer membrane involved in three stages; i) hole opening etch, ii) sacrificial intermediate oxide release etch and iii) closing of etch holes. Therefore seals-off process characterization and optimization experiment are presented in this paper, will spur advancement in the development of a CMOS MEMS product for very low capacitive pressure sensor.

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2

Bi, Cheng, and Yanfei Liu. "CMOS-Compatible Optoelectronic Imagers." Coatings 12, no. 11 (October 22, 2022): 1609. http://dx.doi.org/10.3390/coatings12111609.

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Silicon-based complementary metal oxide semiconductors have revolutionized the field of imaging, especially infrared imaging. Infrared focal plane array imagers are widely applied to night vision, haze imaging, food selection, semiconductor detection, and atmospheric pollutant detection. Over the past several decades, the CMOS integrated circuits modified by traditional bulk semiconductor materials as sensitivity sensors for optoelectronic imagers have been used for infrared imaging. However, traditional bulk semiconductor material-based infrared imagers are synthesized by complicated molecular beam epitaxy, and they are generally coupled with expensive flip-chip-integrated circuits. Hence, high costs and complicated fabrication processes limit the development and popularization of infrared imagers. Emerging materials, such as inorganic–organic metal halide perovskites, organic polymers, and colloidal quantum dots, have become the current focus point for preparing CMOS-compatible optoelectronic imagers, as they can effectively decrease costs. However, these emerging materials also have some problems in coupling with readout integrated circuits and uniformity, which can influence the quality of imagers. The method regarding coupling processes may become a key point for future research directions. In the current review, recent research progress on emerging materials for infrared imagers is summarized.

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3

Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (August 24, 2020): 800. http://dx.doi.org/10.3390/mi11090800.

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The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

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4

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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5

Rasmussen, A., M. Gaitan, L. E. Locascio, and M. E. Zaghloul. "Fabrication techniques to realize CMOS-compatible microfluidic microchannels." Journal of Microelectromechanical Systems 10, no. 2 (June 2001): 286–97. http://dx.doi.org/10.1109/84.925785.

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6

Lv, Hongming, Huaqiang Wu, Jinbiao Liu, Can Huang, Junfeng Li, Jiahan Yu, Jiebin Niu, Qiuxia Xu, Zhiping Yu, and He Qian. "Inverted process for graphene integrated circuits fabrication." Nanoscale 6, no. 11 (2014): 5826–30. http://dx.doi.org/10.1039/c3nr06904d.

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7

Wu, Wenhao, Yu Yu, Wei Liu, and Xinliang Zhang. "Fully integrated CMOS-compatible polarization analyzer." Nanophotonics 8, no. 3 (January 31, 2019): 467–74. http://dx.doi.org/10.1515/nanoph-2018-0205.

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AbstractPolarization measurement has been widely used in material characterization, medical diagnosis and remote sensing. However, existing commercial polarization analyzers are either bulky schemes or operate in non-real time. Recently, various polarization analyzers have been reported using metal metasurface structures, which require elaborate fabrication and additional detection devices. In this paper, a compact and fully integrated silicon polarization analyzer with a photonic crystal-like metastructure for polarization manipulation and four subsequent on-chip photodetectors for light-current conversion is proposed and demonstrated. The input polarization state can be retrieved instantly by calculating four output photocurrents. The proposed polarization analyzer is complementary metal oxide semiconductor-compatible, making it possible for mass production and easy integration with other silicon-based devices monolithically. Experimental verification is also performed for comparison with a commercial polarization analyzer, and deviations of the measured polarization angle are <±1.2%.

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8

AGARWAL, AJAY, N. BALASUBRAMANIAN, N. RANGANATHAN, and R. KUMAR. "SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER." International Journal of Nanoscience 05, no. 04n05 (August 2006): 445–51. http://dx.doi.org/10.1142/s0219581x06004619.

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We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper.

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9

Xiong, Chunle, Bryn Bell, and Benjamin J. Eggleton. "CMOS-compatible photonic devices for single-photon generation." Nanophotonics 5, no. 3 (September 1, 2016): 427–39. http://dx.doi.org/10.1515/nanoph-2016-0022.

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AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

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10

Kang, G. B., J. M. Park, S. G. Kim, J. G. Koo, J. H. Park, Y. S. Sohn, and Y. T. Kim. "Fabrication and characterisation of CMOS compatible silicon nanowire biosensor." Electronics Letters 44, no. 16 (2008): 953. http://dx.doi.org/10.1049/el:20081876.

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11

Cuiling Gong and Tim Hogan. "CMOS Compatible Fabrication Processes for the Digital Micromirror Device." IEEE Journal of the Electron Devices Society 2, no. 3 (May 2014): 27–32. http://dx.doi.org/10.1109/jeds.2014.2309129.

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12

Potts, A., G. J. Parker, J. J. Baumberg, and P. A. J. de Groot. "CMOS compatible fabrication methods for submicron Josephson junction qubits." IEE Proceedings - Science, Measurement and Technology 148, no. 5 (September 1, 2001): 225–28. http://dx.doi.org/10.1049/ip-smt:20010395.

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13

Ray, Vishva, Ramkumar Subramanian, Pradeep Bhadrachalam, Liang-Chieh Ma, Choong-Un Kim, and Seong Jin Koh. "CMOS-compatible fabrication of room-temperature single-electron devices." Nature Nanotechnology 3, no. 10 (September 14, 2008): 603–8. http://dx.doi.org/10.1038/nnano.2008.267.

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14

Bolten, Jens, Jens Hofrichter, Nikolaj Moll, Sophie Schönenberger, Folkert Horst, Bert J. Offrein, Thorsten Wahlbrink, Thomas Mollenhauer, and Heinrich Kurz. "CMOS compatible cost-efficient fabrication of SOI grating couplers." Microelectronic Engineering 86, no. 4-6 (April 2009): 1114–16. http://dx.doi.org/10.1016/j.mee.2008.11.038.

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15

Zhou, Huajie, Yi Song, Qiuxia Xu, Yongliang Li, and Huaxiang Yin. "Fabrication of Bulk-Si FinFET using CMOS compatible process." Microelectronic Engineering 94 (June 2012): 26–28. http://dx.doi.org/10.1016/j.mee.2012.01.004.

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16

Koczorowski, W., P. Kuświk, M. Przychodnia, K. Wiesner, S. El-Ahmar, M. Szybowicz, M. Nowicki, W. Strupiński, and R. Czajka. "CMOS- compatible fabrication method of graphene-based micro devices." Materials Science in Semiconductor Processing 67 (August 2017): 92–97. http://dx.doi.org/10.1016/j.mssp.2017.05.021.

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17

Xie, Sheng, Xuetao Luo, Luhong Mao, and Haiou Li. "Design, Fabrication, and Modeling of CMOS-Compatible Double Photodiode." Transactions of Tianjin University 23, no. 2 (March 2017): 163–67. http://dx.doi.org/10.1007/s12209-017-0038-1.

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18

Zhang Chi, 张弛, and 肖淑敏 Xiao Shumin. "介质超构表面的CMOS兼容制备工艺的进展." Acta Optica Sinica 43, no. 8 (2023): 0822003. http://dx.doi.org/10.3788/aos230489.

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19

Mujeeb-U-Rahman, Muhammad, Dvin Adalian, and Axel Scherer. "Fabrication of Patterned Integrated Electrochemical Sensors." Journal of Nanotechnology 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/467190.

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Fabrication of integrated electrochemical sensors is an important step towards realizing fully integrated and truly wireless platforms for many local, real-time sensing applications. Micro/nanoscale patterning of small area electrochemical sensor surfaces enhances the sensor performance to overcome the limitations resulting from their small surface area and thus is the key to the successful miniaturization of integrated platforms. We have demonstrated the microfabrication of electrochemical sensors utilizing top-down lithography and etching techniques on silicon and CMOS substrates. This choice of fabrication avoids the need of bottom-up techniques that are not compatible with established methods for fabricating electronics (e.g., CMOS) which form the industrial basis of most integrated microsystems. We present the results of applying microfabricated sensors to various measurement problems, with special attention to their use for continuous DNA and glucose sensing. Our results demonstrate the advantages of using micro- and nanofabrication techniques for the miniaturization and optimization of modern sensing platforms that employ well-established electronic measurement techniques.

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20

Vaha-Heikkila, T., and M. Ylonen. "$G$-Band Distributed Microelectromechanical Components Based on CMOS Compatible Fabrication." IEEE Transactions on Microwave Theory and Techniques 56, no. 3 (March 2008): 720–28. http://dx.doi.org/10.1109/tmtt.2008.916885.

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21

Li, Ying, Jun Yu, Hao Wu, and Zhenan Tang. "Design and fabrication of a CMOS-compatible MHP gas sensor." AIP Advances 4, no. 3 (March 2014): 031339. http://dx.doi.org/10.1063/1.4869616.

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22

Khondaker, Saiful I. "Parallel Fabrication of CMOS Compatible Single Walled Carbon Nanotube Devices." Reviews in Nanoscience and Nanotechnology 1, no. 3 (May 1, 2012): 187–99. http://dx.doi.org/10.1166/rnn.2012.1013.

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23

Yin, Mei, Wei Yang, Yanping Li, Xingjun Wang, and Hongbin Li. "CMOS-compatible and fabrication-tolerant MMI-based polarization beam splitter." Optics Communications 335 (January 2015): 48–52. http://dx.doi.org/10.1016/j.optcom.2014.08.060.

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24

Zhu, Huixian, Tai-Chin Lo, Ralf Lenigk, and Reinhard Renneberg. "Fabrication of a novel oxygen sensor with CMOS compatible processes." Sensors and Actuators B: Chemical 46, no. 2 (February 1998): 155–59. http://dx.doi.org/10.1016/s0925-4005(98)00044-6.

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25

Pakula, L. S., H. Yang, H. T. M. Pham, P. J. French, and P. M. Sarro. "Fabrication of a CMOS compatible pressure sensor for harsh environments." Journal of Micromechanics and Microengineering 14, no. 11 (August 11, 2004): 1478–83. http://dx.doi.org/10.1088/0960-1317/14/11/007.

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26

Ng, E. J., T. Myint, N. Shen, J. B. W. Soon, V. Pott, V. X. H. Leong, N. Singh, and J. M. Tsai. "High density vertical silicon NEM switches with CMOS-compatible fabrication." Electronics Letters 47, no. 13 (June 23, 2011): 759–60. http://dx.doi.org/10.1049/el.2011.1073.

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27

Koryazhkina, Maria N., Dmitry O. Filatov, Stanislav V. Tikhov, Alexey I. Belov, Dmitry A. Serov, Ruslan N. Kryukov, Sergey Yu Zubkov, et al. "Electrical Characteristics of CMOS-Compatible SiOx-Based Resistive-Switching Devices." Nanomaterials 13, no. 14 (July 16, 2023): 2082. http://dx.doi.org/10.3390/nano13142082.

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The electrical characteristics and resistive switching properties of memristive devices have been studied in a wide temperature range. The insulator and electrode materials of these devices (silicon oxide and titanium nitride, respectively) are fully compatible with conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. Silicon oxide is also obtained through the low-temperature chemical vapor deposition method. It is revealed that the as-fabricated devices do not require electroforming but their resistance state cannot be stored before thermal treatment. After the thermal treatment, the devices exhibit bipolar-type resistive switching with synaptic behavior. The conduction mechanisms in the device stack are associated with the effect of traps in the insulator, which form filaments in the places where the electric field is concentrated. The filaments shortcut the capacitance of the stack to different degrees in the high-resistance state (HRS) and in the low-resistance state (LRS). As a result, the electron transport possesses an activation nature with relatively low values of activation energy in an HRS. On the contrary, Ohm’s law and tunneling are observed in an LRS. CMOS-compatible materials and low-temperature fabrication techniques enable the easy integration of the studied resistive-switching devices with traditional analog–digital circuits to implement new-generation hardware neuromorphic systems.

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28

Erfanian, Alireza, Hamed Mehrara, Mahdi Khaje, and Ahmad Afifi. "A room temperature 2 × 128 PtSi/Si-nanostructure photodetector array compatible with CMOS process." Sensor Review 35, no. 3 (June 15, 2015): 282–86. http://dx.doi.org/10.1108/sr-11-2014-0736.

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Purpose – The purpose of this paper is to demonstrate a successful fabrication of 2 × 128 linear array of typical infrared (IR) detectors made of p-type tSi/porous Si Schottky barrier. Design/methodology/approach – Using metal-assisted chemical etching (MaCE) as a unique approach, a sample definition of a porous Si nanostructure region for fabricating of any high-density photodetectors array has been formulated. Besides, the uniformity of pixels at different position along the array has been confirmed by optical images and measurements of photocurrent in IR regime at room temperature. Findings – The experimental result illustrates the existence of an open-circuit voltage up to 30 mV at 1.5-μm wavelength for an area of 50 × 50 μm2. Additionally, this behavior is almost the same at different pixels of fabricated array. Research limitations/implications – The uniformity of pixels and definition of nanostructure region are two most important challenges in fabrication of any high-density photodetectors array. Practical implications – MaCE guarantees formation of reproducible, high-fidelity and controllable nanometer-size porous Si with well-defined and sharp edges of the patterned areas. Originality/value – The proposed method offers a low-cost and simple process to fabricate high-density arrays of Schottky detectors which are compatible with the complementary metal-oxide semiconductor process.

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29

Tang, Xiaoyu, Tao Hua, Yujie Liu, and Zhezhe Han. "Heterogeneous CMOS Integration of InGaAs-OI nMOSFETs and Ge pMOSFETs Based on Dual-Gate Oxide Technique." Micromachines 13, no. 11 (October 23, 2022): 1806. http://dx.doi.org/10.3390/mi13111806.

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A compatible fabrication technology for integrating InGaAs nMOSFETs and Ge pMOSFETs is developed based on the development of the two-step gate oxide fabrication strategy. The direct wafer bonding method was utilized to obtain the InGaAs-Insulator-Ge structure, providing the heterogeneous channels for CMOS integration. Superior transistor characteristics were achieved by optimizing the InGaAs gate oxide with a self-cleaning process in atomic layer deposition, and modifying the Ge gate oxide by the ozone post oxidation (OPO) technique, in the sequential two-step gate oxide fabrication process. With the combination of the gate-first fabrication process, superior on- and off-state characteristics, i.e., on current up to 8.3 µA/μm and leakage as low as 10−6 µA/μm, have been demonstrated in the integrated MOSFETs, together with the preferable symmetric output characteristics that promises excellent CMOS performances.

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30

Pérez-Campos, A., G. F. Iriarte, J. Hernando-Garcia, and F. Calle. "Post-CMOS compatible high-throughput fabrication of AlN-based piezoelectric microcantilevers." Journal of Micromechanics and Microengineering 25, no. 2 (January 15, 2015): 025003. http://dx.doi.org/10.1088/0960-1317/25/2/025003.

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31

Smith, Melissa Alyson, Isaac Weaver, and Mordechai Rothschild. "Wafer-scale fabrication of CMOS-compatible, high aspect ratio encapsulated nanochannels." Journal of Vacuum Science & Technology B 36, no. 5 (September 2018): 051801. http://dx.doi.org/10.1116/1.5034463.

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32

Musick, Katherine M., Joel R. Wendt, Paul J. Resnick, Michael B. Sinclair, and D. Bruce Burckel. "Assessing the manufacturing tolerances and uniformity of CMOS compatible metamaterial fabrication." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 36, no. 1 (January 2018): 011208. http://dx.doi.org/10.1116/1.5009918.

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33

Vitale, Wolfgang A., Clara F. Moldovan, Antonio Paone, Andreas Schüler, and Adrian M. Ionescu. "Fabrication of CMOS-compatible abrupt electronic switches based on vanadium dioxide." Microelectronic Engineering 145 (September 2015): 117–19. http://dx.doi.org/10.1016/j.mee.2015.03.055.

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34

Xiao, Jing, Fuchuan Song, Kijeong Han, and Sang-Woo Seo. "Fabrication of CMOS-compatible optical filter arrays using gray-scale lithography." Journal of Micromechanics and Microengineering 22, no. 2 (January 13, 2012): 025006. http://dx.doi.org/10.1088/0960-1317/22/2/025006.

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35

Yu, Huiyang, Xuke Yu, and Yifeng Li. "Design, fabrication and optimization of a CMOS compatible capacitive pressure sensor." Journal of Micromechanics and Microengineering 29, no. 2 (January 4, 2019): 025009. http://dx.doi.org/10.1088/1361-6439/aaf599.

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36

Karam, J. M., B. Courtois, and J. M. Paret. "Collective fabrication of microsystems compatible with CMOS through the CMP service." Materials Science and Engineering: B 35, no. 1-3 (December 1995): 219–23. http://dx.doi.org/10.1016/0921-5107(95)01337-7.

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37

Sugimoto, Yasuhiro, Hiroyuki Hara, Tsutomu Koyanagi, and Hiroyuki Miyakawa. "Fabrication and Evaluation of the ECL/TTL Compatible BI-CMOS Gate Array." IEEJ Transactions on Electronics, Information and Systems 108, no. 12 (1988): 981–88. http://dx.doi.org/10.1541/ieejeiss1987.108.12_981.

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38

Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (October 8, 2019): 4340. http://dx.doi.org/10.3390/s19194340.

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Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper presents several promising designs of CNT growth microstructures and their thermomechanical analyses (by ANSYS Multiphysics software) to check the feasibility of local CNT synthesis in CMOS. Standard CMOS processes have several conductive interconnecting metal and polysilicon layers, both being suitable to serve as microheaters for local resistive heating to achieve the CNT growth temperature. Most of these microheaters need to be partially or fully suspended to produce the required thermal isolation for CMOS compatibility. Necessary CMOS post-processing steps to realize CNT growth structures are discussed. Layout designs of the microstructures, along with some of the microstructures fabricated in a standard AMS 350 nm CMOS process, are also presented in this paper.

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39

Faruque, M. O., R. Al Mahmud, and R. H. Sagor. "CMOS Compatible Plasmonic Refractive Index Sensor based on Heavily Doped Silicon Waveguide." Engineering, Technology & Applied Science Research 10, no. 1 (February 3, 2020): 5295–300. http://dx.doi.org/10.48084/etasr.3264.

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In this study, a plasmonic refractive index (RI) sensor using heavily n-doped silicon waveguide is designed and numerically simulated using finite element method (FEM). The reported sensor is based on gratings inside a heavily doped silicon waveguide structure instead of a conventional metal-insulator-metal structure. This feature enables the device to overcome the limitations of conventional plasmonic devices like optical losses, polarization management, etc. Besides, it makes the device compatible with Complementary Metal Oxide Semiconductor (CMOS) technology and thus provides an easier way of practical fabrication and incorporation in integrated circuits. The presented sensor has a highest sensitivity of 1208.9nm/RIU and a resolution as small as 0.005 which is comparable with conventional plasmonic sensors reported to date. The main advantage of this plasmonic sensor is that it has a very simple structure and uses silicon instead of metal which provides an easier way of fabrication.

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40

Tabassum, Natasha, Mounika Kotha, Vidya Kaushik, Brian Ford, Sonal Dey, Edward Crawford, Vasileios Nikas, and Spyros Gallis. "On-Demand CMOS-Compatible Fabrication of Ultrathin Self-Aligned SiC Nanowire Arrays." Nanomaterials 8, no. 11 (November 5, 2018): 906. http://dx.doi.org/10.3390/nano8110906.

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The field of semiconductor nanowires (NWs) has become one of the most active and mature research areas. However, progress in this field has been limited, due to the difficulty in controlling the density, orientation, and placement of the individual NWs, parameters important for mass producing nanodevices. The work presented herein describes a novel nanosynthesis strategy for ultrathin self-aligned silicon carbide (SiC) NW arrays (≤ 20 nm width, 130 nm height and 200–600 nm variable periodicity), with high quality (~2 Å surface roughness, ~2.4 eV optical bandgap) and reproducibility at predetermined locations, using fabrication protocols compatible with silicon microelectronics. Fourier transform infrared spectroscopy, X-ray photoelectron spectroscopy, ultraviolet-visible spectroscopic ellipsometry, atomic force microscopy, X-ray diffractometry, and transmission electron microscopy studies show nanosynthesis of high-quality polycrystalline cubic 3C-SiC materials (average 5 nm grain size) with tailored properties. An extension of the nanofabrication process is presented for integrating technologically important erbium ions as emission centers at telecom C-band wavelengths. This integration allows for deterministic positioning of the ions and engineering of the ions’ spontaneous emission properties through the resulting NW-based photonic structures, both of which are critical to practical device fabrication for quantum information applications. This holistic approach can enable the development of new scalable SiC nanostructured materials for use in a plethora of emerging applications, such as NW-based sensing, single-photon sources, quantum LEDs, and quantum photonics.

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41

Hu, Juejun, Vladimir Tarasov, Nathan Carlie, Ning-Ning Feng, Laeticia Petit, Anu Agarwal, Kathleen Richardson, and Lionel Kimerling. "Si-CMOS-compatible lift-off fabrication of low-loss planar chalcogenide waveguides." Optics Express 15, no. 19 (2007): 11798. http://dx.doi.org/10.1364/oe.15.011798.

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42

Smith, A. D., Q. Li, A. Anderson, A. Vyas, V. Kuzmenko, M. Haque, L. G. H. Staaf, P. Lundgren, and P. Enoksson. "Toward CMOS compatible wafer-scale fabrication of carbon-based microsupercapacitors for IoT." Journal of Physics: Conference Series 1052 (July 2018): 012143. http://dx.doi.org/10.1088/1742-6596/1052/1/012143.

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43

Koppinen, P. J., M. D. Stewart, and Neil M. Zimmerman. "Fabrication and Electrical Characterization of Fully CMOS-Compatible Si Single-Electron Devices." IEEE Transactions on Electron Devices 60, no. 1 (January 2013): 78–83. http://dx.doi.org/10.1109/ted.2012.2227322.

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Li, Y., W. Parkes, L. I. Haworth, A. A. Stokes, K. R. Muir, P. Li, A. J. Collin, et al. "Anodic Ta2O5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication." Solid-State Electronics 52, no. 9 (September 2008): 1382–87. http://dx.doi.org/10.1016/j.sse.2008.04.030.

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Li, Nanxi, Chong Pei Ho, Shiyang Zhu, Yuan Hsing Fu, Yao Zhu, and Lennon Yao Ting Lee. "Aluminium nitride integrated photonics: a review." Nanophotonics 10, no. 9 (June 18, 2021): 2347–87. http://dx.doi.org/10.1515/nanoph-2021-0130.

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Abstract Integrated photonics based on silicon has drawn a lot of interests, since it is able to provide compact solution for functional devices, and its fabrication process is compatible with the mature complementary metal-oxide-semiconductor (CMOS) fabrication technology. In the meanwhile, silicon material itself has a few limitations, including an indirect bandgap of 1.1 eV, transparency wavelength of >1.1 μm, and insignificant second-order nonlinear optical property. Aluminum nitride (AlN), as a CMOS-compatible material, can overcome these limitations. It has a wide bandgap of 6.2 eV, a broad transparency window covering from ultraviolet to mid-infrared, and a significant second-order nonlinear optical effect. Furthermore, it also exhibits piezoelectric and pyroelectric effects, which enable it to be utilized for optomechanical devices and pyroelectric photodetectors, respectively. In this review, the recent research works on integrated AlN photonics in the past decade have been summarized. The related material properties of AlN have been covered. After that, the demonstrated functional devices, including linear optical devices, optomechanical devices, emitters, photodetectors, metasurfaces, and nonlinear optical devices, are presented. Last but not the least, the summary and future outlook for the AlN-based integrated photonics are provided.

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González-Fernández, Alfredo A., Mariano Aceves-Mijares, Oscar Pérez-Díaz, Joaquin Hernández-Betanzos, and Carlos Domínguez. "Embedded Silicon Nanoparticles as Enabler of a Novel CMOS-Compatible Fully Integrated Silicon Photonics Platform." Crystals 11, no. 6 (May 31, 2021): 630. http://dx.doi.org/10.3390/cryst11060630.

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The historical bottleneck for truly high scale integrated photonics is the light emitter. The lack of monolithically integrable light sources increases costs and reduces scalability. Quantum phenomena found in embedded Si particles in the nanometer scale is a way of overcoming the limitations for bulk Si to emit light. Integrable light sources based in Si nanoparticles can be obtained by different CMOS (Complementary Metal Oxide Semiconductor) -compatible materials and techniques. Such materials in combination with Si3N4 photonic elements allow for integrated Si photonics, in which photodetectors can also be included directly in standard Si wafers, taking advantage of the emission in the visible range by the embedded Si nanocrystals/nanoparticles. We present the advances and perspectives on seamless monolithic integration of CMOS-compatible visible light emitters, photonic elements, and photodetectors, which are shown to be viable and promising well within the technological limits imposed by standard fabrication methods.

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Ranacher, Christian, Cristina Consani, Andreas Tortschanoff, Lukas Rauter, Dominik Holzmann, Clement Fleury, Gerald Stocker, et al. "A CMOS Compatible Pyroelectric Mid-Infrared Detector Based on Aluminium Nitride." Sensors 19, no. 11 (May 31, 2019): 2513. http://dx.doi.org/10.3390/s19112513.

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The detection of infrared radiation is of great interest for a wide range of applications, such as absorption sensing in the infrared spectral range. In this work, we present a CMOS compatible pyroelectric detector which was devised as a mid-infrared detector, comprising aluminium nitride (AlN) as the pyroelectric material and fabricated using semiconductor mass fabrication processes. To ensure thermal decoupling of the detector, the detectors are realized on a Si3N4/SiO2 membrane. The detectors have been tested at a wavelength close to the CO2 absorption region in the mid-infrared. Devices with various detector and membrane sizes were fabricated and the influence of these dimensions on the performance was investigated. The noise equivalent power of the first demonstrator devices connected to a readout circuit was measured to be as low as 5.3 × 10 − 9 W / Hz .

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Filipovic, Lado, and Siegfried Selberherr. "Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors." Nanomaterials 12, no. 20 (October 18, 2022): 3651. http://dx.doi.org/10.3390/nano12203651.

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During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication technique or a technique which is compatible with CMOS due to the inherent low costs, scalability, and potential for mass production that this technology provides. While chemiresistive semiconductor metal oxide (SMO) gas sensors have been the principal semiconductor-based gas sensor technology investigated in the past, resulting in their eventual commercialization, they need high-temperature operation to provide sufficient energies for the surface chemical reactions essential for the molecular detection of gases in the ambient. Therefore, the integration of a microheater in a MEMS structure is a requirement, which can be quite complex. This is, therefore, undesirable and room temperature, or at least near-room temperature, solutions are readily being investigated and sought after. Room-temperature SMO operation has been achieved using UV illumination, but this further complicates CMOS integration. Recent studies suggest that two-dimensional (2D) materials may offer a solution to this problem since they have a high likelihood for integration with sophisticated CMOS fabrication while also providing a high sensitivity towards a plethora of gases of interest, even at room temperature. This review discusses many types of promising 2D materials which show high potential for integration as channel materials for digital logic field effect transistors (FETs) as well as chemiresistive and FET-based sensing films, due to the presence of a sufficiently wide band gap. This excludes graphene from this review, while recent achievements in gas sensing with graphene oxide, reduced graphene oxide, transition metal dichalcogenides (TMDs), phosphorene, and MXenes are examined.

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Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

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Kuo, Yi-Shan, Shen-Yang Lee, Chia-Chin Lee, Shou-Wei Li, and Tien-Sheng Chao. "CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications." IEEE Transactions on Electron Devices 68, no. 2 (February 2021): 879–84. http://dx.doi.org/10.1109/ted.2020.3045955.

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