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Relevant bibliographies by topics / CMOS compatible fabrication

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Journal articles

Academic literature on the topic 'CMOS compatible fabrication'

Author: Grafiati

Published: 6 September 2023

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Journal articles on the topic "CMOS compatible fabrication"

1

Buyong, Muhamad Ramdzan, Norazreen Abd Aziz, and Burhanuddin Yeop Majlis. "Characterization and Optimization of Seals-Off for Very Low Pressure Sensors (VLPS) Fabricated by CMOS MEMS Process." Advanced Materials Research 74 (June 2009): 231–34. http://dx.doi.org/10.4028/www.scientific.net/amr.74.231.

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In the world of MEMS processing today, fabrications of membrane are performed using bulk micromachining (BMM). However these techniques not easiest to integrate with CMOS standard process due to not compatible of the processing flow. An attractive alternative deployment of surface micromachining (SMM). There is a trend to use surface micromachining to their advantage of simplicity in design and fabrication process compatibility. This paper presents process development of thin layer membrane for very low capacitive pressure sensor application. The structure of the membrane consists of parallel plate which both top and bottom electrodes were fixed at both sides. Utilizing CMOS MEMS process compatible fabrication of the thin layer membrane involved in three stages; i) hole opening etch, ii) sacrificial intermediate oxide release etch and iii) closing of etch holes. Therefore seals-off process characterization and optimization experiment are presented in this paper, will spur advancement in the development of a CMOS MEMS product for very low capacitive pressure sensor.

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2

Bi, Cheng, and Yanfei Liu. "CMOS-Compatible Optoelectronic Imagers." Coatings 12, no. 11 (2022): 1609. http://dx.doi.org/10.3390/coatings12111609.

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Silicon-based complementary metal oxide semiconductors have revolutionized the field of imaging, especially infrared imaging. Infrared focal plane array imagers are widely applied to night vision, haze imaging, food selection, semiconductor detection, and atmospheric pollutant detection. Over the past several decades, the CMOS integrated circuits modified by traditional bulk semiconductor materials as sensitivity sensors for optoelectronic imagers have been used for infrared imaging. However, traditional bulk semiconductor material-based infrared imagers are synthesized by complicated molecular beam epitaxy, and they are generally coupled with expensive flip-chip-integrated circuits. Hence, high costs and complicated fabrication processes limit the development and popularization of infrared imagers. Emerging materials, such as inorganic–organic metal halide perovskites, organic polymers, and colloidal quantum dots, have become the current focus point for preparing CMOS-compatible optoelectronic imagers, as they can effectively decrease costs. However, these emerging materials also have some problems in coupling with readout integrated circuits and uniformity, which can influence the quality of imagers. The method regarding coupling processes may become a key point for future research directions. In the current review, recent research progress on emerging materials for infrared imagers is summarized.

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3

Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (2020): 800. http://dx.doi.org/10.3390/mi11090800.

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The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

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4

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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5

Rasmussen, A., M. Gaitan, L. E. Locascio, and M. E. Zaghloul. "Fabrication techniques to realize CMOS-compatible microfluidic microchannels." Journal of Microelectromechanical Systems 10, no. 2 (2001): 286–97. http://dx.doi.org/10.1109/84.925785.

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6

Lv, Hongming, Huaqiang Wu, Jinbiao Liu, et al. "Inverted process for graphene integrated circuits fabrication." Nanoscale 6, no. 11 (2014): 5826–30. http://dx.doi.org/10.1039/c3nr06904d.

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7

Wu, Wenhao, Yu Yu, Wei Liu, and Xinliang Zhang. "Fully integrated CMOS-compatible polarization analyzer." Nanophotonics 8, no. 3 (2019): 467–74. http://dx.doi.org/10.1515/nanoph-2018-0205.

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AbstractPolarization measurement has been widely used in material characterization, medical diagnosis and remote sensing. However, existing commercial polarization analyzers are either bulky schemes or operate in non-real time. Recently, various polarization analyzers have been reported using metal metasurface structures, which require elaborate fabrication and additional detection devices. In this paper, a compact and fully integrated silicon polarization analyzer with a photonic crystal-like metastructure for polarization manipulation and four subsequent on-chip photodetectors for light-current conversion is proposed and demonstrated. The input polarization state can be retrieved instantly by calculating four output photocurrents. The proposed polarization analyzer is complementary metal oxide semiconductor-compatible, making it possible for mass production and easy integration with other silicon-based devices monolithically. Experimental verification is also performed for comparison with a commercial polarization analyzer, and deviations of the measured polarization angle are <±1.2%.

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8

AGARWAL, AJAY, N. BALASUBRAMANIAN, N. RANGANATHAN, and R. KUMAR. "SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER." International Journal of Nanoscience 05, no. 04n05 (2006): 445–51. http://dx.doi.org/10.1142/s0219581x06004619.

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We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper.

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9

Xiong, Chunle, Bryn Bell, and Benjamin J. Eggleton. "CMOS-compatible photonic devices for single-photon generation." Nanophotonics 5, no. 3 (2016): 427–39. http://dx.doi.org/10.1515/nanoph-2016-0022.

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AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

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10

Kang, G. B., J. M. Park, S. G. Kim, et al. "Fabrication and characterisation of CMOS compatible silicon nanowire biosensor." Electronics Letters 44, no. 16 (2008): 953. http://dx.doi.org/10.1049/el:20081876.

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