Relevant bibliographies by topics / CMOS compatible fabrication

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'CMOS compatible fabrication'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "CMOS compatible fabrication"

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Buyong, Muhamad Ramdzan, Norazreen Abd Aziz, and Burhanuddin Yeop Majlis. "Characterization and Optimization of Seals-Off for Very Low Pressure Sensors (VLPS) Fabricated by CMOS MEMS Process." Advanced Materials Research 74 (June 2009): 231–34. http://dx.doi.org/10.4028/www.scientific.net/amr.74.231.

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In the world of MEMS processing today, fabrications of membrane are performed using bulk micromachining (BMM). However these techniques not easiest to integrate with CMOS standard process due to not compatible of the processing flow. An attractive alternative deployment of surface micromachining (SMM). There is a trend to use surface micromachining to their advantage of simplicity in design and fabrication process compatibility. This paper presents process development of thin layer membrane for very low capacitive pressure sensor application. The structure of the membrane consists of parallel plate which both top and bottom electrodes were fixed at both sides. Utilizing CMOS MEMS process compatible fabrication of the thin layer membrane involved in three stages; i) hole opening etch, ii) sacrificial intermediate oxide release etch and iii) closing of etch holes. Therefore seals-off process characterization and optimization experiment are presented in this paper, will spur advancement in the development of a CMOS MEMS product for very low capacitive pressure sensor.
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Bi, Cheng, and Yanfei Liu. "CMOS-Compatible Optoelectronic Imagers." Coatings 12, no. 11 (October 22, 2022): 1609. http://dx.doi.org/10.3390/coatings12111609.

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Silicon-based complementary metal oxide semiconductors have revolutionized the field of imaging, especially infrared imaging. Infrared focal plane array imagers are widely applied to night vision, haze imaging, food selection, semiconductor detection, and atmospheric pollutant detection. Over the past several decades, the CMOS integrated circuits modified by traditional bulk semiconductor materials as sensitivity sensors for optoelectronic imagers have been used for infrared imaging. However, traditional bulk semiconductor material-based infrared imagers are synthesized by complicated molecular beam epitaxy, and they are generally coupled with expensive flip-chip-integrated circuits. Hence, high costs and complicated fabrication processes limit the development and popularization of infrared imagers. Emerging materials, such as inorganic–organic metal halide perovskites, organic polymers, and colloidal quantum dots, have become the current focus point for preparing CMOS-compatible optoelectronic imagers, as they can effectively decrease costs. However, these emerging materials also have some problems in coupling with readout integrated circuits and uniformity, which can influence the quality of imagers. The method regarding coupling processes may become a key point for future research directions. In the current review, recent research progress on emerging materials for infrared imagers is summarized.
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Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (August 24, 2020): 800. http://dx.doi.org/10.3390/mi11090800.

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The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.
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Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.
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Rasmussen, A., M. Gaitan, L. E. Locascio, and M. E. Zaghloul. "Fabrication techniques to realize CMOS-compatible microfluidic microchannels." Journal of Microelectromechanical Systems 10, no. 2 (June 2001): 286–97. http://dx.doi.org/10.1109/84.925785.

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Lv, Hongming, Huaqiang Wu, Jinbiao Liu, Can Huang, Junfeng Li, Jiahan Yu, Jiebin Niu, Qiuxia Xu, Zhiping Yu, and He Qian. "Inverted process for graphene integrated circuits fabrication." Nanoscale 6, no. 11 (2014): 5826–30. http://dx.doi.org/10.1039/c3nr06904d.

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Wu, Wenhao, Yu Yu, Wei Liu, and Xinliang Zhang. "Fully integrated CMOS-compatible polarization analyzer." Nanophotonics 8, no. 3 (January 31, 2019): 467–74. http://dx.doi.org/10.1515/nanoph-2018-0205.

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AbstractPolarization measurement has been widely used in material characterization, medical diagnosis and remote sensing. However, existing commercial polarization analyzers are either bulky schemes or operate in non-real time. Recently, various polarization analyzers have been reported using metal metasurface structures, which require elaborate fabrication and additional detection devices. In this paper, a compact and fully integrated silicon polarization analyzer with a photonic crystal-like metastructure for polarization manipulation and four subsequent on-chip photodetectors for light-current conversion is proposed and demonstrated. The input polarization state can be retrieved instantly by calculating four output photocurrents. The proposed polarization analyzer is complementary metal oxide semiconductor-compatible, making it possible for mass production and easy integration with other silicon-based devices monolithically. Experimental verification is also performed for comparison with a commercial polarization analyzer, and deviations of the measured polarization angle are <±1.2%.
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AGARWAL, AJAY, N. BALASUBRAMANIAN, N. RANGANATHAN, and R. KUMAR. "SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER." International Journal of Nanoscience 05, no. 04n05 (August 2006): 445–51. http://dx.doi.org/10.1142/s0219581x06004619.

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We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper.
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Xiong, Chunle, Bryn Bell, and Benjamin J. Eggleton. "CMOS-compatible photonic devices for single-photon generation." Nanophotonics 5, no. 3 (September 1, 2016): 427–39. http://dx.doi.org/10.1515/nanoph-2016-0022.

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AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.
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Kang, G. B., J. M. Park, S. G. Kim, J. G. Koo, J. H. Park, Y. S. Sohn, and Y. T. Kim. "Fabrication and characterisation of CMOS compatible silicon nanowire biosensor." Electronics Letters 44, no. 16 (2008): 953. http://dx.doi.org/10.1049/el:20081876.

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Dissertations / Theses on the topic "CMOS compatible fabrication"

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DiLello, Nicole Ann. "Fabrication and simulation of CMOS-compatible photodiodes." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43039.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 65-67).
CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber optic telecommunications systems and they have the potential to be integrated in a number of applications. This thesis focuses on germanium photodiodes to be used in an integrated electronic-photonic analog-to-digital converter. It specifically studies the dark current, responsivity, and frequency response of Ge-on-Si LPCVD-grown diodes that will be used in such a system. It outlines a process that can be used to add metal contacts to pre-existing diodes and discusses characterization procedure. It was found that previously fabricated 50 pm square diodes had leakage current of 0.25 uA at -1 V, but responsivity of -5 mA/W. Diodes with higher leakage current, 1.1 piA at -1 V, had a higher responsivity of -0.5 A/W. Spreading resistance profiles (SRP) indicate that better control of the n-type contact is needed to systematically reproduce these results. Furthermore, spreading resistance analysis demonstrated that elimination of the p-type seed during growth will result in a more abrupt junction, for which simulations predict an improved frequency response. Simulations indicate that removal of the p-type seed and associated autodoping should increase the frequency response from -1.6 GHz to 1-4 GHz. Better control of the n-type profile can further increase the frequency response from '14 GHz to -27 GHz.
by Nicole Ann DiLello.
S.M.
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Gantz, Kevin Francis. "Fabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Cooling." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/35863.

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A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized.
Master of Science
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Ben, Masaud Taha. "Development of low temperature fabrication processes of n-ZnO/p-Si optical switch and poly-silicon waveguides for CMOS-compatible multi-layered silicon photonics." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/370612/.

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The potential advantages and applications of Silicon Photonics (SiP) has initiated substantial research efforts. Silicon photonics has been favourably nominated to replace the current copper interconnects due to their high bandwidth, small footprint, and potentially low power consumption. However, the majority of the research into silicon photonics has been based on the silicon-on insulator (SOI) platform. The focus on the SOI platform has limited the design of silicon photonic devices to two-dimensional (2D) structures. Moreover, the fabrication of optical active devices based on silicon photonics has relied on high temperature processing that is not compatible with CMOS back-end integration. New materials that are depositable at low temperatures can offer new possibilities for multi-layered, CMOS back-end compatible, and low optical loss silicon photonic devices. In this project, zinc oxide (ZnO) was investigated as a potential low temperature material whose fabrication is compatible with CMOS technology. Specifically, the naturally n-type doped ZnO can potentially form a heterojunction with p-type silicon without the need for high temperature processing. Poly-silicon is also a depositable and CMOS compatible material that can potentially form future multi-layered silicon photonic structures. However, low optical loss in poly-silicon has been based on high-temperature processing to improve the crystallinity and roughness of the deposited material. The deposition of poly-silicon in the SiP technology have been mainly carried out using plasma-enhanced chemical vapour deposition (PECVD) and other deposition techniques remain under investigated. In this project, ZnO was, for the first time, deposited at low-temperature (150 ˚C) using atomic layer deposition (ALD) on a silicon waveguide to form a heterojunction diode capable of producing optical switching in the silicon core. Optical switching in the n-ZnO/p-Si heterojunction was caused by the plasma dispersion effect. The design of the optical switch comprised a straight silicon waveguide (width = 1000 nm, height = 220 nm, slabheight = 60 nm) partially covered with a thin ZnO film (thickness = 10 nm). The commonly used highly doped p+ region were not included in the devices because of the high thermal budget (T ' 900 ˚C) needed to activate the dopant. Moreover, the aluminium (Al) metal contacts were not annealed because the annealing temperature (Ts = 425˚C) exceeds the high-temperature threshold (Ts = 400˚C). An extinction ratio of ~ 10 dB was achieved for a 1 mm long device at 20 V forward-bias. This result can be expressed as a figure of merit of 5 dB/cm.V. The insertion loss of the device was estimated to be ~ 1:2 dB. The maximum switching speed of the devices was found to be ~1 MHz. Al-though this performance is inferior to the state-of-the-art silicon optical switches, it offers the first silicon-based electro-optical switch fabricated at low-temperatures with low insertion loss. Detailed analysis of the I-V and switching characteristics of the device revealed large series resistance and capacitance. It was also found that the switching speed is primarily governed by the RC time constant of the device rather than the minority carrier lifetime. This fact has led us to believe that the device functions as both injection and accumulation electro-absorption switch. A thin SiO2 layer is suspected to form at the ZnO/Si interface that facilitates the accumulation operation of the device and increases the RC time constant. The first low loss and low-temperature poly-silicon waveguides are demonstrated in this project. Hot-wire chemical vapour deposition (HWCVD) was used to deposit poly-silicon films at 240˚C. The propagation loss of the TE mode for a 600 by 220 nm waveguide was 13:5 dB/cm. Detailed simulation analysis revealed that at least 60% of the loss was caused by the roughness of the top surface of the waveguides. The RMS roughness was measured using atomic force microscopy (AFM) and was found to be 8:9 nm. Optimisation of the design, the deposition process, and the reduction of the top surface roughness, through surface planarisation, led to a reduction in the propagation loss of the TE mode to ~8:5 dB/cm while still maintaining low deposition temperature of 360˚C. The crystal volume fraction of the optimised poly-silicon film was found to be ~96%. An electro-optical switch based on ZnO and poly-silicon heterojunction was fabricated on a multi-layered poly silicon structure. However, there were problems with the metal contact pads as well as the thickness of the first poly-silicon layer. Future work will focus on improving the n-ZnO/p-Si heterojunction electro-optical performance by adapting an accumulation type structure as well as optimising the multi-layered poly-silicon platform.
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Joo, Nicoleta. "Nouveaux dérivés de polyoxométallates (POMs) pour des mémoires moléculaires compatibles avec des procédés de fabrication CMOS." Grenoble, 2010. http://www.theses.fr/2010GRENV031.

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L'objectif de cette thèse est d'étudier la miniaturisation des dispositifs à mémoire non-volatile, de type FLASH, en remplaçant la grille flottante avec des monocouches de molécules redox, les polyoxométallates. Dans ce but, j'ai été engagé dans un programme visant à construire des dispositifs qui utilisent les propriétés des polyoxométallates (POMs) pour stocker des informations. Dans une approche générale, une molécule redox-active fixée à une surface d'électrode de silicium sert de support de stockage actif, et l'information est stockée dans les états d'oxydo-réduction discrets de la molécule (POM). Ce travail est organisé en quatre parties et commence par une brève introduction sur les mémoires moléculaires et les polyoxométallates. Il continue avec les résultats expérimentaux en Partie 2, la synthèse et la caractérisation des polyoxométallates fonctionnalisés; en Partie 3, les électrodes modifiés par des polyoxométallates et en Partie 4, l'étude électrique des condensateurs modifiés par des polyoxométallates
The aim of the present thesis is to study the miniaturization of non-volatile memory devices, FLASH type, by replacing the floating gate with monolayers of redox molecules, polyoxometalates. Towards this goal, I was engaged in a program aimed at constructing devices that use the properties of polyoxometalates (POMs) to store information. In a general approach, a redox-active molecule attached to an electroactive surface serves as the active storage medium, and information is stored in the discrete redox states of the molecule (POM). This work is organized in four parts and begins with a short introduction into the molecular memory and polyoxometalates field. It continues with the experimental results systematized in Part 2, synthesis and characterization of functionalized polyoxometalates; Part 3, polyoxometalates modified electrodes and Part 4, electrical investigation of the polyoxometalates modified capacitors
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Liu, Chuan-Chang, and 劉川漳. "Design、Fabrication and Characterization of Monolithic CMOS Compatible Photodetectors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/65553161667493517415.

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碩士
國立交通大學
電子工程系所
94
In this study, monolithic CMOS technology compatible photodetectors have been investigated. Using the metal as the light-blocking layer, the input light can form a spatial periodical variation to the detector. Thus, the diffusion photocurrent within the substrate can be cancelled out, and the detector response speed can be improved. A rigorous model for analyzing the detectors is adopted. All device parameters in our design have been discussed systematically for obtaining high speed operation without significantly reducing the detector responsivity. The devices were fabricated by TSMC (Taiwan Semiconductor Manufacturing Company) 0.18 um 2P6M CMOS technology. By taking VCSEL (Vertical-Cavity Surface-Emitting Laser) with input light wavelength of 850 nm as input signal, the experimental results of eye patterns of the signals show that these devices can operate at a 1.5-Gb/s datarate.
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Jhou, Cheng-Syu, and 周城旭. "Fabrication and Characterization of CMOS Compatible Poly-Si/SiGe Thermoelectric Microcoolers." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/42609737992501356712.

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碩士
國立中央大學
電機工程學系
103
Silicon and germanium are the best semiconductor material choices for the integrated circuit for their material robustness and the fabrication process compatibility. Therefore, placement of SiGe thermoelectric microcoolers into integrated circuits to cool local hot spots is one of the promising, optimal solution to solve the heat problem in the future. Our research group has fabricated and explored the characteristics of thermal conductivity and electrical conductivity for 100 nm-wide poly-SiGe-pillars-array. Extensive experimental results show that 100 nm-wide, poly-SiGe nanopillars array with the Ge mole concentration of 24% possess, the estimated thermoelectric figure of merit (ZT) to up to 0.5 at 300 K. In this thesis, we have fabricated poly-Si and poly-Si0.76Ge0.24 P-N pillars (diameter of 250 nm/ height of 1 μm) arrays with various of area size in 17 × 12 μm2, 37 × 32 μm2 and 56 × 52 μm2. P-N pillars were produced by ion implantation of Boron/1 × 1020 cm-3 as P-dopants and Phosphorus/1 × 1020 cm-3 for N-type donors, respectively. Following nickel evaporation and silicidation and rapid-thermal annealing, NiSi/NiSiGe nanocontacts were produced to connect the bottom of N- and P-pillars. Also aluminum top electrodes form by thermal evaporation of aluminum in conjunction with lift-off process were formed to bridge the top of pillars, the P-/N- pair SiGe nanopillar thermoelectric microcooler. We systematically investigated effects of the array size and Ge concentration of poly-SiGe nanopillars on cooling capability at test conditions of the environmental temperature at 30, 60 and 90 oC as well as the driving current of 1, 3, 5, 7, 9 and 11 μA, respectively. Experimental results suggest that the poly-Si0.76Ge0.24 thermoelectric cooler with areas size of 37 × 32 µm2 possesses the best of the cooling capability with cooling temperature up to 15 oC for the condition of environmental temperature at 90 oC, and driving current at 11 μA.
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Yang, Chiu-Chin, and 楊久進. "Fabrication of Carbon Nanotube Field-Effect Transistor Compatible with CMOS Process." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/9z4n68.

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碩士
國立臺北科技大學
機電整合研究所
96
The main objectives of this thesis aim to fabricate Carbon nanotube field-effect transistors (CNTFETs) combined with standard CMOS process. In this thesis, we will discuss the properties and fabrication of carbon nanotubes electronic devices on a CMOS chips. This research utilizes several kinds of techniques to reach purposes, such as, low temperature fabrication, manipulate technique (dielectrophoresis force), localized techniques, and surface modification by self-assembled monolayer (SAM), and moreover, to investigate the standard electrical transport characteristics of these CNTFETs. In the experimental process, the SWCNTs-based electronic devices microstructures are fabricated by standard CMOS process and wet etching process (post-process). Finally, CNTs are deposited and aligned CNTs on the predefined electrode pairs by using alternating current dielectrophoresis (AC-DEP) or photo resist defined adherent region for CNTs to complete the fabrication of SWCNTs-based electronic devices fabrication. These SWCNTs-based electronic devices are successfully fabricated and characteristics of the devices possess both weak gate modulation and no gate modulation, respectively. The former shows a turn-on current of 2nA and a conducting current ration of 2-5 folds, which is similar to the conventional silicon-based p-channel MOSFETs, while the latter is similar to characteristics of resistors. After utilizing the electroless plating to replace the low work function of TiN electrodes (~3.74eV) with the high work function of Ni/Au electrodes (~5.1eV), the formation of an improved metal-CNT contact and the reduced probabilities of surface oxidation help improve the performance of the CNT devices and promote the current of more than 10 times. Finally, the ideal of novel chemical and bio sensors, which relies on the CNTFETs technology combined with CMOS circuitry can be made on a single chip in the future.
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Chang, Po-Chih, and 張博智. "Fabrication of Carbon Nanotube Gas Sensor Device Compatible with CMOS Processes." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/62wtdm.

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碩士
國立臺北科技大學
機電整合研究所
97
The study demonstrates the low temperature fabrication of CMOS compatible gas sensor based on CNTs. To begin with, the SIO2 on the silicon wafer was modified by APTS in order to form an aminoterminated (–NH2) self-assembled monolayer (SAM), which could facilitate the chemical bonding between CNTs and amino-groups. By means of it, CNTs were immobilized on SIO2 to be the thin film of gas sensing. Photolithography and Evaporato were then implemented to develop micro parallel electrodes. At last, Lift-off was used to complete the fabrication. In this study, we not only successfully apply the fabrication to the purpose of mass production, but also integrate it with CMOS circuits to achieve System on Chip (SoC). Moreover, from the experiment, laser trimming was proved to modulate the initial resistance of the gas sensors. The initial resistance of sensors ranged from a few hundred Ω to a few thousand Ω at room temperate. The difference of resistance resulted from the amount of CNTs which bridged the parallel electrodes and the material use of the parallel electrodes. Laser trimming could also be used to adjust the resistance of the array of CNT gas sensors. In the future, the sensors will be designed with the specificity of specific gas by modifying CNTs. Moreover, the sensors will be integrated with CMOS circuits for the purpose of wearable SoC.
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Cheng, Chih-Ching, and 鄭智璟. "Fabrication of Ferroelectric Negative Capacitance MOSFETs and Self-Aligned Fin-Shaped TFETs Compatible with CMOS Process." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/27126023298927217666.

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碩士
國立臺灣師範大學
光電科技研究所
103
The enhancement performance of steep swing may reduce power consumption and be a candidate of next generation technology node in CMOS industry.In this work, the superior subthreshold swing is obtained by NC effect with dielectric CET=0.98nm, which the combination of HfOX/ZrOX was used. The self-aligned fin-shaped TFET without space between gate and source/drain is demonstrated successfully, and the fabrication process using all i-line photolithograph stepper without e-beam writer. The high ON current (> 10A) is obtained and indicates the benefit of self-alignment process. The proposed fin-shaped TFET process leads the opportunity of the advanced devices fabrication by 6-inch process with i-line photolithograph stepper.
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Bayat, Khadijeh. "Design, Simulation and Fabrication of Photonic Crystal Slab Waveguide Based Polarization Processors." Thesis, 2009. http://hdl.handle.net/10012/4444.

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The Photonic Crystal (PC) is a potential candidate for a compact optical integrated circuit on a solid state platform. The fabrication process of a PC is compatible with CMOS technology; thus, it could be potentially employed in hybrid optical and electrical integrated circuits. One of the main obstacles in the implementation of an integrated optical circuit is the polarization dependence of wave propagation. Our goal is to overcome this obstacle by implementing PC based polarization controlling devices. One of the crucial elements of polarization controlling devices is the polarization rotator. The polarization rotator is utilized to manipulate and rotate the polarization of light. In this thesis, we have proposed, designed and implemented an ultra-compact passive PC based polarization rotator. Passive polarization rotator structures are mostly composed of geometrically asymmetric structures. The polarization rotator structure consists of a single defect line PC slab waveguide. The geometrical asymmetry has been introduced on top of the defect line as an asymmetric loaded layer. The top loaded layer is asymmetric with respect to the z-axis propagation direction. To synchronize the power conversion and avoid power conversion reversal, the top loaded layer is alternated around the z-axis periodically. The structure is called periodic asymmetric loaded PC slab waveguide. Due to the compactness of the proposed structure, a rigorous numerical method, 3D-FDTD can be employed to analyze and simulate the final designed structure. For the quick preliminary design, an analytical method that provides good approximate values of the structural parameters is preferred. Coupled-mode theory is a robust and well-known method for such analyses of perturbed waveguide structures. Thus, a coupled-mode theory based on semi-vectorial modes was developed for propagation modeling on square hole PC structures. In essence, we wish to develop a simple yet closed form method to carry out the initial design of the device of interest. In the next step, we refined the design by using rigorous but numerically expensive 3D-FDTD simulations. We believe this approach leads to optimization of the device parameters easily, if desired. To extend the design to a more general shape PC based polarization rotator, a design methodology based on hybrid modes of asymmetric loaded PC slab waveguide was introduced. The hybrid modes of the structure were calculated utilizing the 3D-FDTD method combined with the Spatial Fourier Transform (SFT). The propagation constants and profile of the slow and fast modes of an asymmetric loaded PC slab waveguide were extracted from the 3D-FDTD simulation results. The half-beat length, which is the length of each loaded layer, and total number of the loaded layers are calculated using the aforementioned data. This method provides the exact values of the polarization rotator structure’s parameter. The square hole PC based polarization rotator was designed employing both coupled-mode theory and normal modal analysis for THz frequency applications. Both design methods led to the same results. The design was verified by the 3D-FDTD simulation of the polarization rotator structure. For a square hole PC polarization rotator, a polarization conversion efficiency higher than 90% over the propagation distance of 12 λ was achieved within the frequency band of 586.4-604.5 GHz corresponding to the normalized frequency of 0.258-0.267. The design was extended to a circular hole PC based polarization rotator. A polarization conversion efficiency higher than 75% was achieved within the frequency band of 600-604.5 GHz. The circular hole PC polarization rotator is more compact than the square-hole PC structure. On the other hand, the circular hole PC polarization rotator is narrow band in comparison with the square hole PC polarization rotator. In a circular hole PC slab structure, the Bloch modes (fast and slow modes) couple energy to the TM-like PC slab modes. In both square and circular hole PC slab structures with finite number of rows, and the TM-like PC slab modes are extended to the lower edge of the bandgap. In bandgap calculation using PWEM, it is assumed that the PC structure is extended to infinity, however in practice the number of rows is limited, which is the source of discrepancy between the bandgap calculation using PWEM and 3D-FDTD. In an asymmetric loaded circular hole PC slab waveguide, the leaky TM-like PC slab modes are extended deep inside the bandgap and overlapped with both the slow and fast Bloch modes; whereas, in an asymmetric loaded square hole PC slab waveguide, the leaky TM-like PC slab modes are below the frequency band of slow and fast modes. Therefore, TM-like PC slab modes have significantly more adverse effect on the performance of the circular-hole based polarization rotator leading to a narrow band structure. SOI based PC membrane technology for THz application was developed. The device layer is made of highly resistive silicon to maintain low loss propagation for THz wave. The PC slab waveguide and polarization rotators were fabricated employing this technology. Finally, an a-SiON PC slab waveguide structures were also fabricated at low temperature for optical applications. This technology has the potential to be implemented on any substrate or CMOS chips.
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Book chapters on the topic "CMOS compatible fabrication"

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Ojur, John, Farooq Ahmad, and M. Haris. "CMOS Compatible Bulk Micromachining." In Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies. InTech, 2013. http://dx.doi.org/10.5772/55526.

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Cai, Jin, and Tak Ning. "SiGe HBTs on CMOS-Compatible SOI." In Fabrication of SiGe HBT BiCMOS Technology. CRC Press, 2007. http://dx.doi.org/10.1201/9781420066890.ch5.

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"SiGe HBTs on CMOS-Compatible SOI." In Fabrication of SiGe HBT BiCMOS Technology, 63–78. CRC Press, 2018. http://dx.doi.org/10.1201/9781315218892-13.

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Conference papers on the topic "CMOS compatible fabrication"

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Gaugel, Daniel M., and Kaigham J. Gabriel. "CMOS-Compatible Micro-Fluidic Chip Cooling Using Buried Channel Fabrication." In ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-33644.

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We present a CMOS-compatible method of fabricating burried channels within bulk single-crystal silicon serving as the substrate of CMOS circuitry. The channels were designed to provide a compact, forced convection heat transfer liquid cooling approach to microprocessor and integrated circuit thermal management. The baseline fabrication process consumers 8–10% of front-side surface area and serves as a foundation for incorporation of buried-channel cooling with CMOS electronics. Channels were fabricated with diameters ranging from 43–92 μm with sacrificial surface area trenches 10 μm wide. A microchannel heat transfer solution was designed, simulated, and tested with cooling of up to 21 W/cm2. Compatibility with CMOS electronics was investigated by evaluating the post-process transistor performance of a simple oscillator circuit.
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Chen, H. Y., C. Y. Lin, M. C. Chen, H. C. Chen, C. C. Huang, and C. H. Chien. "Fabrication of CMOS-compatible Poly-Si Nanowire FET Sensor." In 2010 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2010. http://dx.doi.org/10.7567/ssdm.2010.g-9-2.

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Yamaguchi, Takuto, Hironobu Yoshimi, Miyoshi Seki, Minoru Ohtsuka, Nobuyuki Yokoyama, Yasutomo Ota, Makoto Okano, and Satoshi Iwamoto. "Fabrication of valley photonic crystals with CMOS-compatible process." In 2021 26th Microoptics Conference (MOC). IEEE, 2021. http://dx.doi.org/10.23919/moc52031.2021.9598129.

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Saffih, Faycal, Amro M. Elshurafa, Mohammad Ali Mohammad, Nathaniel Nelson-Fitzpatrick, and Stephane Evoy. "Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors." In 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS). IEEE, 2012. http://dx.doi.org/10.1109/newcas.2012.6329024.

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Dai, Pengfei, Na Lu, Anran Gao, Yuelin Wang, and Tie Li. "CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array." In 2015 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP). IEEE, 2015. http://dx.doi.org/10.1109/dtip.2015.7160980.

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Heck, John, Richard Jones, and Mario J. Paniccia. "CMOS-compatible fabrication, micromachining, and bonding strategies for silicon photonics." In SPIE MOEMS-MEMS, edited by Winston V. Schoenfeld, Jian Jim Wang, Marko Loncar, and Thomas J. Suleski. SPIE, 2011. http://dx.doi.org/10.1117/12.878499.

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Eibelhuber, M., T. Uhrmann, and T. Glinsner. "CMOS compatible fabrication of 3D photonic crystals by nanoimprint lithography." In SPIE OPTO, edited by Wibool Piyawattanametha and Yong-Hwa Park. SPIE, 2015. http://dx.doi.org/10.1117/12.2084583.

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Notaros, Milica, Thomas Dyer, Ashton Hattori, Kevin Fealey, Seth Kruger, and Jelena Notaros. "Flexible Wafer-Scale Silicon-Photonics Fabrication Platform." In Frontiers in Optics. Washington, D.C.: Optica Publishing Group, 2022. http://dx.doi.org/10.1364/fio.2022.fw1e.3.

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We develop a wafer-scale CMOS-compatible platform and fabrication process that results in 300-mm-diameter flexible wafers, and experimentally demonstrate key functionality at visible wavelengths, including chip coupling, waveguide routing, and passive devices.
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Grabulosa i Vallmajó, Adria, Johnny Moughames, Xavier Porte, and Daniel Brunner. "3D additive fabrication for CMOS-compatible integration of scalable neural networks." In Advanced Fabrication Technologies for Micro/Nano Optics and Photonics XVI, edited by Georg von Freymann, Eva Blasco, and Debashis Chanda. SPIE, 2023. http://dx.doi.org/10.1117/12.2650043.

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Burckel, D. Bruce, and Katherine M. Musick. "Fabrication and Characterization of Large Area Plasmonic Metasurface Lenses." In Frontiers in Optics. Washington, D.C.: Optica Publishing Group, 2022. http://dx.doi.org/10.1364/fio.2022.fm5c.4.

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Metasurface lenses are fabricated using membrane projection lithography following a CMOS-compatible process flow. The lenses are 10-mm in diameter and employ 3-dimensional unit cells designed to function in the mid-infrared spectral range.
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