Relevant bibliographies by topics / CMOS applications

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CMOS applications'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "CMOS applications"

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Banerjee, Sanjay K., Leonard Franklin Register, Emanuel Tutuc, Dipanjan Basu, Seyoung Kim, Dharmendar Reddy, and Allan H. MacDonald. "Graphene for CMOS and Beyond CMOS Applications." Proceedings of the IEEE 98, no. 12 (December 2010): 2032–46. http://dx.doi.org/10.1109/jproc.2010.2064151.

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Balaji, G. Naveen, S. Karthikeyan, and M. Merlin Asha. "0.18µm CMOS Comparator for High-Speed Applications." International Journal of Trend in Scientific Research and Development Volume-1, Issue-5 (August 31, 2017): 671–74. http://dx.doi.org/10.31142/ijtsrd2356.

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Sukhavasi, Susrutha Babu, Suparshya Babu Sukhavasi, Khaled Elleithy, Shakour Abuzneid, and Abdelrahman Elleithy. "CMOS Image Sensors in Surveillance System Applications." Sensors 21, no. 2 (January 12, 2021): 488. http://dx.doi.org/10.3390/s21020488.

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Recent technology advances in CMOS image sensors (CIS) enable their utilization in the most demanding of surveillance fields, especially visual surveillance and intrusion detection in intelligent surveillance systems, aerial surveillance in war zones, Earth environmental surveillance by satellites in space monitoring, agricultural monitoring using wireless sensor networks and internet of things and driver assistance in automotive fields. This paper presents an overview of CMOS image sensor-based surveillance applications over the last decade by tabulating the design characteristics related to image quality such as resolution, frame rate, dynamic range, signal-to-noise ratio, and also processing technology. Different models of CMOS image sensors used in all applications have been surveyed and tabulated for every year and application.
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Faramarzpour, Naser, Munir EL-DESOUKI, M. Deen, Qiyin Fang, Shahramshirani, and L. W. C. Liu. "CMOS imaging for biomedical applications." IEEE Potentials 27, no. 3 (May 2008): 31–36. http://dx.doi.org/10.1109/mpot.2008.916105.

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Hosticka, B. J., W. Brockherde, A. Bussmann, T. Heimann, R. Jeremias, A. Kemna, C. Nitta, and O. Schrey. "CMOS imaging for automotive applications." IEEE Transactions on Electron Devices 50, no. 1 (January 2003): 173–83. http://dx.doi.org/10.1109/ted.2002.807258.

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Mingam, H. "CMOS technologies for logic applications." Microelectronic Engineering 15, no. 1-4 (October 1991): 243–52. http://dx.doi.org/10.1016/0167-9317(91)90222-y.

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Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (June 17, 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.
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Bolaños-Pérez, Ricardo, José Miguel Rocha-Pérez, Alejandro Díaz-Sánchez, Jaime Ramirez-Angulo, and Esteban Tlelo-Cuautle. "CMOS Analog AGC for Biomedical Applications." Electronics 9, no. 5 (May 25, 2020): 878. http://dx.doi.org/10.3390/electronics9050878.

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In this paper, we present the design of an analog Automatic Gain Control with a small silicon area and reduced power consumption using a 0.5 μ m process. The design uses a classical approach implementing the AGC system with simple blocks, such as: peak detector, difference amplifier, four-quadrant multiplier, and inversor amplifier. Those blocks were realized by using a modified Miller type OPAMP, which allows indirect compensation, while the peak detector uses a MOS diode. The AGC design is simulated using the Tanner-Eda environment and Berkeley models BSIM49 of the On-Semiconductor C5 process, and it was fabricated through the MOSIS prototyping service. The AGC system has an operation frequency of around 1 kHz, covering the range of biomedical applications, power consumption of 200 μ W, and the design occupies a silicon area of approximately 508.8 μ m × 317.7 μ m. According to the characteristics obtained at the experimental level (attack and release time), this AGC can be applied to hearing aid systems.
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OHTA, Jun, Takuma KOBAYASHI, Toshihiko NODA, Kiyotaka SASAGAWA, and Takashi TOKUDA. "CMOS Imaging Devices for Biomedical Applications." IEICE Transactions on Communications E94.B, no. 9 (2011): 2454–60. http://dx.doi.org/10.1587/transcom.e94.b.2454.

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Bhuiyan, M. A. S., M. B. I. Reaz, L. F. Rahman, and K. N. Minhad. "Cmos spdt switch for wlan applications." IOP Conference Series: Materials Science and Engineering 78 (April 2, 2015): 012011. http://dx.doi.org/10.1088/1757-899x/78/1/012011.

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Dissertations / Theses on the topic "CMOS applications"

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Carletti, Luca. "Photonique intégrée nonlinéaire sur plate-formes CMOS compatibles pour applications du proche au moyen infrarouge." Thesis, Ecully, Ecole centrale de Lyon, 2015. http://www.theses.fr/2015ECDL0013/document.

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La photonique intégrée offre la possibilité d’exploiter un vaste bouquet de phénomènes optique nonlinéaires pour la génération et le traitement de signaux optiques sur des puces très compactes et à des débits potentiels extrêmement rapides. De nouvelles solutions et technologies de composants pourraient être ainsi réalisées, avec un impact considérable pour les applications télécom et datacom. L’utilisation de phénomènes optiques nonlinéaires (e.g. effet Kerr optique, effet Raman) permet même d’envisager la réalisation de composants actifs (e.g. amplificateurs, modulateurs, lasers, régénérateurs de signaux et convertisseurs en longueur d’onde).Pendant cette dernière décennie, les efforts ont principalement porté sur la plateforme Silicium sur isolant (SOI), profitant du fort confinement optique dans ce matériau, qui permet la miniaturisation et intégration de composants optiques clés (e.g. filtres passifs, jonctions coupleurs et multiplexeurs). Cependant, la présence de fortes pertes nonlinéaires dans ce matériau aux longueurs d’onde d’intérêt (i.e. autour de 1.55 µm dans les télécommunications) limite certaines applications pour lesquelles une forte réponse nonlinéaire est nécessaire et motive la recherche de nouvelles plates-formes, mieux adaptées. L’objectif premier de cette thèse était ainsi l’étude de matériaux alternatifs au Si cristallin, par exemple le silicium amorphe hydrogéné, alliant de très faibles pertes nonlinéaires et une compatibilité CMOS, pour la réalisation de dispositifs photoniques intégrés qui exploitent les phénomènes nonlinéaires. Alternativement, l’utilisation de longueurs d’onde plus élevées (dans le moyen-IR) permet de relaxer la contrainte sur le choix de la filière matériau, en bénéficiant de pertes nonlinéaires réduites, par exemple dans la filière SiGe, également explorée dans cette thèse. Ce travail est organisé de la façon suivante. Le premier chapitre donne un iii panorama des phénomènes nonlinéaires qui permettent de réaliser du traitement tout-optique de l’information, en mettant en évidence les paramètres clés à maitriser (confinement optique, ingénierie de dispersion) pour les composants d’optique intégrée, et en présentant le cadre de modélisation de ces phénomènes utilisé dans le travail de thèse. Il inclut également une revue des démonstrations marquantes publiées sur Silicium cristallin, donnant ainsi des points de référence pour la suite du travail. Le chapitre 2 introduit les cristaux photoniques comme structures d’optique intégrée permettant d’exalter les phénomènes nonlinéaires. On s’intéresse ici aux cavités, avec une démonstration de génération de deuxième et troisième harmoniques qui exploite un design original. Ce chapitre décrit également les enjeux associés à l’utilisation de guides à cristaux photoniques en régime de lumière lente, qui serviront de fondements pour le chapitre 4. Le chapitre 3 présente les résultats de caractérisation de la réponse nonlinéaire associée à des guides réalisés dans deux matériaux alternatifs au silicium cristallin : le silicium amorphe hydrogéné testé dans le proche infrarouge et le silicium germanium testé dans le moyen infrarouge. Le modèle présenté au chapitre 1 est exploité pour déduire la réponse de ces deux matériaux, et il est même étendu pour rendre compte d’effets nonlinéaires d’ordre plus élevé dans le cas du silicium germanium à haute longueur d’onde. Ce chapitre inclut également une discussion sur la comparaison des propriétés nonlinéaires de ces deux matériaux avec le SOI standard. Le chapitre 4 combine l’utilisation d’une plate-forme plus prometteuse que le SOI, avec des structures photoniques plus avancées que les simples guides réfractifs utilisés au chapitre 3 : il décrit l’ingénierie de modes (lents) dans des guides à cristaux photoniques en silicium amorphe hydrogéné et enterrés dans la silice. [...]
Integrated photonics offers a vast choice of nonlinear optical phenomena that could potentially be used for realizing chip-based and cost-effective all-optical signal processing devices that can handle, in principle, optical data signals at very high bit rates. The new components and technological solutions arising from this approach could have a considerable impact for telecom and datacom applications. Nonlinear optical effects (such as the optical Kerr effect or the Raman effect) can be potentially used for realizing active devices (e.g. optical amplifiers, modulators, lasers, signal regenerators and wavelength converters). During the last decade, the silicon on insulator (SOI) platform has known a significant development by exploiting the strong optical confinement, offered by this material platform, which is key for the miniaturization and realization of integrated optical devices (such as passive filters, splitters, junctions and multiplexers). However, the presence of strong nonlinear losses in the standard telecom band (around 1.55 µm) prevents some applications where a strong nonlinear optical response is needed and has motivated the research of more suitable material platforms. The primary goal of this thesis was the study of material alternatives to crystalline silicon (for instance hydrogenated amorphous silicon) with very low nonlinear losses and compatible with the CMOS process in order to realize integrated photonics devices based on nonlinear optical phenomena. Alternatively, the use of longer wavelengths (in the mid-IR) relaxes the constraints on the choice of the material platform, through taking advantage of lower nonlinear losses, for instance on the SiGe platform, which is also explored in this thesis. This work is organized as follows. In the first chapter we provide an overview of the nonlinear optical effects used to realize all optical signal processing functions, focusing on the key parameters that are essential (optical confinement and dispersion engineering) for integrated optical components, and presenting the main models used in this thesis. This chapter also includes a review of the main demonstrations reported on crystalline silicon, to give some benchmarks. Chapter 2 introduces the use of photonic crystals as integrated optical structures that can significantly enhance nonlinear optical phenomena. First we present photonic crystal cavities, with a demonstration of second and third harmonic generation that makes use of an original design. In the second part of the chapter, we describe the main features and challenges associated with photonic crystal waveguides in the slow light regime, which will be used later in chapter 4. In chapter 3, we report the experimental results related to the characterization of the optical nonlinear response of integrated waveguides made of two materials that are alternative to crystalline silicon : the hydrogenated amorphous silicon, probed in the near infrared, and the silicon germanium, probed in the mid-infrared. The model presented in chapter 1 is extensively used here for extracting the nonlinear parameters of these materials and it is also extended to account for higher order nonlinearities in the case of silicon germanium tested at longer wavelengths. This chapter also includes a comparison of the nonlinear properties of these two material platforms with respect to the standard SOI. In chapter 4, we combine the use of a material platform that is better suited than SOI for nonlinear applications with integrated photonics structures that are more advanced that those used in chapter 3. Here we describe the design of (slow) modes in photonic crystal waveguides made in hydrogenated amorphous silicon fully embedded in silica. [...]
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ALLEGRI, DANIELE GUIDO. "CMOS-Based Impedance Analyzer for Biomedical Applications." Doctoral thesis, Università degli studi di Pavia, 2017. http://hdl.handle.net/11571/1215968.

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This thesis presents a device which can be used to monitor the hydration level of patients suffering from renal diseases and who are forced to undergo regular dialysis sessions. The system comprises a skin interface and a stimulation and readout circuit. A dimensionless hydration index obtained by performing a bio impedance analysis has been proposed. The proposed device combines the tetra polar multifrequency bio impedance analysis with the 4-electrodes focused impedance measurement approach. Moreover, it combines the lock-in structure with the dual step super-heterodyne demodulation scheme. In contrast to the full analog approach, a mixed analog/digital solution is adopted. In particular, the proposed solution performs a first frequency down conversion in the analog domain and shifts the I,Q demodulation in the digital domain. This solution allows removing any sensible dual path from the analog domain with important benefits in terms of complexity, precision and power consumption. Moreover, with the adopted solution the digital demodulation step is achieved in a very simple and efficient way, without the need of high complexity digital multipliers. We compared the results obtained with a high precision LRC meter with the impedance measurement performed with the new chip and showed a relative error of less than 0.8%. In addition, a FEM model of the thorax tissue has been developed and simulated with the EIDORS toolbox. Simulated results have been compared with in-vivo measurements and we found good accordance between them.
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Muhammad, Wasim. "CMOS LNA Design for Multi-Standard Applications." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7841.

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This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.

As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.

Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.

Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.

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Scholvin, Jörg 1976. "Deeply scaled CMOS for RF power applications." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37904.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 117-140).
The microelectronics industry is striving to reduce the cost, complexity, and form factor of wireless systems through single-chip integration of analog, RF and digital functions. Driven by the requirements of the digital system components, the 90 nm and 65 nm technology nodes are currently emerging as platforms for highly integrated systems. Achieving such integration while minimizing the cost of adding specialized RF modules places high demands on the base CMOS technology. In this regard, the integration of the power amplifier (PA) function becomes an increasing challenge as technology geometries and supply voltages scale down. Gate length (Lg) scaling yields improved frequency response, promising higher power-added efficiency (PAE), a key RF PA consideration. This benefit comes at the cost of a lower drain voltage, which demands a higher output current and thus wider devices in order to produce a given output power level (Po,,). In this work, we have investigated the potential of deeply scaled CMOS for RF power applications, from 0.25 um down to 65 nm. We demonstrate the frequency and power limitations that the different CMOS technologies face, and describe the physical mechanisms that give rise to these limitations.
(cont.) We find that layout considerations, such as splitting a single large device into many smaller parallel devices, become increasingly important as the technology scales down the roadmap, both for power and frequency. We also show that parasitic resistances associated with the back-end wiring are responsible for placing an upper limit on the RF power that can be obtained for a single bond pad. We demonstrate a power density of 31 mW/mm for the 65 nm node, with PAE in excess of 60% at 4 GHz and 1 V. Similar results are obtained in 90 nm, where a peak PAE of 66% was measured at 2.2 GHz and 1 V, with a power density of 24 mW/mm. We find that efficient integrated PA functionality for many applications can be achieved even in a deeply-scaled logic CMOS technology. For low power levels (below 50 mW), we find that the 65 nm CMOS devices offer excellent efficiency (>50%) over a broad frequency range (2-8 GHz). Their RF power performance approaches that of 90 nm devices both in peak PAE and output power density. This is possible without costly PA-specific add-ons, or the use of higher voltage input-output (I/O) device options.
(cont.) However, since I/O devices are often included as part of the process, they represent a real option for PA integration because they allow for higher power densities. The 0.25 /xm I/O device that is available in the 90 nm process, when biased at Vdd = 2.5 V showed excellent results, with a peak PAE of 60% and an output power of 75 mW (125 mW/mm) at 8 GHz.
by Jörg Scholvin.
Ph.D.
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Bardyn, Jean-Paul. "Amplificateurs CMOS faible bruit pour applications sonar." Lille 1, 1990. http://www.theses.fr/1990LIL10167.

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Ce travail a pour but d'évaluer les possibilités d'une intégration monolithique d'amplificateurs à très faible bruit dans une technologie CMOS. Il présente les principales caractéristiques et limitations des dispositifs actifs de cette technologie pour des applications analogiques pointues. En particulier, le bruit 1/F du transistor MOS est caractérisé et modélisé par une approche unifiée valide pour tous les régimes de fonctionnement. Dans le cadre d'applications en acoustique sous-marine, différents critères d'optimisation de l'amplificateur sont évalués. Ils ont été implémentés au sein d'un circuit prototype original de part certains aspects de sa structure. Le niveau de performances atteint par ce circuit nous permet d'envisager le remplacement des actuels circuits hybrides BIFET. Ceci ouvre la perspective d'une intégration monolithique de chaînes en traitement de signal complètes pour des capteurs sonar.
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Chao, Yu-Lin. "Germanium channel devices for nanoscale CMOS applications." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1581637981&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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Czornomaz, Lukas. "Filière technologique hybride InGaAs/SiGe pour applications CMOS." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT013/document.

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Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe
High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits
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Dryer, Benjamin James. "Characterisation of CMOS APS technologies for space applications." Thesis, Open University, 2013. http://oro.open.ac.uk/40637/.

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In recent years, the performance of scientific CMOS active pixel sensors has been improved to the point that it is now approaching that of the current silicon sensor of choice, CCDs. For some applications, CMOS APSs is believed to present significant advantages over CCDs, such as improved radiation hardness. In this work, the effect of radiation damage on a ‘baseline’ commercial APS, e2v technologies’ Jade APS, is characterised in response to gamma, proton and heavy ion irradiation. Specific performance problems encountered during this radiation characterisation, such as dark current non-uniformity under gamma irradiation, random telegraph signals under proton irradiation, and single event effects under heavy ion irradiation are described and analyzed. The X-ray spectroscopic imaging performance of the device is measured and compared to the Ocean Colour Imager APS test array showing progress towards a high frame rate spectroscopic X-ray imager for space science. The implications of these results for using similar devices in space applications are considered. Furthermore, possible novel techniques for measuring inter-pixel responsivity non-uniformity, heavy ion detection and spectroscopy, and measuring the dynamics of radiation-induced trap formation are discussed.
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Kim, Hyung-Seuk 1976. "Low voltage CMOS frequency synthesizers for RF applications." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82607.

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Frequency synthesizers play an important role in modern communications and timing systems. The output of frequency synthesizers may be used as the local oscillator signal in superheterodyne transceivers, or in frequency modulation/demodulation. Fully integrated CMOS RF synthesizers are currently a major research topic. Several publications demonstrated improvements in a variety of aspects such as phase noise, power consumption, and tuning range. However, very low voltage frequency synthesizers are very challenging, since they usually have a limited tuning range and a relatively high phase noise. This research work demonstrates a new architecture to achieve a wide tuning range and low phase noise from a very low voltage supply. The synthesizer is fully integrated in a 0.18 mum CMOS technology covering the 5 GHz WLAN frequency range, requiring only a 1-V power supply. The second part of this thesis consists of the implementation of a 2.4-GHz fractional-N frequency synthesizer to be compatible with two MEMS resonators that resonate at 20-MHz and 70-MHz.
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Esteves, J. "La technologie CMOS-MEMS pour des applications acoustiques." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01068940.

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Récemment, des travaux montrant la faisabilité des MEMS à base de la technologie CMOS complétée par un micro-usinage en surface sans masque ont été publiés. A la différence de l'approche plus ancienne où la libération des composants MEMS a été faite par une gravure du silicium, la technologie proposée consiste en la gravure des couches d'oxyde afin de libérer les couches métalliques issues de la technologie CMOS. Ce sujet de thèse propose donc de fabriquer des microsystèmes à vocation acoustique à partir d'une technologie CMOS standard : AMS 0.35 μm. Il sera, pour cela, composé de deux parties. Dans la première partie, il s'agit de développer un procédé technologique (déterminer le type de gravure, les temps de gravure, ainsi que les dimensions extrêmes réalisables pour les structures simples en technologie CMOS). En effet, après avoir étudié les différentes possibilités de la technologie CMOS-MEMS proposées dans la littérature, un procédé CMOSMEMS a été mis au point. Ce procédé consiste à graver une couche sacrificielle d'oxyde afin de libérer des microstructures constituées des couches métalliques issues de la technologie CMOS 0.35 μm d'AMS. Le procédé est premièrement testé sur des échantillons contenant des microstructures telles que des ponts et des poutres. La seconde partie du travail est consacrée à la validation du procédé CMOS-MEMS par un développement de structures MEMS acoustiques représentées par un microphone MEMS capacitif. Dans un premier temps, un microphone MEMS capacitif a été réalisé à partir de la technologie CMOS 0.35 μm d'AMS. Après avoir pris connaissance des différents aspects de la technologie CMOS 0.35 μm d'AMS (matériaux, dimensions, règles de dessin,...), une modélisation de microphone MEMS capacitifs est proposée grâce à la réalisation d'un schéma électrique équivalent basé sur les analogies entre les domaines électrique, mécanique et acoustique. Chaque paramètre de ce circuit est déterminé par l'intermédiaire de relations connues et par des logiciels de simulation utilisant la méthode des éléments finis (ANSYS, CoventorWare). Une fois les performances des microphones estimés à partir de ce circuit équivalent, un layout, représentant les différents microphones conçus, a été créé sous Cadence afin d'être envoyé au fondeur AMS. Dès la réception des échantillons, le procédé CMOSMEMS mise en oeuvre précédemment a été appliqué afin de libérer les structures des différents dispositifs. Ensuite, une série de caractérisations a pu être réalisée sur les premiers échantillons. Ces caractérisations visent à déterminer les performances des différents dispositifs fabriqués, mais aussi à estimer les propriétés mécaniques des différentes couches utilisées pour former la structure des microphones. De cette façon, le circuit équivalent pourra être validé ou être amélioré selon les résultats obtenus.
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Books on the topic "CMOS applications"

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Ohta, Jun. Smart CMOS image sensors and applications. Boca Raton: CRC Press, 2008.

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Jamal, Deen M., and Fjeldly Tor A, eds. CMOS RF modeling, characterization and applications. River Edge, N.J: World Scientific, 2002.

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Youssef, Ahmed A., and James Haslett. Nanometer CMOS RFICs for Mobile TV Applications. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-8604-4.

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Youssef, Ahmed A. Nanometer CMOS RFICs for mobile TV applications. Dordrecht: Springer, 2010.

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Dal Fabbro, Paulo Augusto, and Maher Kayal. Linear CMOS RF Power Amplifiers for Wireless Applications. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9361-5.

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Ghafar-Zadeh, Ebrahim, and Mohamad Sawan. CMOS Capacitive Sensors for Lab-on-Chip Applications. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-3727-5.

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Limited, Mullard. High-speed CMOS: Designer's guide and applications handbook. London: Mullard, 1986.

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Yuan, Fei. CMOS active inductors and transformers: Principle, implementation, and applications. New York: Springer, 2008.

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Ye, Song. 1 V, 1.9 GHz CMOS mixers for wireless applications. Ottawa: National Library of Canada, 2001.

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Mohammadi, Behnam. A 5.8 GHz CMOS low noise amplifier for WLAN applications. Ottawa: National Library of Canada, 2003.

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Book chapters on the topic "CMOS applications"

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Ghafar-Zadeh, Ebrahim. "CMOS Capacitive Biointerfaces for Lab-on-Chip Applications." In CMOS Biomicrosystems, 215–38. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118016497.ch8.

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Siu, Christopher. "PMOS and CMOS." In Electronic Devices, Circuits, and Applications, 121–37. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-80538-8_7.

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Gharavi, Sam, Frank Chang, and Mohammed H. Gharavi. "Imaging Applications." In Ultra High-Speed CMOS Circuits, 81–104. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_7.

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Wang, Zhihua, Xiang Xie, Xinkai Chen, and Xiaowen Li. "Design Considerations of Low-Power Digital Integrated Systems for Implantable Medical Applications." In CMOS Biomicrosystems, 119–62. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118016497.ch5.

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Seo, Sungkyu, Ting-Wei Su, Anthony Erlinger, and Aydogan Ozcan. "Lensfree Imaging Cytometry and Diagnostics for Point-of-Care and Telemedicine Applications." In CMOS Biomicrosystems, 239–67. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118016497.ch9.

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El-Khatib, Ziad, Leonard MacEachern, and Samy A. Mahmoud. "Distributed RF Linearization Circuit Applications." In Distributed CMOS Bidirectional Amplifiers, 47–70. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0272-5_4.

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Zhang, Lining, Chenyue Ma, Xinnan Lin, Jin He, and Mansun Chan. "Modeling FinFETs for CMOS Applications." In Lecture Notes in Nanoscale Science and Technology, 263–84. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-02021-1_11.

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Ghosh, Sumalya, Ashis Kumar Mal, and Surajit Mal. "Amplifier Design Optimization in CMOS." In Intelligent Computing and Applications, 287–97. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2268-2_31.

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Roy, Saibal, Jeffrey Godsell, and Tuhin Maity. "Nanostructured Magnetic Materials for High-Frequency Applications." In Beyond-CMOS Nanodevices 1, 457–83. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2014. http://dx.doi.org/10.1002/9781118984772.ch15.

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Craninckx, J., and G. Van der Plas. "Low-Power ADCs for Bio-Medical Applications." In Bio-Medical CMOS ICs, 157–90. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6597-4_5.

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Conference papers on the topic "CMOS applications"

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Ji Chen and Juin J. Liou. "CMOS technology-based spiral inductors for RF applications." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570986.

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Kenji Kimura, Zhao Ming, Kaoru Nakajima, and Motofumi Suzuki. "High-resolution Rutherford backscattering spectroscopy for Nano-CMOS applications." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570980.

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Przewlocki, Henryk M. "New applications of internal photoemission to determine basic MOS system parameters." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570989.

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Gunn, Cary. "CMOS Photonics." In Integrated Photonics Research and Applications. Washington, D.C.: OSA, 2006. http://dx.doi.org/10.1364/ipra.2006.itub5.

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Reed, Mark A. "CMOS biosensor devices and applications." In 2013 IEEE International Electron Devices Meeting (IEDM). IEEE, 2013. http://dx.doi.org/10.1109/iedm.2013.6724587.

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Wang, Weng Lyang, and Shengmin Lin. "CMOS sensor for RSI applications." In SPIE Asia-Pacific Remote Sensing, edited by Haruhisa Shimoda, Xiaoxiong Xiong, Changyong Cao, Xingfa Gu, Choen Kim, and A. S. Kiran Kumar. SPIE, 2012. http://dx.doi.org/10.1117/12.977606.

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Current, Michael I., Russel A. Martin, Kyriakos Doganis, and Richard H. Bruce. "MeV Implantation For CMOS Applications." In 1985 Los Angeles Technical Symposium, edited by Michael I. Current and Devindra K. Sadana. SPIE, 1985. http://dx.doi.org/10.1117/12.946463.

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Fabel, B., T. Maul, L. Nowack, M. Sterkel, and W. Hansch. "Emerging CMOS-Devices and Applications." In 2007 International Symposium on Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441873.

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Sekitani, Tsuyoshi, Koichi Ishida, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takayasu Sakurai, and Takao Someya. "Large-area stretchable sensors with integrating organic CMOS ICs with Si-CMOS LSIs." In SPIE Photonic Devices + Applications, edited by Ruth Shinar and Ioannis Kymissis. SPIE, 2010. http://dx.doi.org/10.1117/12.861019.

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Zhang, Bohan, Mark Schiller, Kenaish Al Qubaisi, Deniz Onural, Anatol Khilo, Michael J. Naughton, and Miloš A. Popović. "Polarization-Insensitive One-Dimensional Grating Coupler Demonstrated in a CMOS-Photonics Foundry Platform." In CLEO: Applications and Technology. Washington, D.C.: Optica Publishing Group, 2022. http://dx.doi.org/10.1364/cleo_at.2022.jth3a.46.

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We demonstrate a one-dimensional dual polarization fiber-to-chip grating coupler implemented in a CMOS-photonics foundry platform, with a measured 1 dB polarization-dependent loss bandwidth of 70 nm in the O-band.
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Reports on the topic "CMOS applications"

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Mirow, Fred, and Dick Mabry. Precision CMOS Clock Oscillator for HI-G Applications. Fort Belvoir, VA: Defense Technical Information Center, April 2001. http://dx.doi.org/10.21236/ada386050.

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Potok, Thomas, Catherine Schuman, Robert Patton, Todd Hylton, Hai Li, and Robinson Pino. Neuromorphic Computing, Architectures, Models, and Applications. A Beyond-CMOS Approach to Future Computing, June 29-July 1, 2016, Oak Ridge, TN. Office of Scientific and Technical Information (OSTI), December 2016. http://dx.doi.org/10.2172/1341738.

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Nuckolls, L. CMOS ASIC (application specific integrated circuit). Office of Scientific and Technical Information (OSTI), July 1989. http://dx.doi.org/10.2172/5551185.

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Turner, S., R. Housley, and J. Schaad. The application/cms Media Type. RFC Editor, April 2014. http://dx.doi.org/10.17487/rfc7193.

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Li, Honghai, Lihwa Lin, Cody Johnson, Yan Ding, Mitchell Brown, Tanya Beck, Alejandro Sánchez, and Weiming Wu. A revisit and update on the verification and validation of the Coastal Modeling System (CMS) : report 1--hydrodynamics and waves. Engineer Research and Development Center (U.S.), September 2022. http://dx.doi.org/10.21079/11681/45444.

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This is the first part of a two-part report that revisits and updates the verification and validation (V&V) of the Coastal Modeling System (CMS). The V&V study in this part of the report focuses on hydrodynamic and wave modeling. With the updated CMS code (Version 5) and its latest graphical user interface, the Surface-water Modeling System (Version 13), the goal of this study is to revisit some early CMS V&V cases and assess some new cases on model performance in coastal applications. The V&V process includes the comparison and evaluation of the CMS output against analytical solutions, laboratory experiments in prototype cases, and field cases in and around coastal inlets and navigation projects. The V&V results prove that the basic physics incorporated are represented well, the computational algorithms implemented are accurate, and the coastal processes are reproduced well. This report provides the detailed descriptions of those test simulations, which include the model configuration, the selection of model parameters, the determination of model forcing, and the quantitative assessment of the model and data comparisons. It is to be hoped that, through the V&V process, the CMS users will better understand the model’s capability and limitation as a tool to solve real-world problems.
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Shen, Gianetto, and Tyson. L52342 Development of Procedure for Low-Constraint Toughness Testing Using a Single-Specimen Technique. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), December 2011. http://dx.doi.org/10.55274/r0010687.

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Pipelines from remote frontier regions are increasingly required to have adequate resistance to large deformations such as that caused by ground movement. In response to this, �strain-based design"� has been developed to enable assessment of imperfections at applied strains beyond yield. In addition, it is proposed to take advantage of the increased apparent toughness of pipe under low constraint, such as girth weld imperfections under axial tension, compared with the high-constraint toughness measured in conventional tests such as ASTM E1290 [1]. Application of low-constraint testing has been dvantageously applied in assessment of toughness for offshore pipeline projects. Also in the pipeline industry, demands on new pipeline projects include low design temperatures as well as high strain capacity. At the same time, increased strength is specified, which increases the level of required toughness. These factors make it increasingly important to assure weldment toughness, in particular to ensure that the failure mode remains ductile. It is well known that brittle cleavage is especially sensitive to constraint, and the availability of a toughness test that would reproduce field conditions would enable more rational development and acceptance of candidate welds and, in particular, enable more appropriate testing of weld heat-affected zones. This work was performed for specific application to surface circumferential cracks in pipe under strain-based design, for which the best constraint matching has been found to occur for clamped single-edge tension (SE(T)) specimens with H/W=10. For this geometry, a test procedure similar to that of ASTM E1820-06 for single-edge bend (SE(B)) and compact tension (C(T)) specimens was developed for J-resistance tests using a single-specimen technique. All the equations used in the procedure, including those for evaluation of J-integrals from the area under load/plastic crack mouth opening displacement (CMOD) curves, and evaluation of crack length from unloading compliance including rotation correction, were developed using finite element analysis (FEA) with a range of crack depths, focusing on a/W= 0.2 to 0.5 which is of most practical interest. The present procedure is compared with that of E1820 for SE(B) testing regarding evaluation of J-integral with crack growth correction, crack length evaluation, and correction of compliance for rotation.
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