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Journal articles on the topic 'CMOS 65 nm, 45 nm and 32 nm'

Author: Grafiati

Published: 12 October 2022

Last updated: 18 November 2022

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1

Wilk, Seth J., William Lepkowski, and Trevor J. Thornton. "32 dBm Power Amplifier on 45 nm SOI CMOS." IEEE Microwave and Wireless Components Letters 23, no. 3 (March 2013): 161–63. http://dx.doi.org/10.1109/lmwc.2013.2245413.

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2

Yadav, Vinamrata, Nikhil Saxena, and Amit Rajput. "Process Variation and Optimization of Two Stage CMOS Operational Amplifier at 45 nm and 32 nm Technology." Journal of Computational and Theoretical Nanoscience 14, no. 8 (August 1, 2017): 3653–56. http://dx.doi.org/10.1166/jctn.2017.6999.

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3

HE, Xun, Xin JIN, Minghui WANG, Dajiang ZHOU, and Satoshi GOTO. "A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E94-A, no. 12 (2011): 2609–18. http://dx.doi.org/10.1587/transfun.e94.a.2609.

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4

England, Troy D., Rajan Arora, Zachary E. Fleetwood, Nelson E. Lourenco, Kurt A. Moen, Adilson S. Cardoso, Dale McMorrow, et al. "An Investigation of Single Event Transient Response in 45-nm and 32-nm SOI RF-CMOS Devices and Circuits." IEEE Transactions on Nuclear Science 60, no. 6 (December 2013): 4405–11. http://dx.doi.org/10.1109/tns.2013.2289368.

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5

Sathishkumar, Arumugam, and Siddhan Saravanan. "A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950022. http://dx.doi.org/10.1142/s0218126619500221.

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A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

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Wei, Jiaju, and Zhigong Wang. "Characterization of on-chip balun with patterned floating shield in 65 nm CMOS." Journal of Semiconductors 32, no. 10 (October 2011): 104008. http://dx.doi.org/10.1088/1674-4926/32/10/104008.

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7

Thakkar, Chintan, Lingkai Kong, Kwangmo Jung, Antoine Frappe, and Elad Alon. "A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS." IEEE Journal of Solid-State Circuits 47, no. 4 (April 2012): 952–68. http://dx.doi.org/10.1109/jssc.2012.2184651.

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Magnone, Paolo, Felice Crupi, Nicole Wils, Ruchil Jain, Hans Tuinhout, Pietro Andricciola, Gino Giusi, and Claudio Fiegna. "Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies." IEEE Transactions on Electron Devices 58, no. 8 (August 2011): 2347–53. http://dx.doi.org/10.1109/ted.2011.2156414.

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9

Seifert, Norbert, Balkaran Gill, Jonathan A. Pellish, Paul W. Marshall, and Kenneth A. LaBel. "The Susceptibility of 45 and 32 nm Bulk CMOS Latches to Low-Energy Protons." IEEE Transactions on Nuclear Science 58, no. 6 (December 2011): 2711–18. http://dx.doi.org/10.1109/tns.2011.2171004.

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10

Roshan-Zamir, Ashkan, Osama Elhadidy, Hae-Woong Yang, and Samuel Palermo. "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS." IEEE Journal of Solid-State Circuits 52, no. 9 (September 2017): 2430–47. http://dx.doi.org/10.1109/jssc.2017.2705070.

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11

Hafez, Amr Amin, Ming-Shuan Chen, and Chih-Kong Ken Yang. "A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology." IEEE Journal of Solid-State Circuits 50, no. 3 (March 2015): 763–75. http://dx.doi.org/10.1109/jssc.2015.2394323.

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12

Shah, Jaspal Singh, David Nairn, and Manoj Sachdev. "A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS." IEEE Transactions on Nuclear Science 62, no. 3 (June 2015): 1367–74. http://dx.doi.org/10.1109/tns.2015.2429589.

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13

Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology." International Journal of Sensors, Wireless Communications and Control 9, no. 4 (September 17, 2019): 462–67. http://dx.doi.org/10.2174/2210327909666190206144601.

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Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs. Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product. Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.

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14

Uzunkol, Mehmet, and Gabriel M. Rebeiz. "A 65 GHz LNA/Phase Shifter With 4.3 dB NF Using 45 nm CMOS SOI." IEEE Microwave and Wireless Components Letters 22, no. 10 (October 2012): 530–32. http://dx.doi.org/10.1109/lmwc.2012.2218651.

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15

Zare, Mahdi, Hossein Manouchehrpour, and Ahmad Esmaeilkhah. "An efficient high speed, high frequency domino-logic based circuit." International Journal of Engineering & Technology 7, no. 2 (March 4, 2018): 252. http://dx.doi.org/10.14419/ijet.v7i2.8219.

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As the Very Large-Scale Integration (VLSI) techniques are mostly focused on high-speed and low power consumption circuits, various techniques and technologies were investigated to gain these two precious goals. Domino-logic is one of the circuits which is regarded to have high speed, high frequency and low power consumption. This work proposes a Domini logic circuit which has improved PDP compare to the previous one. The suggested circuit was simulated and the attained results show a considerable improvement in circuit’s speed in respect with its ancestor. The PDP of the circuit in 90 nm, biased at 1V, has been calculated as 53% approximately improvement. This improvement for PDP in 65 nm, 45 nm and 32 nm are 48%, 47% and 51% respectively.

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16

Tanaka, Tomoki, Keiji Kishine, Akira Tsuchiya, Hiromi Inaba, and Daichi Omoto. "A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS." IEIE Transactions on Smart Processing and Computing 5, no. 3 (June 30, 2016): 207–14. http://dx.doi.org/10.5573/ieiespc.2016.5.3.207.

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17

Quemerais, Thomas, Laurence Moquillon, Jean-Michel Fournier, and Philippe Benech. "65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies." IEEE Transactions on Microwave Theory and Techniques 58, no. 9 (September 2010): 2426–33. http://dx.doi.org/10.1109/tmtt.2010.2058277.

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18

Miyauchi, Ken, Kazuya Mori, Toshinori Otaka, Toshiyuki Isozaki, Naoto Yasuda, Alex Tsai, Yusuke Sawai, Hideki Owada, Isao Takayanagi, and Junichi Nakamura. "A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel." Sensors 20, no. 2 (January 15, 2020): 486. http://dx.doi.org/10.3390/s20020486.

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A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

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19

Lotfi, Sara, Olof Bengtsson, and Jörgen Olsson. "Power performance of 65 nm CMOS integrated LDMOS transistors at WLAN and X-band frequencies." International Journal of Microwave and Wireless Technologies 8, no. 2 (January 9, 2015): 135–41. http://dx.doi.org/10.1017/s1759078714001603.

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Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

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20

Hu, Zhi, Cheng Wang, and Ruonan Han. "A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking." IEEE Journal of Solid-State Circuits 54, no. 5 (May 2019): 1216–27. http://dx.doi.org/10.1109/jssc.2019.2893231.

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21

Hwang, Jeongho, Gyu-Seob Jeong, Woorham Bae, Jun-Eun Park, Chang Soo Yoon, Jung Min Yoon, Jiho Joo, Gyungock Kim, and Deog-Kyoon Jeong. "A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 4 (April 2018): 436–40. http://dx.doi.org/10.1109/tcsii.2017.2699328.

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22

Bol, David. "Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS." Journal of Low Power Electronics and Applications 1, no. 1 (January 25, 2011): 1–19. http://dx.doi.org/10.3390/jlpea1010001.

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23

Ronchini Ximenes, Augusto, Preethi Padmanabhan, Myung-Jae Lee, Yuichiro Yamashita, Dun-Nian Yaung, and Edoardo Charbon. "A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology." IEEE Journal of Solid-State Circuits 54, no. 11 (November 2019): 3203–14. http://dx.doi.org/10.1109/jssc.2019.2938412.

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24

Fu, Yupeng, Lianming Li, Yilong Liao, Xuan Wang, Yongjian Shi, and Dongming Wang. "A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 7 (July 2020): 1600–1609. http://dx.doi.org/10.1109/tvlsi.2020.2992123.

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25

Larionov, A. V., O. N. Buyakova, O. V. Sysoeva, S. E. Osina, S. O. Zadiabin, P. A. Aleksan, I. V. Tarasov, Yu B. Rogatkin, and V. V. Masterov. "A 4-Channel Multi-Standard Adaptive Serial Transceiver for the Range 1.25–10.3 Gb/s in CMOS 65 nm." Problems of advanced micro- and nanoelectronic systems development, no. 3 (2019): 26–32. http://dx.doi.org/10.31114/2078-7707-2019-3-26-32.

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26

Yin, Zhaoyang, Jiaju Ma, Saleh Masoodian, and Eric R. Fossum. "Threshold Uniformity Improvement in 1b Quanta Image Sensor Readout Circuit." Sensors 22, no. 7 (March 28, 2022): 2578. http://dx.doi.org/10.3390/s22072578.

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A new readout architecture for single-bit quanta image sensor (QIS) consisting of a capacitive transimpedance amplifier (CTIA) before a 1-bit quantizer to improve the threshold uniformity of the readout cluster is proposed in this paper. The 1-bit quantizer in the previous single-bit QIS had significant threshold non-uniformity likely caused by the fluctuation of the common-mode voltage of the jot output. To guarantee the stability of the common-mode voltage of input signals fed to the 1-bit quantizer, the CTIA is added before the 1-bit quantizer. A pipeline operation mode is also proposed so the CTIA and 1-bit ADC can work at the same time, thereby reducing the CTIA power consumption. A 2048 × 1024 high-speed test chip was implemented with 45 nm/65 nm stacked backside illuminated (BSI) CMOS image sensor (CIS) process and tested. According to the measured D-log-H results, a good threshold uniformity in the range of 0.3 to 0.8 e− for all readout clusters is demonstrated at 500 frame per second (fps) equivalent timing with 68 mW power consumption.

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27

Ciocoveanu, Radu, Robert Weigel, Amelie Hagelauer, and Vadim Issakov. "Design of a 60 GHz 32% PAE Class-AB PA with 2nd Harmonic Control in 45-nm PD-SOI CMOS." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 8 (August 2020): 2635–46. http://dx.doi.org/10.1109/tcsi.2020.2984042.

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28

Bajpai, Pratibha, Neeta Pandey, Kirti Gupta, Shrey Bagga, and Jeebananda Panda. "On Improving the Performance of Dynamic DCVSL Circuits." Journal of Electrical and Computer Engineering 2017 (2017): 1–11. http://dx.doi.org/10.1155/2017/8207104.

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This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.

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29

Park, Jun-Young, Minhyun Jin, Soo-Youn Kim, and Minkyu Song. "Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips." Electronics 11, no. 6 (March 10, 2022): 877. http://dx.doi.org/10.3390/electronics11060877.

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In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

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30

N Md, Bilal, Bhaskara Rao K, and Mohan Das S. "Energy Efficient GDI Based Full Adders For Computing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 6 (September 28, 2020): 5–9. http://dx.doi.org/10.46647/ijetms.2020.v04i06.002.

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This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

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31

Balachandran, Arya, Yong Chen, and Chirn Chye Boon. "A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 3 (March 2018): 599–603. http://dx.doi.org/10.1109/tvlsi.2017.2771429.

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32

Niesyto, Katarzyna, Aleksy Mazur, and Dorota Neugebauer. "Dual-Drug Delivery via the Self-Assembled Conjugates of Choline-Functionalized Graft Copolymers." Materials 15, no. 13 (June 24, 2022): 4457. http://dx.doi.org/10.3390/ma15134457.

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Graft copolymers based on a choline ionic liquid (IL), [2-(methacryloyloxy)ethyl]-trimethylammonium chloride (TMAMA), were obtained by atom transfer radical polymerization. The presence of chloride counterions in the trimethylammonium groups promoted anion exchange to introduce fusidate anions (FUS, 32–55 mol.%) as the pharmaceutical anions. Both the choline-based IL copolymers and their ionic drug-carrier conjugates (FUS systems as the first type, 26–208 nm) formed micellar structures (CMC = 0.011–0.025 mg/mL). The amphiphilic systems were advantageous for the encapsulation of rifampicin (RIF, 40–67 mol.%), a well-known antibiotic, resulting in single-drug (RIF systems as the second type, 40–95 nm) and dual-drug systems (FUS/RIF as the third type, 31–65 nm). The obtained systems released significant amounts of drugs (FUS > RIF), which could be adjusted by the content of ionic units and the length of the copolymer side chains. The dual-drug systems released 31–55% FUS (4.3–5.6 μg/mL) and 19–31% RIF (3.3–4.0 μg/mL), and these results were slightly lower than those for the single-drug systems, reaching 45–81% for FUS (3.8–8.2 μg/mL) and 20–37% for RIF (3.4–4.0 μg/mL). The designed polymer systems show potential as co-delivery systems for combined therapy against drug-resistant strains using two drugs in one formula instead of the separate delivery of two drugs.

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Howard, J., S. Dighe, S. R. Vangal, G. Ruhl, N. Borkar, S. Jain, V. Erraguntla, et al. "A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling." IEEE Journal of Solid-State Circuits 46, no. 1 (January 2011): 173–83. http://dx.doi.org/10.1109/jssc.2010.2079450.

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Al-Bayati, Essra E., and R. S. Fyath. "Design and Performance Investigation of a New Distributed Amplifier Architecture for 40 and 100 Gb/s Optical Receivers." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 14, no. 5 (February 3, 2015): 5661–86. http://dx.doi.org/10.24297/ijct.v14i5.5274.

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The design of distributed amplifiers (DAs) is one of the challenging aspects in emerging ultra high bit rate optical communication systems. This is especially important when implementation in submicron silicon complementary metal oxide semiconductor (CMOS) process is considered. This work presents a novel design scheme for DAs suitable for frontend amplification in 40 and 100 Gb/s optical receivers. The goal is to achieve high flat gain and low noise figure (NF) over the ultra wideband operating bandwidth (BW). The design scheme combines shifted second tire (SST) matrix configuration with cascode amplification cell configuration and uses m-derived technique. Performance investigation of the proposed DA architecture is carried out and the results are compared with that of other DA architectures reported in the literature. The investigation covers the gain and NF spectra when the DAs are implemented in 180, 130, 90, 65 and 45 CMOS standards.The simulation results reveal that the proposed DA architecture offers the highest gain with highest degree of flatness and low NF when compared with other DA configurations. Gain-BW products of 42772 and 21137 GHz are achieved when the amplifier is designed for 40 and 100 Gb/s operation, respectively, using 45 nm CMOS standard. Thesimulation is performed using AWR Microwave Office (version 10).

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35

Nasreen, Shaikh Zinnat Ara, Shafinaz Shahreen, and Shahnaz Rahman. "Is There any Difference of Climacteric Symptoms between Natural and Surgical Menopause?" Journal of SAFOMS 1, no. 2 (2013): 63–65. http://dx.doi.org/10.5005/jp-journals-10032-1014.

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ABSTRACT Objective To compare the effects of the natural and the surgical menopause (SM) on climacteric condition. Materials and methods This prospective study was conducted from Jan 2008 to Jan 2013 in ZHSWMCH. Initially, 4,000 women were enrolled but finally 1,743 of natural menopause (NM) and 554 of SM were analyzed. All women were aged between 45 and 50 years, and they were of menopause for 1 to 5 years. Ethical and patient's permission was taken. Once enrolled, they were asked questions. The questions were related to menopausal symptoms (MS). Data was collected and analyzed by SPSS software. Results Hot flushes, (535 vs 290, p < 0.001), sweating (344 vs 122, p < 0.001), poor memory (99 vs 65 p < 0.001), feeling depressed (335 vs 126, p < 0.001), dry skin/mucosa (229 vs 91, p < 0.001), decreased libido (289 vs 117, p < 0.001), dry vagina (99 vs 65, p < 0.001) and urinary complains (59 vs 42, p < 0.001) were found in SM vs NM. Hypertension or cardiovascular disease was more (191 vs 92, p < 0.01), blood sugar were more (90 vs 32, p ≤ 0.001) and metabolic syndrome are also more (48 vs 26, p < 0.07) in SM than NM but this did not reach the significance. Conclusion Menopausal symptoms are common in both NM and SM. These MS were significantly higher in surgically menopause women and they were troubled more, so we need to be cautious about oophorectomy, and ovarian preservation should be the aim in all benign cases. Of course, we need to assess the risks and benefit where there is risk of ovarian cancer during the time of total abdominal hysterectomy. Both hormone replacement therapy (HRT) (following a risk/benefit analysis) and treatment of osteoporosis may be recommended after surgery to decrease the climacteric symptoms and osteoporosis in women with menopausal symptoms. How to cite this article Nasreen SZA, Shahreen S, Rahman S. Is There any Difference of Climacteric Symptoms between Natural and Surgical Menopause? J South Asian Feder Menopause Soc 2013;1(2):63-65.

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Lai, Fu-Der, and Jian Long Huang. "Proposed single layer composite film used as high transmission phase shifting masks for the 32, 45, and 65 nm technology nodes." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, no. 6 (2007): 1799. http://dx.doi.org/10.1116/1.2790920.

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37

Song, Junyoung, Sewook Hwang, and Chulwoo Kim. "A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, no. 8 (August 2021): 1567–74. http://dx.doi.org/10.1109/tvlsi.2021.3086325.

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Hayatleh, K., S. Zourob, R. Nagulapalli, S. Barker, N. Yassine, P. Georgiou, and F. J. Lidgey. "A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950110. http://dx.doi.org/10.1142/s021812661950110x.

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This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.

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Mitrovic, Mladen, Michael Hofbauer, Bernhard Goll, Kerstin Schneider-Hornstein, Robert Swoboda, Bernhard Steindl, Kay-Obbe Voss, and Horst Zimmermann. "A DC-to-8.5 GHz 32 : 1 Analog Multiplexer for On-Chip Continuous-Time Probing of Single-Event Transients in a 65-nm CMOS." IEEE Transactions on Circuits and Systems II: Express Briefs 64, no. 4 (April 2017): 377–81. http://dx.doi.org/10.1109/tcsii.2016.2567781.

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TSUCHIYA, Akira, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, and Hidetoshi ONODERA. "Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS." IEICE Transactions on Electronics E103.C, no. 10 (October 1, 2020): 489–96. http://dx.doi.org/10.1587/transele.2019ctp0008.

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Park, Dongjun, Sungwook Choi, and Jongsun Kim. "A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links." Electronics 10, no. 2 (January 15, 2021): 177. http://dx.doi.org/10.3390/electronics10020177.

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An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

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Biagioni, Cristian, Jiří Sejkora, Silvia Musetti, Emil Makovicky, Renato Pagano, Marco Pasero, and Zdeněk Dolníček. "Stibiogoldfieldite, Cu₁₂(Sb₂Te₂)S₁₃, a new tetrahedrite-group mineral." Mineralogical Magazine 86, no. 1 (January 7, 2022): 168–75. http://dx.doi.org/10.1180/mgm.2021.107.

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ABSTRACTStibiogoldfieldite, Cu12(Sb2Te2)S13, was approved as a new mineral species from the Mohawk mine, Goldfield mining district, Esmeralda County, Nevada, USA. It occurs as metallic anhedral grains, dark grey in colour. It is associated with quartz, pyrite and an Ag–Bi–(S,Se) phase (holotype material) and with quartz, pyrite, calaverite, bismuthinite, bohdanowiczite, and the Ag–Bi–(S,Se) phase (cotype material). In reflected light, stibiogoldfieldite is isotropic, grey in colour, with indistinct brownish shade. Reflectance data in air [R (%)] are: 31.1 at 470 nm, 30.9 at 546 nm, 30.8 at 589 nm and 31.0 at 650 nm. Electron microprobe analysis for holotype material gave (in wt.% – average of 60 spot analyses): Cu 45.03(60), Ag 0.26(7), Fe 0.02(3), Zn 0.13(15), Sn 0.02(4), Pb 0.05(6), Sb 8.02(62), As 2.80(65), Bi 2.77(87), Te 15.15(1.24), S 24.50(32), Se 0.52(11), total 99.27(69). On the basis of (As + Sb + Te + Bi) = 4 atoms per formula unit (apfu), the empirical formula of stibiogoldfieldite is (Cu12.05Ag0.04Zn0.03Fe0.01)Σ12.13(Sb1.12As0.63Bi0.23Te2.02)Σ4.00(S12.99Se0.11)Σ13.10. Chemical data on an additional sample from the same locality (cotype material) gave the following results (in wt.% – average of 181 spot analyses): Cu 43.84(63), Ag 0.21(7), Sb 5.92(78), As 2.63(45), Te 20.07(1.19), S 25.13(53), Se 0.97(35), total 99.47(66). On the basis of (As + Sb + Te + Bi) = 4 apfu, the empirical formula of cotype material is (Cu11.30Ag0.03)Σ11.33(Sb0.80As0.57Bi0.06Te2.57)Σ4.00(S12.83Se0.20)Σ13.03. Stibiogoldfieldite is cubic, I$\overline 4$3m, with unit-cell parameters a = 10.3466(17) Å, V = 1107.6(5) Å3 and Z = 2 (holotype). Unit-cell parameters for the cotype sample are a = 10.3035(2) Å and V = 1093.83(7) Å3. The crystal structure of holotype stibiogoldfieldite was refined by single-crystal X-ray diffraction data to a final R1 = 0.032 on the basis of 285 reflections with Fo > 4σ(Fo) and 20 refined parameters. Stibiogoldfieldite is isotypic with other members of the tetrahedrite group.

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Wu, Bo, Shuang Zhu, Benwei Xu, and Yun Chiu. "A 24.7 mW 65 nm CMOS SAR-Assisted CT $\Delta\Sigma $ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR." IEEE Journal of Solid-State Circuits 51, no. 12 (December 2016): 2893–905. http://dx.doi.org/10.1109/jssc.2016.2594953.

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Salimi, Atefeh, Rasoul Dehghani, and Abdolreza Nabavi. "A Digital Linear-Switching Hybrid Power Amplifier for Envelope Tracking Hybrid Supply Modulators." Journal of Circuits, Systems and Computers 26, no. 10 (March 28, 2017): 1750162. http://dx.doi.org/10.1142/s0218126617501626.

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A novel envelope modulator for envelope tracking RF power amplifier (PA) is presented in this paper. The proposed modulator consists of a parallel combination of analog class AB and digitally controlled hybrid PAs. The analog and digital class AB PAs are effective in both reducing the clock frequency and also static power dissipation, thus improving the efficiency of the modulator. On the other hand, lower clock frequencies result in simpler and more power-efficient digital to analog converters required in the architecture. The modulator digital block is evaluated with a 45[Formula: see text]nm CMOS technology. The overall power consumption of the digital block is around 76[Formula: see text]mW at 800[Formula: see text]MHz clock frequency. As an application, the designed digital block is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital block power consumption, is around 80.7% at an average 32[Formula: see text]dBm output power for a 5[Formula: see text]MHz input signal.

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Tannheimer, Stacey, Jia Liu, Rick Sorensen, Anella Yahiaoui, Sarah Meadows, Li Li, Peng Yue, et al. "Combination of Idelalisib and ONO/GS-4059 in Lymphoma Cell Lines Sensitive and Resistant to BTK Inhibitors." Blood 126, no. 23 (December 3, 2015): 3697. http://dx.doi.org/10.1182/blood.v126.23.3697.3697.

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Abstract Idelalisib (Zydelig™), a first-in-class, selective, oral inhibitor of PI3Kδ, is approved for the treatment of chronic lymphocytic leukemia (CLL) in combination with rituximab and as monotherapy for patients with follicular lymphoma who have received at least 2 prior therapies. Despite remarkable clinical efficacy, complete responses are rare, highlighting the need to identify more effective therapies, including combinations of novel agents. GS-4059 (ONO-4059) is an investigational next generation BTK inhibitor with improved selectivity compared to ibrutinib. We report here on the results of the combination of idelalisib and GS-4059 in lymphoma cell lines. Methods: Growth inhibition was assessed using CellTiter-Glo™ Assay (Promega) after 72-96 h incubation with idelalisib and GS-4059. Synergy for anti-proliferative effects was assessed using the Bliss Model of Independence (Meletiadis et al., Med Mycol, 2005), using MacSynergy II (Prichard et al., MacSynergyTM II, Version 1.0, 1993) or the Chalice software (Horizon Discovery, Inc., Lehar et al., Nature Biotech, 2009). Lysates were analyzed by Simple Western (Protein Simple) or Western blot. Ibrutinib resistance was established by continuous passaging of a clonal isolate of TMD8 in the presence of 10-20 nM ibrutinib. Resistance mutations were identified by whole exon sequencing (WES, GeneWiz). Results: GS-4059 potently inhibited growth (EC50<26 nM) of 3 ABC-DLBCL cell lines (OCI-LY10, Ri-1, and TMD8) that were also sensitive to idelalisib (EC50<210 nM). The combination showed synergistic growth inhibition in OCI-LY10 and TMD8 and increased apoptosis above the level observed with single agents (Table 1). Idelalisib and GS-4059 synergistically inhibited growth in 2 MCL cell lines (Rec-1 and JMV-2). The combination was additive in the other lymphoma cell lines sensitive to these agents. Two mechanisms of resistance to BTK inhibitors were identified in TMD8: an inactivating mutation in the NF-kB inhibitor A20 (TNFAIP3 Q143*), and a BTK mutation (C481F). TMD8 cells with the BTK (C481F) mutation only were less sensitive to idelalisib (Emax = 14% at 1 uM vs. 86% in parental, Figure 1A). Addition of GS-4059 did not enhance growth inhibition in those clones. A20 mutant only TMD8 cells were resistant to GS-4059 (EC50>10 μM), but were sensitive to idelalisib, albeit less than parental (EC50 ≥ 4300 nM vs. 54 nM). Addition of 50 nM GS-4059 to idelalisib provided further growth inhibition, consistent with the presence of wild-type BTK, and increased the potency of idelalisib to a level comparable to parental TMD8 (EC50 ≥ 99 nM, n=5 clones, Figure 1B). Conclusion: Idelalisib and GS-4059 synergistically inhibited the growth of a subset of DLBCL and MCL cell lines. A20 mutation and loss-of -function was identified as a novel mechanism of resistance to BTK inhibitors. Idelalisib less potently inhibited the growth of A20 mutant TMD8 but the combination with GS-4059 provided additional benefit. TMD8 with a BTK-C481F mutation, were resistant to idelalisib and to the combination with GS-4059. These data suggest that the combination of idelalisib and GS-4059 may overcome some mechanisms of resistance to BTK. Table 1. Synergistic inhibition of ABC-DLBCL cell viability by GS-4059 and idelalisib GS-4059 (nM) EC50 of idelalisib (nM) when combined with GS-4059 TMD-8 OCI-LY-10 Ri-1 Pfeiffer 0 254 440 442 174 5 130 38 372 NTc 15 32 22 372 NT 45 24 5 372 174 EC50 shift (fold) 10.6 88 12 1 Synergy Score 65 65 0 0 Figure 1. Growth inhibition of ibrutinib resistant TMD8 with (A) BTK C481F mutation or (B) A20 Q143* mutation A. B. Figure 1. Growth inhibition of ibrutinib resistant TMD8 with (A) BTK C481F mutation or (B) A20 Q143* mutation. / A. / B. Figure 2. Figure 2. Disclosures Tannheimer: Gilead Sciences: Employment, Other: Share holder. Sorensen:Gilead Sciences: Employment, Other: Share holder. Yahiaoui:Gilead Sciences: Employment, Other: Share holder. Meadows:Gilead Sciences: Employment, Other: Share holder. Li:Gilead Sciences: Employment, Other: Share holder. Yue:Gilead Sciences: Employment, Other: Share holder. Tumas:Gilead Sciences: Employment, Equity Ownership. Queva:Gilead Sciences: Other: Share holder.

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Dyachkov, I. A., I. Ya Motus, A. V. Bazhenov, S. N. Skornyakov, and R. B. Berdnikov. "Precision resection of pulmonary tuberculoma using Nd:YAG-laser." Tuberculosis and Lung Diseases 99, no. 12 (January 12, 2022): 27–32. http://dx.doi.org/10.21292/2075-1230-2021-99-12-27-32.

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The objective of the study: a comparative study of immediate and long-term results of pulmonary tuberculoma precision resection with Nd:YAG-laser with a wavelength of 1,318 nm and atypical resection with suturing devices.Subjects and Methods. Two groups of 58 patients each were compared. The groups were comparable in terms of gender, age, the nature of the concomitant pathology and the main pathological process. In Group I, patients were operated on using precision 1,318-nm Nd:YAG-laser resection, and in Group II, the sublobar resection with suturing devices were used.Results. The mean duration of hospital stay in Groups I and II was 19.10 ± 6.02 and 19.20 ± 6.02 days respectively (p > 0.05), the duration of surgery made 65 [55; 75] and 55 [45; 60] minutes (p > 0.05), the mean volume of surgical blood loss was 50 [33; 70] and 70 [50; 165] ml (p > 0.05), and the mean duration of pleural cavity drainage after surgery was 4 [3; 5] and 4 [3; 6] days (p > 0.05). Statistically significant differences were noted in the mean volume of the resected part of the lung: 14.0 ± 7.4 mm3 in Group I versus 95.0 ± 9.7 mm3 in Group II (p ≤ 0.05). The complete clinical and radiological cure was achieved in 70% of patients in Group I and 82% in Group II. According to MSCT data, in 91.6% of cases, a thin linear scar is formed in the area of precision intervention.Conclusion: The surgical methods are comparable in terms of immediate and long-term results but precision laser resection minimizes the removal of intact tissue during the removal of tuberculomas.

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Lu, Yue, Shengyu Duan, Basel Halak, and Tom Kazmierski. "A Variation-Aware Design Methodology for Distributed Arithmetic." Electronics 8, no. 1 (January 18, 2019): 108. http://dx.doi.org/10.3390/electronics8010108.

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Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, new error resilient techniques for DA computation are urgently required to improve robustness against the process, voltage, and temperature (PVT) variations. This paper proposes a new in-situ timing error prevention technique to mitigate the impact of variations in DA circuits by providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the sign extension block and carefully gate-sizing. Therefore, least significant bit (LSB) computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Our approach is demonstrated on a 16-tap finite impulse respons (FIR) filter using the 65 nm CMOS process and the simulation results show that this design can still maintain high-accuracy performance without worst case timing margin, and achieve up to 32 % power savings by voltage scaling when the worst case margin is considered with only 9 % area overhead.

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Lai, Fu-Der, Jui-Ming Hua, C. Y. Huang, Fu-Hsiang Ko, L. A. Wang, C. H. Lin, C. M. Chang, S. Lee, and Gia-Wei Chern. "ArF-line high transmittance attenuated phase shift mask blanks using amorphous Al2O3–ZrO2–SiO2 composite thin films for the 65-, 45- and 32-nm technology nodes." Thin Solid Films 496, no. 2 (February 2006): 247–52. http://dx.doi.org/10.1016/j.tsf.2005.08.382.

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Thakkar, Chintan, Nathan Narevsky, Christopher D. Hull, and Elad Alon. "Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver." IEEE Journal of Solid-State Circuits 49, no. 11 (November 2014): 2588–607. http://dx.doi.org/10.1109/jssc.2014.2360917.

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Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (August 10, 2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

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