Relevant bibliographies by topics / CMOS

Academic literature on the topic 'CMOS'

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Published: 4 June 2021
Last updated: 25 May 2024

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Journal articles on the topic "CMOS"

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Deleonibus, S. "Alternative CMOS or alternative to CMOS?" Microelectronics Reliability 41, no. 1 (January 2001): 3–12. http://dx.doi.org/10.1016/s0026-2714(00)00196-7.

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Kawahito, Shoji. "CMOS Image Sensors." IEEJ Transactions on Sensors and Micromachines 134, no. 7 (2014): 199–205. http://dx.doi.org/10.1541/ieejsmas.134.199.

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Lau, K. T., W. Y. Wang, and K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit." International Journal of Electronics 87, no. 1 (January 2000): 27–32. http://dx.doi.org/10.1080/002072100132417.

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Banerjee, Sanjay K., Leonard Franklin Register, Emanuel Tutuc, Dipanjan Basu, Seyoung Kim, Dharmendar Reddy, and Allan H. MacDonald. "Graphene for CMOS and Beyond CMOS Applications." Proceedings of the IEEE 98, no. 12 (December 2010): 2032–46. http://dx.doi.org/10.1109/jproc.2010.2064151.

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GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (June 1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.
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Ko, Ji Wang, and Woo Young Choi. "Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4176–81. http://dx.doi.org/10.1166/jnn.2020.17790.

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Monolithic-three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) hybrid reconfigurable logic (RL) circuits are compared and analyzed with CMOS-only RL ones in the 130-nm CMOS technology node. M3D CMOS-NEM hybrid RL circuits are superior to CMOS-only ones in terms of power consumption and signal transfer speed thanks to the NEM memory switches. As well as in the routing part, it has many advantages in the logic part following the switch.
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Agrawal, Gaurav R., and Leena A. Yelmule. "Linear CMOS LNA." International Journal of Trend in Scientific Research and Development Volume-3, Issue-1 (December 31, 2018): 829–35. http://dx.doi.org/10.31142/ijtsrd19087.

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Wong, H. S. P., D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser. "Nanoscale CMOS." Proceedings of the IEEE 87, no. 4 (April 1999): 537–70. http://dx.doi.org/10.1109/5.752515.

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Malhi, S. D. S., K. E. Bean, R. Sunderesan, and L. R. Hite. "Overlaid CMOS." Electronics Letters 22, no. 11 (May 22, 1986): 598–99. http://dx.doi.org/10.1049/el:19860406.

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Brown, G. A., P. M. Zeitzoff, G. Bersuker, and H. R. Huff. "Scaling CMOS." Materials Today 7, no. 1 (January 2004): 20–25. http://dx.doi.org/10.1016/s1369-7021(04)00051-3.

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Dissertations / Theses on the topic "CMOS"

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Covington, James A. "CMOS and SOI CMOS FET-based gas sensors." Thesis, University of Warwick, 2001. http://wrap.warwick.ac.uk/3589/.

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In recent years, there has been considerable interest in the use of gas/vapour monitors and electronic nose instruments by the environmental, automotive and medical industries. These applications require low cost and low power sensors with high yield and high reproducibility, with an annual prospective market of 1 million pounds. Present device and sensor technologies suffer a major limitation, their incompatibility with a standard silicon CMOS process. These technologies have either operating/annealing temperatures unsuited for MOSFET operation or an inappropriate sensing mechanism. The aim of this research is the development of CMOS compatible gas/vapour sensors, with a low cost of fabrication, high device repeatability and, in the future, transducer sensor amalgamation. Two novel approaches have been applied, utilising bulk CMOS and SOI BiCMOS. The bulk CMOS designs use a MOSFET sensing structure, with an active polymeric gate material, operating at low temperatures (<100°C), based on an array device of four elements, with channel lengths of 10 μm or 5 μm. The SOI designs exploit a MOSFET heater with a chemoresistive or chemFET sensing structure, on a thin membrane formed by the epi-taxial layer. By applying SOI technology, the first use in gas sensor applications, operating temperatures of up to 300 °C can be achieved at a power cost of only 35 mW (simulated). Full characterisation of the bulk CMOS chemFET sensors has been performed using electrochemically deposited (e.g. poly(pyrrole)/BSA)) and composite polymers (e.g. poly(9-vinylcarbazole)) to ethanol and toluene vapour in air. In addition, environmental factors (humidity and temperature) on the response and baseline were investigated. This was carried out using a newly developed flow injection analysis test station, which conditions the test vapour to precise analyte (<15 PPM of toluene) and water concentrations at a fixed temperature (RT to 105°C +- 0.1), with the sensor characterised by either I-V or constant current instrumentation. N-channel chemFET sensors operated at constant current (10 μA) with electrochemically deposited and composite polymers showed sensitivities of up to 1.1 μV/PPM and 4.0 μV/PPM to toluene vapour and to 1.1 μV/PPM and 0.4 μV/PPM for ethanol vapour, respectively, with detection limits of <20 PPM and <100 PPM to toluene and <20 PPM and 10+ PPM to ethanol vapour (limited by baseline noise), respectively. These responses followed either a power law (composite polymers) or a modified Langmuir isotherm model (electrochemically deposited polymers) with analyte concentration. It is proposed that this reaction-rate limited response is due to an alteration in polymers work function by either a partial charge transfer from the analyte or a swelling effect (polymer expansion). Increasing humidity caused, in nearly all cases a reduction in relative baseline, possible by dipole formation at the gate oxide surface. For the response, increasing humidity had no effect on sensors with composite polymers and an increase for sensors with electrochemically-deposited polymers. Higher temperatures caused a reduction in baseline signal, by a thermal expansion of the polymer, and a reduction in response explained by the analyte boiling point model describing a reduction in the bulk solubility of the polymer. Electrical and thermal characterisation of the SOI heaters, fabricated by the MATRA process, has been performed. I-V measurements show a reduction in drain current for a MOSFET after back-etching, by a degradation of the carrier mobility. Dynamic measurement showed a two stage thermal response (dual exponential), as the membrane reaching equilibrium (100-200 ms) followed by the bulk (1-2 s). A temperature coefficient of 8 mW/°C was measured, this was significantly higher than expected from simulations, explained by the membrane being only partially formed. Diode and resistive temperature sensors showed detection limits under 0.1°C and shown to measure a modulated heater output of less than 1°C at frequencies higher than 10Hz. The principal research objectives have been achieved, although further work on the SOI device is required. The results and theories presented in this study should provide a useful contribution to this research area.
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Meng, Huaiyu. "CMOS nanofluidics." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/120374.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 217-226).
Diagnostic tests are essential to medical practice. In vitro diagnostics is a market worth US$ 40-45 billion. Diagnostic tests are usually conducted in centralized laboratories, equipped with expensive instrumentation and staffed with trained personnel. An important part of clinical diagnosis involves protein and DNA sensing. Significant effort is made to make protein and DNA sensing more accessible and affordable, through micro and nano-technologies. However, typical commercial and academic devices for molecular sensing suffered needs for external equipment, high cost and large form factors. In this work, we propose a self-contained point-of-care platform based on complementary metal oxide semiconductor (CMOS). CMOS platform has the capability of pattern features at the scale of nanometers. Important electronic functions in bio-sensing, such as amplifiers, counters and drivers are routinely implemented in CMOS. With the introduction of photonic and nanofluidic functionalities in this thesis, a CMOS chip can potentially perform biomolecular sensing without the aid of external equipment, hence becoming true lab-on-chip devices. This thesis presents the methods developed to introduce nanofluidic and photonic devices in commercial CMOS chips. We first introduce a method to fabricate nanofluidic channels in CMOS by using the transistor gate polysilicon as a sacrificial layer. A nanochannel with critical dimension of 100nm and length of 200 [mu]m is fabricated. Actuation and separation of bio-molecules in the nanochannel with electrophoresis is demonstrated. We then incorporate avalanche photodiodes (APD) in CMOS. Additionally, a packaging method is introduced to work with CMOS chips with size of a few square millimeters. With components mentioned above, clinical applications, such as gene mapping for virus identification and protein separation for cancer diagnosis and monitoring, could potentially run on a chip without external equipment.
by Huaiyu Meng.
Ph. D.
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Kerber, Andreas. "Methodology for electrical characterization of MOS devices with alternative gate dielectrics." Phd thesis, [S.l. : s.n.], 2004. http://elib.tu-darmstadt.de/diss/000404.

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Carletti, Luca. "Photonique intégrée nonlinéaire sur plate-formes CMOS compatibles pour applications du proche au moyen infrarouge." Thesis, Ecully, Ecole centrale de Lyon, 2015. http://www.theses.fr/2015ECDL0013/document.

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La photonique intégrée offre la possibilité d’exploiter un vaste bouquet de phénomènes optique nonlinéaires pour la génération et le traitement de signaux optiques sur des puces très compactes et à des débits potentiels extrêmement rapides. De nouvelles solutions et technologies de composants pourraient être ainsi réalisées, avec un impact considérable pour les applications télécom et datacom. L’utilisation de phénomènes optiques nonlinéaires (e.g. effet Kerr optique, effet Raman) permet même d’envisager la réalisation de composants actifs (e.g. amplificateurs, modulateurs, lasers, régénérateurs de signaux et convertisseurs en longueur d’onde).Pendant cette dernière décennie, les efforts ont principalement porté sur la plateforme Silicium sur isolant (SOI), profitant du fort confinement optique dans ce matériau, qui permet la miniaturisation et intégration de composants optiques clés (e.g. filtres passifs, jonctions coupleurs et multiplexeurs). Cependant, la présence de fortes pertes nonlinéaires dans ce matériau aux longueurs d’onde d’intérêt (i.e. autour de 1.55 µm dans les télécommunications) limite certaines applications pour lesquelles une forte réponse nonlinéaire est nécessaire et motive la recherche de nouvelles plates-formes, mieux adaptées. L’objectif premier de cette thèse était ainsi l’étude de matériaux alternatifs au Si cristallin, par exemple le silicium amorphe hydrogéné, alliant de très faibles pertes nonlinéaires et une compatibilité CMOS, pour la réalisation de dispositifs photoniques intégrés qui exploitent les phénomènes nonlinéaires. Alternativement, l’utilisation de longueurs d’onde plus élevées (dans le moyen-IR) permet de relaxer la contrainte sur le choix de la filière matériau, en bénéficiant de pertes nonlinéaires réduites, par exemple dans la filière SiGe, également explorée dans cette thèse. Ce travail est organisé de la façon suivante. Le premier chapitre donne un iii panorama des phénomènes nonlinéaires qui permettent de réaliser du traitement tout-optique de l’information, en mettant en évidence les paramètres clés à maitriser (confinement optique, ingénierie de dispersion) pour les composants d’optique intégrée, et en présentant le cadre de modélisation de ces phénomènes utilisé dans le travail de thèse. Il inclut également une revue des démonstrations marquantes publiées sur Silicium cristallin, donnant ainsi des points de référence pour la suite du travail. Le chapitre 2 introduit les cristaux photoniques comme structures d’optique intégrée permettant d’exalter les phénomènes nonlinéaires. On s’intéresse ici aux cavités, avec une démonstration de génération de deuxième et troisième harmoniques qui exploite un design original. Ce chapitre décrit également les enjeux associés à l’utilisation de guides à cristaux photoniques en régime de lumière lente, qui serviront de fondements pour le chapitre 4. Le chapitre 3 présente les résultats de caractérisation de la réponse nonlinéaire associée à des guides réalisés dans deux matériaux alternatifs au silicium cristallin : le silicium amorphe hydrogéné testé dans le proche infrarouge et le silicium germanium testé dans le moyen infrarouge. Le modèle présenté au chapitre 1 est exploité pour déduire la réponse de ces deux matériaux, et il est même étendu pour rendre compte d’effets nonlinéaires d’ordre plus élevé dans le cas du silicium germanium à haute longueur d’onde. Ce chapitre inclut également une discussion sur la comparaison des propriétés nonlinéaires de ces deux matériaux avec le SOI standard. Le chapitre 4 combine l’utilisation d’une plate-forme plus prometteuse que le SOI, avec des structures photoniques plus avancées que les simples guides réfractifs utilisés au chapitre 3 : il décrit l’ingénierie de modes (lents) dans des guides à cristaux photoniques en silicium amorphe hydrogéné et enterrés dans la silice. [...]
Integrated photonics offers a vast choice of nonlinear optical phenomena that could potentially be used for realizing chip-based and cost-effective all-optical signal processing devices that can handle, in principle, optical data signals at very high bit rates. The new components and technological solutions arising from this approach could have a considerable impact for telecom and datacom applications. Nonlinear optical effects (such as the optical Kerr effect or the Raman effect) can be potentially used for realizing active devices (e.g. optical amplifiers, modulators, lasers, signal regenerators and wavelength converters). During the last decade, the silicon on insulator (SOI) platform has known a significant development by exploiting the strong optical confinement, offered by this material platform, which is key for the miniaturization and realization of integrated optical devices (such as passive filters, splitters, junctions and multiplexers). However, the presence of strong nonlinear losses in the standard telecom band (around 1.55 µm) prevents some applications where a strong nonlinear optical response is needed and has motivated the research of more suitable material platforms. The primary goal of this thesis was the study of material alternatives to crystalline silicon (for instance hydrogenated amorphous silicon) with very low nonlinear losses and compatible with the CMOS process in order to realize integrated photonics devices based on nonlinear optical phenomena. Alternatively, the use of longer wavelengths (in the mid-IR) relaxes the constraints on the choice of the material platform, through taking advantage of lower nonlinear losses, for instance on the SiGe platform, which is also explored in this thesis. This work is organized as follows. In the first chapter we provide an overview of the nonlinear optical effects used to realize all optical signal processing functions, focusing on the key parameters that are essential (optical confinement and dispersion engineering) for integrated optical components, and presenting the main models used in this thesis. This chapter also includes a review of the main demonstrations reported on crystalline silicon, to give some benchmarks. Chapter 2 introduces the use of photonic crystals as integrated optical structures that can significantly enhance nonlinear optical phenomena. First we present photonic crystal cavities, with a demonstration of second and third harmonic generation that makes use of an original design. In the second part of the chapter, we describe the main features and challenges associated with photonic crystal waveguides in the slow light regime, which will be used later in chapter 4. In chapter 3, we report the experimental results related to the characterization of the optical nonlinear response of integrated waveguides made of two materials that are alternative to crystalline silicon : the hydrogenated amorphous silicon, probed in the near infrared, and the silicon germanium, probed in the mid-infrared. The model presented in chapter 1 is extensively used here for extracting the nonlinear parameters of these materials and it is also extended to account for higher order nonlinearities in the case of silicon germanium tested at longer wavelengths. This chapter also includes a comparison of the nonlinear properties of these two material platforms with respect to the standard SOI. In chapter 4, we combine the use of a material platform that is better suited than SOI for nonlinear applications with integrated photonics structures that are more advanced that those used in chapter 3. Here we describe the design of (slow) modes in photonic crystal waveguides made in hydrogenated amorphous silicon fully embedded in silica. [...]
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Chen, Tingsu. "Spin Torque Oscillator Modeling, CMOS Design and STO-CMOS Integration." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-176890.

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Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration. An electrical model, which can capture magnetic tunnel junction (MTJ) STO's characteristics, while enabling system- and circuit-level designs and performance evaluations, is of great importance for the development of MTJ STO-based applications. A comprehensive and compact analytical model, which is based on macrospin approximations and can fulfill the aforementioned requirements, is proposed. This model is fully implemented in Verilog-A, and can be used for efficient simulations of various MTJ STOs. Moreover, an accurate phase noise generation approach, which ensures a reliable model, is proposed and successfully used in the Verilog-A model implementation. The model is experimentally validated by three different MTJ STOs under different bias conditions. CMOS circuits, which can enhance the limited output power of MTJ STOs to levels that are required in different applications, are proposed, implemented and tested. A novel balun-low noise amplifier (LNA), which can offer sufficient gain, bandwidth and linearity for MTJ STO-based magnetic field sensing applications, is proposed. Additionally, a wideband amplifier, which can be connected to an MTJ STO to form a highly-tunable microwave oscillator in a phase-locked loop (PLL), is also proposed. The measurement results demonstrate that the proposed circuits can be used to develop MTJ STO-based magnetic field sensing and microwave source applications. The investigation of possible STO-CMOS IC integration approaches demonstrates that the wire-bonding-based integration is the most suitable approach. Therefore, a giant magnetoresistance (GMR) STO is integrated with its dedicated CMOS IC, which provides the necessary functions, using the wire-bonding-based approach. The RF characterization of the integrated GMR STO-CMOS IC system under different magnetic fields and DC currents shows that such an integration can eliminate wave reflections. These findings open the possibility of using GMR STOs in magnetic field sensing and microwave source applications.

QC 20151112

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Boltshauser, Thomas. "CMOS humidity sensors /." [S.l.] : [s.n.], 1993. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10320.

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Maul, Thomas. "CMOS-integrierte Feldemissionsspitzen /." Göttingen : Cuvillier, 2009. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=018923495&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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Zhou, Tiansheng. "CMOS cantilever microresonator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0010/MQ60201.pdf.

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Scholvin, Jörg 1976. "RF power CMOS." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86742.

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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 103-105).
by Jörg Scholvin.
M.Eng.and S.B.
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Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.

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Books on the topic "CMOS"

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Baker, R. Jacob. CMOS. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2010. http://dx.doi.org/10.1002/9780470891179.

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Gakkai, Eizō Jōhō Media, ed. CMOS imēji sensa: CMOS image sensor. Tōkyō: Koronasha, 2012.

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Lee, Hakho, Robert M. Westervelt, and Donhee Ham, eds. CMOS Biotechnology. Boston, MA: Springer US, 2007. http://dx.doi.org/10.1007/978-0-387-68913-5.

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Segura, Jaume, and Charles F. Hawkins. CMOS Electronics. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2004. http://dx.doi.org/10.1002/0471728527.

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Segura, Jaume, and Charles F. Hawkins. CMOS Electronics. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2004. http://dx.doi.org/10.1002/0471728527.

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Iniewski, Krzysztof, ed. CMOS Biomicrosystems. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118016497.

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Balestra, Francis, ed. Nanoscale CMOS. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.

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Yadid-Pecht, Orly, and Ralph Etienne-Cummings, eds. CMOS Imagers. Boston: Kluwer Academic Publishers, 2004. http://dx.doi.org/10.1007/b117398.

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Brand, Oliver, and Gary K. Fedder. CMOS-MEMS. Weinheim: Wiley-VCH, 2005.

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M, Berlin Howard, ed. CMOS cookbook. 2nd ed. Boston: Newnes, 1997.

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Book chapters on the topic "CMOS"

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Abbas, Karim. "CMOS." In Handbook of Digital CMOS Technology, Circuits, and Systems, 111–43. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_3.

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Domínguez-Castro, Rafael, Manuel Delgado-Restituto, Angel Rodríguez-Vázquez, José M. de la Rosa, and Fernando Medeiro. "CMOS Comparators." In CMOS Telecom Data Converters, 149–82. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_4.

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Giebel, Thomas. "CMOS-Technologie." In Grundlagen der CMOS-Technologie, 95–150. Wiesbaden: Vieweg+Teubner Verlag, 2002. http://dx.doi.org/10.1007/978-3-663-07914-9_5.

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Abbas, Karim. "CMOS Process." In Handbook of Digital CMOS Technology, Circuits, and Systems, 217–73. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_7.

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Ma, Yanjun, and Edwin Kan. "CMOS Biosensors." In Non-logic Devices in Logic Processes, 237–61. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-48339-9_12.

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"CMOS." In The VLSI Handbook, 810–20. CRC Press, 1999. http://dx.doi.org/10.1201/9781420049671-39.

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Muroga, Saburo. "CMOS." In Electrical Engineering Handbook. CRC Press, 1999. http://dx.doi.org/10.1201/9781420049671.ch36.

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Rousseau, Paul. "CMOS." In Circuits at the Nanoscale, 2–9. CRC Press, 2008. http://dx.doi.org/10.1201/9781420070637.pt1.

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Muroga, Saburo. "Cmos." In The VLSI Handbook, Second Edition, 39–1. CRC Press, 2006. http://dx.doi.org/10.1201/9781420005967.ch39.

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"CMOS." In Logic Design, 169–78. CRC Press, 2003. http://dx.doi.org/10.1201/9780203010150-18.

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Conference papers on the topic "CMOS"

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Skotnicki, Thomas. "Quo vadis nano-CMOS ?" In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570995.

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"2006 international workshop on Nano CMOS proceedings." In 2006 International Workshop on Nano CMOS. IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570969.

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Wong, H. S. Philip. "Research opportunities for nanoscale CMOS." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570976.

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"Preface." In 2006 International Workshop on Nano CMOS. IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570970.

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Yoshio Nishi. "CMOS scaling and non-silicon opportunities." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570972.

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Tohru Mogami and Hitoshi Wakabayashi. "Challenges for sub-10 nm CMOS devices." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570982.

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Hiroshi Iwai. "Recent status on Nano CMOS and future direction." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570971.

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Ji Chen and Juin J. Liou. "CMOS technology-based spiral inductors for RF applications." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570986.

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Abbas, Haider Muhi, Mark Zwolinski, and Basel Halak. "An application-specific NBTI ageing analysis method." In 2015 International Workshop on CMOS Variability (VARI). IEEE, 2015. http://dx.doi.org/10.1109/vari.2015.7456553.

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Chua, Adelson N., Rico Jossel M. Maestro, Mark Earvin V. Alba, Wes Vernon V. Lofamia, Bernard Raymond D. Pelayo, Ken Bryan F. Fabay, John Cris F. Jardin, et al. "Delay variation compensation through error correction using razor." In 2015 International Workshop on CMOS Variability (VARI). IEEE, 2015. http://dx.doi.org/10.1109/vari.2015.7456554.

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Reports on the topic "CMOS"

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Rau, Jerry. PR-542-163745-R01 Defining Close Metal Object Detection Capabilities of MFL ILI Tools. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), September 2017. http://dx.doi.org/10.55274/r0011422.

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Abstract:
There is a need to understand Magnetic Flux Leakage (MFL) in-line inspection data and determine if it distinguishes whether a Close Metal Object (CMO) is an adjacent pipeline or independent metallic article. There have been failures associated with CMOs both in contact and in close proximity with the pipeline, specifically water lines. With the knowledge gained on the sensitivity of MFL technology to detect such objects, a process could be developed to identify those CMOs which may be a hazard to the pipeline and prioritize them for evaluation. This report has a related webinar. ?
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Voss, L. DARPA beyond CMOS RFI. Office of Scientific and Technical Information (OSTI), January 2021. http://dx.doi.org/10.2172/1788329.

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Trotter, J. D., and G. S. Prasad. Bulk CMOS VLSI Technology Studies. Part 4. Design of a CMOS Microsequencer. Fort Belvoir, VA: Defense Technical Information Center, June 1985. http://dx.doi.org/10.21236/ada158369.

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Trotter, J. D., and A. K. R. Naini. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design. Fort Belvoir, VA: Defense Technical Information Center, June 1985. http://dx.doi.org/10.21236/ada158367.

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McCarthy, A., and T. W. Sigmon. Radiation Hardening of CMOS Microelectronics. Office of Scientific and Technical Information (OSTI), February 2000. http://dx.doi.org/10.2172/792429.

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Nuckolls, L. CMOS ASIC (application specific integrated circuit). Office of Scientific and Technical Information (OSTI), July 1989. http://dx.doi.org/10.2172/5551185.

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Brocco, Lynne M. Macromodeling CMOS Circuits for Timing Simulation. Fort Belvoir, VA: Defense Technical Information Center, June 1987. http://dx.doi.org/10.21236/ada459654.

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Lala, P. K., and A. Walker. Self-Checking State Machine Realization in CMOS. Fort Belvoir, VA: Defense Technical Information Center, December 1994. http://dx.doi.org/10.21236/ada289149.

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Likharev, Konstantin K., and James Lukens. Fundamental Problems of Hybrid CMOS/Nanodevice Circuits. Fort Belvoir, VA: Defense Technical Information Center, December 2010. http://dx.doi.org/10.21236/ada564340.

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Likharev, Konstantin K., and James Lukens. Fundamental Problems of Hybrid CMOS/Nanodevice Circuits. Fort Belvoir, VA: Defense Technical Information Center, December 2010. http://dx.doi.org/10.21236/ada565890.

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