Dissertations / Theses on the topic 'Clock'

For this project I was planning to construct a clock that could be synchronized with an external source. The clock should be able to keep the time between synchronizations as these may be sparse. It also needed to be able to store the current time in a memory and keep a register of stored times. The current time and the register must be viewable by the user and the clock must also have the ability to count down the last five seconds prior to a minute selected by the user. I have performed this work at home with my own equipments.

As an external source for the synchronization I have chosen the DCF-77 clock signal broadcasted from Germany. To receive this signal I used a cheap AM receiver built specifically for this purpose. For the actual clock I used a PIC microcontroller which I programmed in C. The chip had all I needed including an oscillator and a RAM memory. I also connected a 3x16 character LCD display to the clock as well as 4 1-pole buttons for the user interface.

The program is built upon an interrupt routine that with help of an internal timer is set to execute once every hundreds of a second. During this interrupt routine all other functions are executed. These functions include a DCF decoder, an internal clock to keep the time, an LCD driver and a user interface.

I have managed to read the clock signal from the receiver but due to interferences from the computer I used to program the PIC chip, I have not been able to get any good reception close to the computer. Apart from this setback the clock works as it should and it meets all other criteria.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados.
Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Les deux premiers chapitres de la thèse présentent le principe d’un étalon de fréquence optique et les applications qui en découlent. Les principaux avantages métrologiques de l’horloge à réseau optique de mercure sont mis en avant, et quelques rappels théoriques d’interraction matière-rayonnement appliquée à la métrologie des fréquences sont effectués. Le montage expérimental est décrit de manière générale dans le chapitre 3, en insistant particulièrement sur les différentes sources laser utilisées. Les améliorations apportées au montage durant la thèse, font l’objet du chapitre 4. La première amélioration concerne le laser de refroidissement à 254nm. Mes travaux nous ont permis d’augmenter le temps d’interrogation des atomes, étape nécessaire pour une nouvelle mesure de stabilité de l’horloge et la caractérisation des effets systématiques. Afin d’augmenter ultérieurement la stabilité, une refonte de la cavité optique qui piège les atomes dans le réseau s’est révèlée indispensable. La nouvelle cavité permet de capturer 10 fois plus d’atomes grâce à une profondeur de piégage acrue d’un facteur 3, influant directement sur le rapport signal sur bruit. Enfin, les résultats expérimentaux obtenus sont décrits dans le 5ème et dernier chapitre. La spectroscopie sur fond noir d’un échantillon de mercure polarisé en spin avec une largeur de raie record de 3.3Hz nous a permis de mesurer une stabilité de 1.2x10 -15 à une seconde, soit presque un facteur 5 mieux par rapport à notre précédente mesure. Une caractérisation de plusieurs effets systématiques sur la transitions d’horloge (shift colisionnel, effet zeeman ou encore effet de la lumière de piégage) a été menée au niveau de 10-16
The first two chapters of thesis describe the basics of optical standards and its applications. Highlight advantages of mercury as a frequency reference in optical lattice clock and give theoretical background about atom-light interaction, origins of systematic shifts and their influence on stability of a clock. The third chapter describes the experimental setup. It includes the schemes and operation of the main laser systems and their characteristics, the vacuum chamber and magneto-optical trapping of atoms. The fourth chapter is about the setup improvements that I made during the thesis. It describes the new doubling stage at 254 nm for the cooling laser system that was designed and implemented during the thesis. The new doubling stage allowed us to perform spectroscopies with long integration times necessary for the measurement of stability of our clock and systematic shifts. The second major and important improvement was the change of the lattice trap cavity. The new lattice cavity allowed us to increase trap depth by a factor of 3, number of trapped atoms by 10, improved the signal to noise ratio and increased stability of the clock. The fifth chapter tells about the obtained results. Thanks to all the technical improvements spectroscopy of the clock transition with the record linewidth of 3.3 Hz was demonstrated. State selection and spectroscopy on dark background were implemented. Stability of the clock was improved by a factor of 5 and measured to be 1.2*10-15 at 1 s. No observable collision shift and second order Zeeman shift were measured at the uncertainty level of ~1*10-16. The shift of the clock frequency due to lattice light was measured to be below 6*10-17

The measurement of time and frequency is at the heart of many technological applications and scientific measurements alike. In fact, the SI-unit the second is by quite a margin the SI-unit with the best relative uncertainty (ca. 10^{-16}), given by the accuracies of Cs fountain clocks probing the F = 3 - F = 4 ground-state transition in 133Cs. Still, demands for even higher accuracy and especially stability (a Cs fountain needs up to two weeks for the statistics to reach its declared uncertainty) are uttered in support of technological advancements (e.g. geodesy and GNSS systems) as well as fundamental science (physics beyond the standard model, tests of relativity). Nowadays optical lattice clocks confining a large number of neutral atoms in Stark shift free optical traps (the Stark shift free condition is characterised by a so-called magic wavelength of the trap) propose good candidates for a future redefinition of the SI-second in terms of an optical transition. Their accuracy and stability already surpass the Cs-fountains by two and three orders of magnitude, respectively. With further improvements to be expected in the near future, the application of optical lattice clocks to relativistic gravimetry, quantum computing, quantum simulation and fundamental physics keeps evolving. This thesis describes the development and characterisation of an 171Yb lattice clock at INRIM as well as its first frequency measurement campaigns and technolo- gies towards improved optical frequency measurements. The lattice clock confines cold atoms in a 1D optical dipole trap at the magic wavelength, which also cancels any Doppler- and recoil-related effects on the ultra-narrow clock transition. The first chapter offers a general overview of the physics behind lattice clocks and opti- cal frequency measurements. In the second chapter the 171Yb lattice clock developed during this work is expounded, including the trapping, state-preparation and state-probing of ultracold atoms inside the optical lattice. An exhaustive uncertainty budget for the clock transition is given and discussed showing already a performance beyond state-of- the-art Cs fountain clocks. An absolute frequency measurement obtained during this work is laid out. The result represents the lowest uncertainty achieved in a measurement of this transition against a primary frequency standard so far and is in agreement with previous values obtained by other groups around the world. A proof-of-principle experiment demonstrating for the first time the feasibility of transportable optical lattice clocks for geodesy and metrology applications outside of laboratory environments is described in chapter three. This experiment was conducted in collaboration with PTB and NPL and included a geodetic measurement with a transportable optical lattice clock that agreed with conventional methods as well as an optical 171Yb-87Sr frequency ratio measurement, enlarging the database on this particular ratio and thereby contributing to a possible redefinition of the SI-unit the second in terms of an optical transition or frequency-ratio matrix in the future. The fourth chapter discusses improvements added to the Yb lattice clock after the aforementioned measurements, in particular the stabilisation of the cooling and trapping lasers on a single stable low-drift cavity using mirrors coated for three disparate wavelengths across the optical spectrum. The simultaneous offset sideband locking and a throughout characterisation of the cavity are discussed. The last chapter is about the characterisation and optimisation of the NPL universal oscillator, which was conducted during my secondment at the NPL research facilities in the UK. The universal oscillator consists out of a femtosecond frequency comb, an ultra stable master laser and six slave oscillators. The femtosecond comb is transferring the stability of the superior master oscillator cavity to all six slave oscillators, which includes five lasers ranging from the infrared to the visible region. The principle of operation is explained and the obtained high performance of the spectral purity transfer set forth and discussed. This experiment demonstrated an unprecedented spectral purity transfer performance in a multi-branch configuration, opening the way for the interrogation of whole clock ensembles by just one master oscillator.

El presente proyecto consiste en la construcción de un plan de emprendimiento. Este plan es diseñado para varones y mujeres entre 20 a 45 años que radican en el Perú. Clock es nuestra marca desarrollada para brindar relojes importados de China. A través de nuestras validaciones, pudimos encontrar un segmento de clientes no satisfechos con respecto a la compra de relojes elegantes a un bajo precio. En ese momento nació la idea de nuestro proyecto, comercializar relojes a todo el Perú, llegando a todas las ciudades a través de nuestros socios claves.  Tras ocho semanas de duración de este curso, se ha comprobado la viabilidad de este proyecto. Llegamos a la conclusión que el modelo de negocio presentado es rentable para los inversionistas.
The present project consists in the construction of an entrepreneurship plan. This plan is designed for men and women between 20 and 45 years old living in Peru. CLOCK is our brand developed to provide watches imported from China. Through our validations, we were able to find a segment of unsatisfied customers regarding the purchase of good quality watches at a low price.  At that time the idea of our project was born, to market watches throughout Peru, reaching all cities through our key partners. After eight hard weeks of this course, the viability of this project has been proven. We conclude that the business model presented is profitable for investors. After 8 weeks of this course, the viability of this project has been verified. We conclude that the business model presented is profitable for investors.
Trabajo de investigación

Cyanobakterien zŠhlen zu den Šltesten Lebewesen auf der Erde. Diese Bakterien, auch Blaualgen genannt, trugen wesentlich zur Sauerstoffanreicherung der Erde bei, da sie eine ausgeprŠgte FŠhigkeit zur Photosynthese besitzen. Der produzerte Sauerstoff der Photosynthese hemmt jedoch eine weitere AktivitŠt von Cyanobakterien, die Stickstofffixierung. Um die Hemmung zu vermeiden, werden diese AktivitŠten zeitlich getrennt und optimal dem tŠglichen Hell-Dunkel-Rhythmus angepasst. Ein evolutionŠrer Vorteil wird erzielt, wenn der Organismus diesen Rhythmus antizipiert und sich darauf vorbereitet. Aus diesem Grund haben Cyanobakterien eine innere Uhr entwickelt, deren Rhythmus zirkadian ist, ãzirka diemÒ bedeutet ãungefŠhr ein TagÒ. Cyanobakterien der Spezies Synechococcus elongatus PCC 7942 haben sich als Modellorganismus etabliert, weil in ihnen die ersten bakteriellen zirkadianen Oszillationen auf molekularer Ebene entdeckt worden sind. Ihre zirkadiane Uhr entspringt dreier, auf der DNS beieinanderliegenden, Gene (kaiA, kaiB, kaiC) und ihrer dazugehšrigen Proteine. Phosphorylierte KaiC-Proteine Ÿben eine RŸckkopplung auf die Transkription von kaiB und kaiC aus, wodurch die AktivitŠt des kaiBC-Promotors zirkadian oszilliert. Eines der wichtigsten Experimente der letzten Jahre hat gezeigt, dass dieser Transkriptions-Translations-Oszillator mit einem weiteren Oszillator gekoppelt ist, der nicht von Transkription und Translation abhŠngt. Das Experiment des Kondo Labors rekonstruiert zirkadiane Oszillationen mit nur drei Proteinen KaiA, KaiB, KaiC und ATP. Die Proteine bilden Komplexe verschiedener Stoichiometrie, die durchschnittliche Phosphorylierung des Proteins KaiC zeigt stabile Oszillationen mit einer zirkadianen Periode. Da ein Entfernen von einem der Proteine zum Verlust der Oszillationen fŸhrt, wird dieser Post-Translations-Oszillator auch als Kernoszillator bezeichnet. Der Phosphorylierungszyklus von KaiC wird bestimmt durch fortlaufende Phosphorylierung und Dephosphorylierung an zwei Positionen des Proteins, den AminosŠuren Serin 431 und Threonin 432. Die Phase des Kernoszillators kann an der Verteilung der vier PhosphorylierungszustŠnde (nicht-, serin-, threonin- und doppeltphosphoryliert) abgelesen werden. KaiC wechselwirkt mit KaiA und KaiB, damit verschieden phosphorylierte KaiC synchronisieren und die Uhr Ÿber mehrere Tage konstante Oszillationen zeigt. Die Details dieser Wechselwirkung sind jedoch unbekannt. In dieser Dissertation erstelle ich ein mathematisches Modell des Kernoszillators und simuliere die vorliegenden Experimente des O''Shea Labors. Die Simulation reproduziert den KaiC Phosphorylierungszyklus der Uhr quantitativ. Um die wichtigsten experimentellen Nebenbedingungen zu erfŸllen, muss das theoretische Modell zwei molekulare Eigenschaften von KaiC berŸcksichtigen, wodurch ich wichtige Vorhersagen treffe. Die erste Nebenbedingung ist durch die Robustheit des Systems gegeben. Die KaiC-Phosphorylierung Šndert sich nicht, wenn die Gesamtkonzentrationen der drei Proteine in gleicher Weise variiert werden. Um diese Bedingung zu erfŸllen, muss das Modell zwei verschiedenartige Komplexe von KaiA und KaiC berŸcksichtigen. ZusŠtzlich zu einem KaiAC Komplex, der die Autophosphorylierung von KaiC unterstŸtzt, muss KaiC den grš§ten Teil von KaiA unabhŠngig vom Phosphorylierungszustand sequestrieren. Diese zweite Bindestelle ist meine erste theoretische Vorhersage. Die zweite Nebenbedingung ist durch das Ÿbergangsverhalten nach Hinzugabe von KaiB gegeben. KaiB induziert eine Dephosphorylierung von KaiC, die abhŠngig vom Phosphorylierungsniveau ist. Ein Umschalten zwischen phosphoylierendem und dephosphorylierendem KaiC ist deshalb nur in bestimmten Zeitfenstern mšglich. Um die gemessenen Zeitfenster in der Simulation zu reproduzieren, postuliere ich im Modell, dass sechsfach Serin phosphorylierte KaiBC Komplexe KaiA inaktivieren. Diese hochgradig nichtlineare RŸckkopplung ist meine zweite theoretische Vorhersage. Die beiden Vorhersagen werden anschlie§end experimentell ŸberprŸft. HierfŸr werden aufgereinigte Kai-Proteine mit ATP gemischt. Proben an ausgewŠhlten Zeitpunkten werden mit der nativen Massenspektrometrie untersucht. Diese ist eine neuartige Methode, die es erlaubt, intakte Proteinkomplexe zu untersuchen. Die Spektren bestŠtigen sowohl die zweite KaiAC-Bindestelle als auch die nichtlineare RŸckkopplung. Das mathematische Modell erlaubt es au§erdem, die drei definierenden Prinzipien von zirkadianen Uhren fŸr den Kernoszillator zu erklŠren. Erstens sichern konstante Phosphorylierungs- und Dephosphorylierungsraten von KaiC und ein pŸnktliches Umschalten zwischen beiden Phasen den Freilauf des Oszillators. Dieser Freilauf bewirkt, dass die zirkadiane Uhr auch unter konstanten Bedingungen, vor allem gleichbleibenden LichtverhŠltnissen, weiterlaufen kann. Zweitens muss die Periodendauer des Oszillators zu unterschiedlichen Šu§eren Bedingungen erhalten bleiben (Temperaturkompensation). Diese Bedingung wird realisiert, indem temperaturabhŠngige Dissoziationskonstanten von KaiAC und KaiBC Komplexen Phasenverschiebungen erzeugen, die sich gegenseitig kompensieren. Drittens muss die Phase des Oszillators sich dem Tagesrhythmus anpassen kšnnen. Diese Anpassung folgt aus einem Šu§eren Warm-Kalt-Rhythmus, der die drei temperaturabhŠngigen Phasenverschiebungen nur zum Teil einschaltet und damit die Kompensation verhindert. Eine in silico Evolutionsanalyse zeigt, dass eine zweite phosphorylierbare AminosŠure einen evolutionŠren Vorteil bringt und die Verteilung der PhosphorylierungszustŠnde optimiert ist, um eindeutig die Zeit zu bestimmen. Das Ergebnis weist darauf hin, dass diese Verteilung die physiologisch wichtige Ausgangsgrš§e der Uhr ist und die vier PhosphroylierungszustŠnde die Funktionen der zirkadianen Uhr von Cyanobakterien sichern.
Biological activities in cyanobacteria are coordinated by an internal clock. The rhythm of the cyanobacterium Synechococcus elongatus PCC 7942 originates from the kai gene cluster and its corresponding proteins. In a test tube, the proteins KaiA, KaiB and KaiC form complexes of various stoichiometry and the average phosphorylation level of KaiC exhibits robust circadian oscillations in the presence of ATP. The characteristic cycle of individual KaiC proteins is determined by phosphorylation of serine 431 and threonine 432. Differently phosphorylated KaiC synchronize due to an interaction with KaiA and KaiB. However, the details of this interaction are unknown. Here, I quantitatively investigate the experimentally observed characteristic phosphorylation cycle of the KaiABC clockwork using mathematical modeling. I thereby predict the binding properties of KaiA to both KaiC and KaiBC complexes by analyzing the two most important experimental constraints for the model. In order to reproduce the KaiB-induced dephosphorylation of KaiC a highly non-linear feedback loop has been identified. This feedback originates from KaiBC complexes, which are exclusively phosphorylated at the serine residue. The observed robustness of the KaiC phosphorylation level to concerted changes of the total protein concentrations demands an inclusion of two KaiC binding sites to KaiA in the mathematical model. Besides the formation of KaiAC complexes enhancing the autophosphorylation activity of KaiC, the model accounts for a KaiC binding site, which constantly sequestrates a large fraction of free KaiA. These theoretical predictions have been confirmed by the novel method of native mass spectrometry, which was applied in collaboration with the Heck laboratory. The mathematical model elucidates the mechanism by which the circadian clock satisfies three defining principles. First, the highly non-linear feedback loop assures a rapid and punctual switch to dephosphorylation which is essential for a precise period of approximately 24 h (free-running rhythm). Second, the dissociation of the protein complexes increases with increasing temperatures. These perturbations induce opposing phase shifts, which exactly compensate during one period (temperature compensation). Third, a shifted external rhythm of low and high temperature affects only a part of the three compensating phase perturbations, which leads to phase shifts (phase entrainment). An in silico evolution analysis shows that the existing second phosphorylatable residue of KaiC is not necessary for the existence of sustained oscillations but provides an evolutionary benefit. The analysis demonstrates that the distribution of four phosphorylated states of KaiC is optimized in order for the organism to uniquely distinguish between dusk and dawn. Consequently, this thesis emphasizes the importance of the four phosphorylated states of KaiC, which assure the outstanding performance of the core oscillator.

This thesis will discuss the making of my short film The Water Clock at the University of New Orleans from its inception to its final short film form. Part One discusses the balancing of content and style and explores the relation between time and water as inspirations for story. Part Two details the preproduction process and major crew members’ collaborations and contributions before filming. Part Three describes daily successes, struggles, and direction while in production. Part Four describes every phase of the post-production process as the film is completed. Lastly, I will analyze my personal growth as a filmmaker.

Clock synchronization between different entities in a system has been approached using two main methods, decentralized and centralized synchronization. Examples of centralized synchronization include Network Time Protocol (NTP) and the use of Global Positioning System (GPS) as a central clock. The synchronization of clocks in distributed systems is a well-studied and difficult problem. Current solutions possess a significant convergence delay and a non-perfect synchronization window. This thesis approaches the problem of clock synchronization in decentralized systems by analysing and using pulse-coupled oscillator models, like the Kuramoto model and the Mirollo-Strogatz firefly model, while leveraging the knowledge of internode latencies to form a biased gradient overlay topology, and creating a custom firefly synchronization model. The system node coordinates are indicative of internode latencies if they are assigned statically using a latency data set or through a dynamic coordinate protocol, which assigns coordinates according to current internode latencies. The coordinates are then used to create an overlay over the physical topology by having larger number of links with lower internode latency. Neighbours are selected based on an information need basis. Logical time on the nodes is set in sync along with the phase synchronization using fine tuned algorithms to set a common timestamp on each cycle, and to optimize the synchronization window and the convergence time. The results show that the gradient firefly synchronization is efficient in convergence time as well as synchronization window. The protocol works better with a single cluster of nodes as compared to multiple clusters. It is concluded in the thesis that latency aware gradient firefly synchronization protocols can be used per cluster and the performance can be improved further with the incorporation of dynamic coordinate protocols.

The involvement of clock genes in the temporal regulation of the function and lifespan of the corpus luteum (CL) has not been investigated in detail. Immunohistochemistry and real-time quantitative PCR techniques were used to examine the expression of the canonical clock genes: period1, period2, period3, cryptochrome1, cryptochrome2, clock and bmal1, at protein and mRNA levels respectively. The expression of the clock genes was examined in the human CL, cultured luteinised granulosa cells, cultured luteal fibroblast-like cells and the ovine CL. The main findings were that clock genes are expressed in the human and ovine CL; that this expression is manifest at mRNA and protein level in all discernible cell types within the human and ovine CL, and that the pattern of mRNA expression differs between the early luteal phase compared to the late luteal phase. The circadian expression of the clock genes was established in the ovine CL during the late luteal phase and could not be determined in the human CL, although indications from cultured luteinised granulosa cells and luteal fibroblast-like cells suggest that this may also be the case in humans. With the exception of per2, the circadian pattern of clock gene expression emerged in the late luteal phase CL when the early luteal phase CL did not demonstrate circadian clock gene expression. This emergence later in the lifespan of the CL was akin to that observed in embryonic development, where the clock genes are initially non-rhythmic but then acquire circadian rhythmicity with age. In this case, the clock genes have been proposed to perform a non-classical circadian timing role in the timing of embryonic development. The per2 gene was also found to be special, in its loss rather than gain of rhythmic gene expression across the luteal lifespan and in its protein localisation in the cytoplasm of some granulosa-lutein cells. The exceptional behaviour of per2 is consistent with a growing body of evidence supporting its role as a unique clock gene in many respects, able to maintain circadian protein levels in the absence of circadian gene expression, integrating peripheral clock inputs and outputs and acting as a tumour suppressor gene. The CL was also found to be a potential target of melatonin regulation, based on its possession of melatonin MT1 receptors and the timing of circadian cry1 gene expression in the late luteal phase. The expression of cry1 is known to be directly melatonin-induced in the PT and appeared to be similarly activated, downstream of a melatonin signal, in the CL. This supports the evolving view of a hierarchical organisation of the central and peripheral clocks, which are integrated in order to establish information feedback loops that maintain circadian homeostasis, and which can regulate seasonal physiology.

In distributed real-time systems, data are time-dependent and the time notation, which marks the validity of data, is an indispensable component of data. Therefore, setting up a common time base in distributed real-time systems to provide all computers in the system with a consistent view of time inevitably becomes important. Clock synchronization is an approach to establishing such an greed global time base in a system. The aim of work is to investigate clock synchronization in a distributed real-time system. A hybrid synchronization method is adopted in the project. By this means, each computer in the system periodically exchanges time messages with other computers via the existing communication network, and thus knows the clock time of every other computer which participates in the clock synchronization. Then, it applies a synchronization algorithm on the received time data to compute an approximate global time for the system, and finally adjusts its local clock to the computed global time. An approximate global time is thus reached and maintained. In this dissertation, various approaches are studied and compared. A hybrid scheme is proved to be the currently dominant solution to the problem investigated, in that it balances the performance and cost criteria. The fault tolerant averaging algorithm selected for this attempt is discussed and analysed, and its software implementation is described. The design and silicon implementation of the associated VLSI clock synchronization unit device are also introduced. The experiments with clock synchronization on an Ethernet system are presented. The results of the experiments are given and analysed to support the conclusions that the technique developed in this work is feasible and can be used in distributed real-time systems. On this basis, recommendations for further research in clock synchronization are suggested.

This thesis focuses on the design, construction and stable integration in mammalian cells of a natural microRNA-based genetic oscillator. This will help both in better understanding the rules underlying the periodic expression of genes observed in major biological processes, such as the circadian clock and cell-cycle, as well as, in generating new tools to probe and investigate the function of a gene in a cell, by allowing not only its over-expression or knock-down, but also its cyclic expression. The circuit involves a positive feedback loop, consisting of a transcription factor (TF) activating itself, and a negative feedback loop, using a natural micro RNA controlled by the TF, which induces degradation of the TF itself. The circuit was built in a modular way, and implemented it in two lentiviral vectors able to infect both dividing and non-dividing cells, hence suitable for many different applications. Since obtaining stable oscillations is non-trivial, a modified version of the oscillator was engineered, including an intermediate step between the TF and the microRNA, to increase the delay in the negative feedback loop. The oscillatory behavior was tested via in vivo time-lapse fluorescence microscopy in both versions of the oscillator, since both the TF(s) and the microRNA are expressed together with fluorescent reporters.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Includes bibliographical references (p. 143-146) and index.
by Boaz Patt.
Ph.D.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California
Sub-Microsecond timing accuracy for event tagging and multisite synchronization is possible using the Global Positioning System. In order to maintain a high degree of accuracy during periods when no satellites are visible, a highly stable local time base is required. For those cases which require Cesium Oscillator stability, initial cost and continuing maintenance of the Cesium Oscillator must be considered. A viable alternative is attained by using the Global Positioning System and an oscillator disciplining process. With this system, near Cesium performance can be achieved using a more rugged lower cost Rubidium oscillator. Additionally, when 24 hour satellite coverage becomes available, system performance may surpass that of a Cesium in long term stability as well as long term drift. This presentation describes the system components, including Global Positioning System receiver, Miniaturized Controllable Rubidium Oscillator and Global Positioning System Clock. Clock timing accuracy and short and long term frequency stability results are discussed along with the control algorithms used in the disciplining process. A brief discussion of the computer modeling tools used is also presented.

Метою роботи є розробка мобільного додатку для платформи Android, що базується на алгоритмі визначення пробудження людини. Дана дипломна робота присвячена розробці програмного продукту для визначення у людини проблем зі сном. Було розглянуто існуючі методи розробки алгоритмів, та створено унікальний алгоритм, що допоможе людям виявити проблеми зі сном та вчасно звернутись до лікаря. Розроблено мобільний додаток «Smart Clock». Додаток-будильник, який аналізує протягом ночі, скільки разів людина прокидалась. Це відбувається завдяки унікальному алгоритму визначення пробудження людини. Це відбувається завдяки сенсорам вбудованим у будь який нині смартфон.

The aim of this project was to make an alarm clock with multiple functions intended to make waking up a more pleasant experience. The main function of the alarm clock was to simulate a sunrise by raising roller blinds. The project was limited in scope due to both time and budget. If the main function was to be completed, more secondary functions were to be implemented. An intuitive control method, supplementary lights and wireless connectivity were for example considered as secondary functions. A demonstrator was built, using an Arduino microcontroller at its core. Different types of motors were considered for raising the roller blinds but in the end a stepper motor was chosen because of its ease of use. To keep track of the time a real time clock module was connected to the Arduino. The time was displayed on an liquid crystal display and the clock settings were controllable with five different buttons. All of the implemented functions worked with satisfaction. Even if the implemented functions worked, there are still a lot of improvements to be made before the prototype can be called a smart alarm clock.
Syftet med detta projekt var att göra en väckarklocka med flera funktioner avsedda att göra väckningen till en mer trevlig upplevelse. Väckarklockans huvudsakliga funktion var att simulera en soluppgång genom att dra upp rullgardiner. Projektet var begränsat både i tid och budget. Om huvudfunktionen blev klar skulle fler funktioner läggas till, som till exempel en intuitiv kontrollmetod, en kompletterande ljuskälla och trädlös anslutning arbetas vidare med. En prototyp byggdes med en Arduino mikrokontroller som grund. Olika typer av motorer beaktades för att rulla upp rullgardinerna, men i slutändan valdes en stegmotor på grund av att den ansågs lättare att använda. För att hålla koll på tiden anslöts en realtidsklockmodul till Arduinon. Tiden visades på en LCD bildskärm och klockinställningarna var styrbara med fem olika knappar. Alla implementerade funktioner fungerade tillfredsställande. Även om de implementerade funktionerna fungerade finns det fortfarande många förbättringar att göra innan prototypen kan kallas en smart väckarklocka.

For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces.

Clock synchronization is one of fundamental requirements in distributed networks. However, the imperfection of crystal oscillators is a potential hurdle for network-wide collaboration and degrades the performance of cooperative applications. Since clock discrepancy among nodes is inevitable, many software and hardware attempts have been introduced to meet synchronization requirements. Most of the attempts are built on communication protocols that demand timestamp exchanges to improve synchronization accuracy or resource efficiency. However, link delay and environmental changes sometimes impede these synchronization efforts that achieve in desired accuracy. First, the clock synchronization problem was examined in networks where nodes lack the high accuracy oscillators or programmable network interfaces some previous protocols depend on. Next, a stochastic and practical clock model was developed by using information criteria which followed the principle of Occam's razor. The model was optimized in terms of the number of parameters. Simulation by using real measurements on low-powered micro-controllers validated the derived clock model. Last, based on the model, a clock tracking algorithm was proposed to achieve high synchronization accuracy between unstable clocks. This algorithm employed the Kalman filter to track clock offset and skew. Extensive simulations demonstrated that the proposed synchronization algorithm not only could follow the clock uncertainties shown in real measurements but also was tolerant to corrupted timestamp deliveries. Clock oscillators are vulnerable to noises and environmental changes. As a second approach, clock estimation technique that took circumstances into consideration was proposed. Through experiments on mobile devices, the obstacles were clarified in synchronization over wireless networks. While the causes of clock inaccuracy were focused on, the effect of environmental changes on clock drifting was investigated. The analysis of the observations inspired an M-estimator of clock error that was accurate but under dominant disturbances such as oscillator instability and random network delay. A Kalman filter was designed to compensate with temperature changes and estimate clock offset and skew. The proposed temperature-compensated Kalman filter achieved the better estimates of clock offset and skew by adjusting frequency shifts caused by temperature changes. The proposed Kalman filter-based clock synchronization was implemented in C. A real-time operation was proved by clock tracking between two mobile platforms that the synchronization technique was implemented on. Moreover, the technique was converted to fixed-point algorithm, which might degrade performance, to evaluate the synchronizing operation on fixed-point processors. The fixed-point simulation reported performance degradation caused by limited hardware resources; however, it also corroborated the applicability of the synchronization technique.

Somites are precursors of the vertebrae, ribs, and associated musculature and their formation relies on ordered and timely segmentation during early embryonic development. Somites form as they ‘pinch’ away from the pre-somitic mesoderm (PSM) with a species-specific periodicity, coinciding with waves of cycling mRNA expression of ‘clock’ genes sweeping across the PSM that are regulated by a molecular oscillator. Mathematical models suggest that sustained rapid oscillations of Notch-regulated gene transcription in the PSM depend on transient negative feedback loops that rely on unstable protein products. However, the pacemaker mechanism that underlies this segmentation clock is poorly understood and little experimental evidence exists linking the level of clock proteins to the periodicity of clock gene oscillations. It was previously shown that pharmacological inhibition of Wnt signalling slows oscillating transcription of the Notch target Lfng in the PSM of the chicken and mouse embryos. We have shown that another Wnt inhibitor XAV939 and a number of cdk inhibitors can phenocopy this effect in the PSM. This effect appears independent of the cell cycle and these inhibitors appear to have a general effect on transcription in the chicken PSM. In contrast to a previous report, we find that direct inhibition of Sonic hedgehog (Shh) signalling has no effect on oscillating clock gene transcription in the chicken PSM. A custom-made antibody reveals that the level of a key clock protein is increased in the chicken PSM when treated with XAV939, or either of the cdk inhibitors which also slow oscillating clock gene transcription. This molecular evidence supports models which predict that the level of clock proteins in the PSM is fundamental to maintain rapid clock oscillations and timely somite formation. The Microarray and RNA-seq analyses of chicken PSM tissues discovered a set of genes whose transcription is affected by all three inhibitor treatments relative to corresponding controls. These candidates will be studied further as potential regulators of the segmentation clock period. Immunoprecipitation with the custom-made antibody followed by mass spectrometry analysis of lysates from chicken PSM tissues treated with reagents that modify clock pace will uncover any post-translational modifications of this key protein which are altered by these inhibitors with the aim of identifying any key enzymatic regulators of its stability which act as part of the segmentation clock pacemaker mechanism.

Ingeniero Civil Electricista
Los circuitos digitales, que juegan un papel crucial en la vida cotidiana, consumen grandes cantidades de potencia lo que es considerado como una situación no deseada, lo que es particularmente cierto para equipos que dependen de baterías como celulares, es por esto que los diseñadores de circuitos así como las herramientas de síntesis utilizan diferentes técnicas con el fin de reducir su consumo de potencia. Una de las técnicas de reducción de potencia mas exitosas es clock-gating cuyo objetivo es reducir el consumo de potencia generado por las transiciones debidas a la señal de clk. La reducción de potencia se logra mediante la inserción de clock-gating cells (celdas de clock-gating) que impiden que la señal de clk llegue a los Flip-Flop cuando el valor de la salida de estos no se espera que cambie. Los diseños basados en Latch, que si bien no son tan utilizados como los diseños basados en Flip-Flop debido a sus complejidades adicionales, todavía son utilizados gracias a ciertos beneficios que presentan las restricciones de timing (timing o sincronización) de los Latch, sin embargo ninguna de las herramientas de síntesis existentes permite la inserción automática de clock-gates para diseños basados en Latches, por lo que los diseñadores de circuitos se ven forzados a insertar las clock-gates de forma manual lo que es ineficiente. El presente trabajo se enfoca en los mecanismos de clock-gating y los requisitos que se deben cumplir para permitir su uso en diseños basados en Latches desde la perspectiva de una herramienta de síntesis, al tiempo que provee de una discusión teórica sobre las diferencias entre Latches y Flip-Flops y como estas diferencias fuerzan los requerimientos de una herramienta de inserción de clock-gates Considerando las restricciones que debieran aplicar para una herramienta de inserción de clock-gates automática enfocada en Latches y utilizando el entorno de desarrollo provisto por Synopsys así como el código existente en la herramienta de síntesis desarrollada por ellos, se desarrolla un prototipo de inserción de clock-gates para Latches como parte de Design-Compiler El prototipo una vez embebido en Design-Compiler es probado en diversos diseños creados con este propósito y un diseño de mayor envergadura provisto por uno de los clientes de Synopsys y que es utilizado durante el desarrollo de circuitos reales, lo cual permite verificar la robustez de la herramienta desarrollada en diseños grandes.

Clock synchronisation is a widely studied problem. Most research has focused on real-time clock synchronisation algorithms, which run as background processes to maintain synchronisation between the clocks of a collection of computers. Research has also been done into off-line clock synchronisation algorithms. These algorithms can be used where time-stamped event records have been recorded on a collection of computers. In evaluating the effectiveness of a clock synchronisation algorithm, it is important to determine the offsets of clocks from each other or from an external reference. The reason that the clock synchronisation problem is a difficult one is because it is not possible to directly measure the offsets between two clocks without using special hardware. Consequently, in all of the clock synchronisation work with which we are familiar, effectiveness is assessed by indirect measures of clock offsets, or by simulation. We have developed hardware and software to enable us to directly determine clock offsets so the performance of clock synchronisation algorithms can be accurately assessed. The main hardware component is a "clockcard" that connects to any IBM PC compatible parallel port. On the clockcard are two logical 32-bit binary counters that can be latched at exactly the same time. One of the counters is clocked from an on board oscillator that mimics the accuracy of modern day computer oscillators. The other counter is driven via an external clock. In a collection of computers under test, all the external counters are driven from the same external clock, so each clockcard has a notion of external global time. The local counter on the clockcard is used as a replacement for the local clock on the computer that the clockcard is attached to. The new local clock is the one synchronised by a clock synchronisation algorithm under test. Whenever timestamps are read from the clockcard, the values of both counters are returned. The global timestamps allow offsets between local clocks to be measured very accurately. We describe the design and construction of the test bed hardware, design and implementation of software to interface clock synchronisation programs to the test bed, and present results from initial experiments performed to check that the test bed works as intended.

Circadian and photoperiodic phenomena serve to organize the temporal pattern of various biological processes. While the former generates endogenous daily rhythms, the latter is related to seasonality. In Drosophila melanogaster, the gene timeless (tim) encodes a cardinal component of the circadian clock and also contributes to photoperiodism, which is observed as an adult reproductive diapause. In this work, natural tim variants were examined for diapause across different temperatures and photoperiods. The newly derived allele, ls-tim, exhibited consistently higher diapause levels than the ancestral one, s-tim, implicating a putative adaptive advantage in the seasonal European environment and providing a perfect substrate for the recently proposed scenario of directional selection. To investigate further genetic links between circadian and photoperiodic mechanisms, classical clock mutations and transgenes were placed on a natural congenic background and assayed for locomotor activity behaviour and diapause response. Surprisingly, the results not only highlighted the importance of tim, and its natural alleles, but also revealed the participation of other clock components in diapause, suggesting that both daily and seasonal timers might have molecularly coevolved. The phenotypic effects promoted by ls-tim arise from the protein isoform LTIM, which expresses an additional N-terminal fragment. To study the adaptive significance of the N-terminal residues, including putative phosphorylation sites, a number of mutagenized TIM constructs were generated and functionally analysed. At the molecular level, it was demonstrated that both the N-terminus length and the order of its residues are important variables modulating the interaction dynamics between TIM and CRYPTOCHROME (CRY). At the behaviour level, the overall amino acid composition, rather than a particular order, appeared to be more critical for the phaseshift responses. Interestingly, despite the functional importance of the N-terminus, a deletion mapping analysis revealed that CRY directly binds to a protein sequence located at TIM C-terminus.

A clock driver that works on the principle of charging and discharging the clock network in a VLSI circuit in two steps is investigated in a few different configurations. The aim of the design is twofold: to reduce the power consumption to reduce the third harmonic of the clock signal, and thereby the EMI (electromagnetic interference) emitted by the clock network. The first should be possible to accomplish as the clock interconnect network gets charged by half the voltage during each rising transition, and the second should be possible to accomplish by carefully time the rising and falling transitions, so that the third Fourier coefficient of the resulting wave form cancels. The drivers are loaded by eight 16-bit adders. The drivers’ power consumption, and the spectrum of the output signal, are investigated under varying clock frequencies, power supply voltage, and driver architecture. The results are compared to a conventional square wave clock. The results are that while the third harmonics of the resulting output sees an improvement in all the investigated cases over the square wave clock, the power savings are, for higher clock frequencies, more than completely canceled by the extra power needed in the logic stage which controls these drivers. On the other hand, the power consumption of the new driver appears to drop below that of the conventional driver when the clock frequency drops below approximately 100MHz. A few suggestions for further investigations of new designs and clock wave forms are given.

Optical atomic clocks with precisions and accuracies in the 10\(^-\)\(^1\)\(^8\) level [1] are now the most advanced man-made timekeeping devices. They outperform the microwave cesium atomic clocks that realize the SI definition of the second. Scaling down the size of optical atomic clocks may open the door to a range of industrial and space applications. In this thesis, the design and preliminary results of a compact strontium cooling system are presented. In the first cooling stage, the high power 461 nm laser with 300 mW output features a modular design, while smaller laser sources for demonstrating a strontium magneto-optical trap have also been investigated. An innovative design that couples a spectroscopy cell directly into the scientific chamber reduces the overall size and power consumption of the system. Additionally, using strontium oxide as a source of strontium atoms suitable for optical clocks has achieved initial success. For the first time, a single-beam MOT configuration is applied to strontium. In this novel apparatus, the blue MOT and red MOT broadband cooling phases are able to trap 5x10\(^6\) and 1000 atoms, respectively. This work shows promising progress towards developing a functional miniaturized strontium optical lattice clock.

It is well established that elderly individuals have increased difficulty sleeping at night combined with falling asleep and waking up earlier. Although these age-related declines in circadian output are clearly observable in activity recordings of laboratory animals, the underlying changes in molecular and neuronal activity remain unknown. The fruit fly, Drosophila melanogaster, has long been used as a model for studying the circadian system and for ageing research. In this thesis Drosophila was used as a model to study the effect of ageing on circadian and sleep behaviour. Circadian behaviour was measured using the Drosophila Activity Monitoring system, recording activity of flies at various stages of the ageing process, demonstrating a linear decline in rhythm strength with age combined with an increase in period length. Weakened circadian output is combined with significant alterations of diurnal behaviour of Drosophila, namely a reduction in morning and evening anticipatory behaviour. Ageing also has a significant impact on sleep behaviour, significantly increasing sleep duration whilst reducing latency, with larger effects observed on day- time sleep. Age-related changes in neuronal activity were investigated using whole-cell patch clamp electrophysiology to record from large lateral ventral (l-LNV) clock neurons, finding that ageing was associated with a significant decrease in input resistance, but no significant changes in spontaneous electrical activity or membrane potential. Manipulating the electrical properties of the circadian system by knocking down expression of candidate ion channels in all clock neurons had significant effects on behaviour, linking electrical activity with clock outputs. The results presented in this thesis demonstrate the suitability of Drosophila as a model to interrogate how ageing effects the circadian clock, identifying Alterations in the electrical properties of the l-LNV neurons may underlie observed changes in diurnal activity and sleep, while decreased remodelling of the s-LNV neurons can explain weakened circadian behaviour.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 103-105).
Reducing the timing uncertainty associated with clock edges has become an exceedingly difficult problem as clock frequencies in high-performance processors increase past several gigahertz. Absolute quantities of skew and jitter that were insignificant at lower frequencies now consume an increasingly large percentage of each clock cycle and directly reduce the time available for logic propagation. Processor designers currently employ several types of electrical deskew mechanisms to combat this problem in order to delay the inevitable need for more radical clocking solutions. Optical clock distribution has the potential to deliver extremely high precision global clocks across large chips. However, traditional transimpedance amplifier approaches to optical-electrical conversion introduce so much timing uncertainty that the accuracy gained through optical global distribution is lost at the global-to-local clock domain interface. This thesis analyzes the feasibility of a phase-locked loop (PLL) based approach to the optical-electrical clock signal conversion. The proposed small-signal current-steering optical-electrical phase detector extracts timing information from the optical reference without explicit optical-electrical conversion. This phase detector is integrated with a loop filter, LC VCO, and frequency divider to form a complete optical-electrical PLL system capable of generating 1.6 GHz local electrical clocks from a 200 MHz global optical reference. The insights gained through the design and implementation of this system are used as the basis for a broader analysis of the advantages and challenges of PLL-based optical clock distribution systems.
by Alexandra M. Kern.
S.M.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 115-121).
Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.
by Belal Moheedin Helal.
Ph.D.

Due to the recent success, in terms of accuracy and precision, of a number of strontium optical lattice optical frequency standards, and the classification of the 5s^{2 1}S₀ to 5s5p ³P₀ transition in neutral strontium as a secondary definition of the SI unit of the second, many new strontium lattice clocks are under development. The strontium optical lattice clock (Sr OLC) at the National Physical Laboratory (NPL) is one such project. This thesis describes the design and build of the NPL Sr OLC, discussing the considerations behind the design. Details of the first cooling stage are given, which includes the characterisation of a novel permanent-magnet Zeeman slower by measurements of the longitudinal velocity distributions and loading of the MOT at 461 nm. Development of a narrow linewidth laser system at 689 nm is described, which is used for initial spectroscopy of the second-stage cooling transition. In particular, this work describes progress towards two independent ultra-narrow linewidth clock lasers. The new generation of strontium lattice clock experiments have focused on characterising the systematic frequency shifts and reducing their associated fractional frequency uncertainties, as well as reducing the fractional frequency instability of the measurement. One focus of the Sr OLC at NPL is to help characterise the frequency shift of the clock transition due to black-body radiation (BBR), which is currently the largest contributor to the uncertainty budget of the measured clock frequency. Our approach, discussed here, is to make a direct, differential measurement of the shift with the atoms housed alternately in environments of differing temperatures. Better characterisation and control of the BBR frequency shift of the strontium clock transition is crucial for the future of the Sr OLC as a leading frequency standard.

In vertebrates, the repeating vertebrae in the vertebral column are the clearest indicators of the segmented body plan. The embryonic precursors of the vertebral column and skeletal musculature are bilaterally symmetric blocks of tissue flanking the notochord called somites. Somites are generated sequentially and periodically from an unsegmented tissue called the presomitic mesoderm (PSM) by a process called somitogenesis. Underlying the periodicity of somitogenesis are transcriptional oscillations of cyclic genes in the cells of the PSM. On a tissue level, these oscillations manifest as travelling waves, departing from the posterior and arresting in the anterior. The position of arrest prefigures the position of the new somite boundary. The molecular network that comprises the cyclic genes and their regulation in the PSM is termed the segmentation clock. Retinoic acid (RA) has been previously proposed to be a differentiation signal that acts to arrest the oscillations at the anterior of the PSM. This thesis shows the zebrafish RA catabolism mutant giraffe has an altered cyclic gene wave pattern, an observation that suggests that rather than stop their oscillations, cells tune their frequencies in response to RA signalling, introducing a novel function for RA in the zebrafish segmentation clock. In amniotes, the segmentation clock instructs the metamery of the vertebral column, but in zebrafish, the relationship is not established. This thesis demonstrates that the segmentation clock is not required in zebrafish for the development of a periodic vertebral column by using a novel segmentation clock mutant, thereby supporting a role for the notochord in the development of vertebral column metamery. Therefore, two periodic patterning processes establish zebrafish body pattern – one segments the somites and musculature, and the second segments the vertebral column. This thesis advances the understanding of the mechanisms of body pattern establishment by way of these novel insights.

碩士
中原大學
資訊工程研究所
100
The power consumption is always an important issue in high performance VLSI design. Clock gating technique has been used widely to reduce the power consumption in clock circuit design. By simply shutting off a part of clock gating cells during the idle state, designer can easily reduce the power consumption. Previous research has shown that fewer clock gating cell can benefit the area and the routability of clock circuit. In this paper, we propose a three-phase clock gating optimization approach by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating cell, we derive a parameter  that can be used to adjust the tradeoff between clock gating cell and buffer. Our three-phase algorithm described below (1) flip-flop clustering (2) clock gating cell legalization (3) solution refinement. In the first phase we split the die into three regions and clustering flip-flops with different strategy in each region. After the first phase, we can get an initial solution which is not meeting the setup-time constraint. Therefore, in the second phase, we propose two methods to fix the setup-time constraint and also reduce the number of clock gating cells and buffers. In the final phase, we will merge each nearby clock gating cell if the result can improve our cost function. Experimental results show that our proposed approach can reduce the number of clock gating cells and buffers in each phase. Moreover, the well-defined parameter derived by input parameter  can adjust the tradeoff between clock gating cell and buffer efficiently.

碩士
國立臺灣大學
昆蟲學研究所
96
Not only light, but also temperature can synchronize the circadian clock of German cockroach (Blattella germanica). By manipulating environmental conditions, we have proved a unique thermal clock underlying rhythmic locomotion behavior. Thermal and Photoperiodic clock may exert its own influence on the overt rhythm simultaneously, but can also couple forces for a proper phase. For male German cockroach, the locomotor circadian rhythm with only one peak of daily activity was found under constant temperature and LD or DD condition, which was restricted in scotophase or subjective night as a nocturnal animal does. However, a thermal cycle (30:20°C) under constant darkness, might switch the active phase from cold (subjective night) into warm (subjective day) phase, under which caused the presenting of multiple activity peaks. Two of the three peaks were triggered by the thermal clock at the transition of temperature, in the mean time, the photo clock kept a free-running rhythm, and would couple again with the thermal clock when activity peaks were getting closer. Although both clocks share the same opportunity in leading the activity pattern either in synchrony or free-running, the DD condition insinuate the power of photo clock. This finding provides direct evidence of a cooperative multiple-oscillator system for different zeitgebers, and also a novel behavioral basis from current studies on circadian mechanism.

碩士
國立中央大學
電機工程研究所
91
The optical network applies in the high-speed and long-haul communications has become a major trend presently. Today, the highest speed for wired data communication is reached using optical fiber transmission operating in accordance with the SONET (Synchronous Optical Networking Standards) standards. The data rate of the SONET OC-192 is close to 10Gb/s and it expects that the data rate of 10Gb/s will be universal in backbone network and applied in terminal networks. And the transceiver is the critical device in high-speed optical networks. The goal in the thesis is to develop a clock multiplier unit and clock/data recovery circuit that suit to the SNOCT OC-192 transceiver. At the transmitter end, the encoded parallel data must be transformed into serial signals by MUX and therefore a CMU is needed to generate a high-speed reference signal for parallel-to-serial data conversion and multiplexing. At the receiver end, a CDR circuit derives the input frequency and phase of the NRZ signals and generates a high precision clock to sample the incoming data so as to reduce the bit error rate. Clock multiplier Unit is accomplished by using PLL-based frequency synthesizer. The main goal is to generate a reference signal for multiplexer. Its function is to synthesize a 9.9533GHz output signal form a 622.08MHz reference source according to the SONET OC-192 standard. For various applications, the output frequency range of the oscillator covers that of various communication standards around 10Gb/s. The CMU circuit is fabricated in TSMC 0.35μm BiCMOS process and its operation voltage is 3.3V. An individual chip of 16:1 static frequency divider has been designed and demonstrated. Its operation range is 500 MHz ~ 9.1 GHz, chip size is 1 × 0.8 mm2, and power consumption is 78.7mW. It can be used to generate down-frequency clock signals for demultiplexer and used in frequency synthesizer. A fully differential clock multiplier unit presented in the thesis achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture. The CMU has a die size of 2.1 × 1.1 mm2 and consumes 230.4mW from 3.3 V. PLL-based CDRs are benefited from capabilities of high frequency operation and feasibility for monolithic integration. Moreover, the phase frequency detector can adjust the transition edge of the sampling clock and align to that of the input data. Therefore, conventionally, high frequency clock and data recovery circuits are of PLL based type. A PLL-based high-speed CDR circuit without reference signals is achieved in this thesis. Because the phase detector used in the CDR is binary type, the conventional linear model of the PLL does not fit it. A novel analytical linear model for the binary type CDR circuit is addressed. Then a CDR circuit that conforms to the SONET OC-192 jitter requirements is designed by it. The CDR circuit is fabricated in TSMC 0.35μm BiCMOS process and its operation voltage is 3.3V. The architecture of it is fully differential and the output frequency range covers that of various communication standards around 10Gb/s. Finally, the jitter bandwidth is 4.18MHz, jitter peaking is 0dB, and the jitter generation is about 5ps. The jitter performances of it suit the OC-192 jitter requirements and its power consumption is 589.1mW.

碩士
臺灣大學
電子工程學研究所
97
In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clock Network Synthesis Contest as the ma jor optimization objective to measure the effects of process variation on clock-tree synthesis. In this thesis, we propose a framework which effectively constructs a clock tree by performing blockage-avoiding buffer insertion with CLR minimization. For practical considerations of clock tree synthesis, our strategy ensures that the construction satisfies the slew rate and resource usage constraint which is established by SPICE simulations. Experimental results show that our framework with the clock tree construction algorithm achieves the best average quality for CLR and the least running time, compared to all the participating teams for the 2009 ISPD Clock Network Synthesis Contest.

碩士
中原大學
資訊工程研究所
102
In the clock network synthesis, the power consumption of the clock mesh is higher than the power consumption of the clock tree, and non-uniform clock mesh and clock gating are two commonly techniques to reduce dynamic power. Non-uniform clock mesh can reduce wire length, and clock gating can reduce dynamic power consumption. In this paper, under both the enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance. In comparison with no clock gating in the non-uniform clock mesh and with clock gating in the uniform clock mesh is applied, experimental results show that our methodology can get feasible solution and reduce the switching capacitance efficiently.

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.