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Journal articles on the topic 'Circuit booléen'
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1
Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.
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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.
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Matrosova, Angela Yu, Victor A. Provkin, and Valentina V. Andreeva. "Masking of Internal Nodes Faults Based on Applying of Incompletely Specified Boolean Functions." Izvestiya of Saratov University. New Series. Series: Mathematics. Mechanics. Informatics 20, no. 4 (2020): 517–26. http://dx.doi.org/10.18500/1816-9791-2020-20-4-517-526.
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Combinational circuits (combinational parts of sequential circuits) are considered. Masking of internal nodes faults with applying sub-circuit, inputs of which are connected to the circuit inputs and outputs — to the circuit proper internal nodes, is suggested. The algorithm of deriving incompletely specified Boolean function for an internal node of the circuit based on using operations on ROBDDs is described. Masking circuit (patch circuit) design for the given internal fault nodes is reduced to covering of the system of incompletely specified Boolean functions corresponding to the fault nodes by the proper SoP system. Then the obtained system of completely specified Boolean functions is applied to derive masking circuit by using ABC system (A System for Sequential Synthesis and Verification). Experiments on bench marks show essential cutting of overhead in the frame of the suggested approach.
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Limaye, Nutan, Srikanth Srinivasan, and Sébastien Tavenas. "Superpolynomial Lower Bounds Against Low-Depth Algebraic Circuits." Communications of the ACM 67, no. 2 (2024): 101–8. http://dx.doi.org/10.1145/3611094.
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An Algebraic Circuit for a multivariate polynomial P is a computational model for constructing the polynomial P using only additions and multiplications. It is a syntactic model of computation, as opposed to the Boolean Circuit model, and hence lower bounds for this model are widely expected to be easier to prove than lower bounds for Boolean circuits. Despite this, we do not have superpolynomial lower bounds against general algebraic circuits of depth 3 (except over constant-sized finite fields) and depth 4 (over any field other than F 2 ), while constant-depth Boolean circuit lower bounds have been known since the early 1980s. In this paper, we prove the first superpolynomial lower bounds against algebraic circuits of all constant depths over all fields of characteristic 0. We also observe that our super-polynomial lower bound for constant-depth circuits implies the first deterministic sub-exponential time algorithm for solving the Polynomial Identity Testing (PIT) problem for all small-depth circuits using the known connection between algebraic hardness and randomness.
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Borodina, Yulia V. "Easily testable circuits in Zhegalkin basis in the case of constant faults of type “1” at gate outputs." Discrete Mathematics and Applications 30, no. 5 (2020): 303–6. http://dx.doi.org/10.1515/dma-2020-0026.
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AbstractWe consider Boolean circuits in Zhegalkin basis and describe all Boolean functions that can be implemented by a circuit admitting a complete fault detection test of length 1 in case of constant faults of type “1” at gate outputs.
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Agrawal, Nishant. "Automatic Test Pattern Generation using Grover’s Algorithm." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 2373–79. http://dx.doi.org/10.22214/ijraset.2021.34837.
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Quantum computing is an exciting new field in the intersection of computer science, physics and mathematics. It refines the central concepts from Quantum mechanics into its least difficult structures, peeling away the complications from the physical world. Any combinational circuit that has only one stuck at fault can be tested by applying a set of inputs that drive the circuit to verify the output response. The outputs of that circuit will be different from the one desired if the faults exist. This project describes a method of generating test patterns using the Boolean satisfaction method. First, the Boolean formula is constructed to express the Boolean difference between a fault-free circuit and a faulty circuit. Second, the Boolean satisfaction algorithm is applied to the formula in the previous step. The Grover algorithm is used to solve the Boolean satisfaction problem. The Boolean Satisfiability problem for Automatic Test Pattern Generation(ATPG) is implemented on IBM Quantum Experience. The Python program initially generates the boolean expression from the file and converts it into Conjunctive Normal Form(CNF) which is passed on to Grover Oracle and runs on IBM simulator and produces excellent results on combinational circuits for test pattern generation with a quadratic speedup. Grover’s Algorithm on this problem has a run time of O(√N).
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Li, Hongtao, Chunbiao Li, Zeshi Yuan, Wen Hu, and Xiaochen Zhen. "A New Class of Chaotic Circuit with Logic Elements." Journal of Circuits, Systems and Computers 24, no. 09 (2015): 1550136. http://dx.doi.org/10.1142/s0218126615501364.
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When signum operation is applied in chaotic systems to realize piecewise-linearity, the original nonlinearity turns to be a kind of Boolean calculation, and correspondingly the chaotic circuit can be implemented by an analog structure embedded with some logic-gate circuits. In this paper, as examples based on the diffusionless Lorenz system we proposed a couple of chaotic flows with signum piecewise-linearity, which experimentally resorts to digital gate circuits. The experimental chaotic circuit with logic elements was built, and the oscillation in the physical circuit agrees well with the numerical simulation.
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Prihozhy, Anatoly A. "Synthesis of quantum circuits based on incompletely specified functions and if-decision diagrams." Journal of the Belarusian State University. Mathematics and Informatics, no. 3 (December 14, 2021): 84–97. http://dx.doi.org/10.33581/2520-6508-2021-3-84-97.
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The problem of synthesis and optimisation of logical reversible and quantum circuits from functional descriptions represented as decision diagrams is considered. It is one of the key problems being solved with the aim of creating quantum computing technology and quantum computers. A new method of stepwise transformation of the initial functional specification to a quantum circuit is proposed, which provides for the following project states: reduced ordered binary decision diagram, if-decision diagram, functional if-decision diagram, reversible circuit and quantum circuit. The novelty of the method consists in extending the Shannon and Davio expansions of a Boolean function on a single variable to the expansions of the same Boolean function on another function with obtaining decomposition products that are represented by incompletely defined Boolean functions. Uncertainty in the decomposition products gives remarkable opportunities for minimising the graph representation of the specified function. Instead of two outgoing branches of the binary diagram vertex, three outgoing branches of the if-diagram vertex are generated, which increase the level of parallelism in reversible and quantum circuits. For each transformation step, appropriate mapping rules are proposed that reduce the number of lines, gates and the depth of the reversible and quantum circuit. The comparison of new results with the results given by the known method of mapping the vertices of binary decision diagram into cascades of reversible and quantum gates shows a significant improvement in the quality of quantum circuits that are synthesised by the proposed method.
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YOUNES, AHMED. "REDUCING QUANTUM COST OF REVERSIBLE CIRCUITS FOR HOMOGENEOUS BOOLEAN FUNCTIONS." Journal of Circuits, Systems and Computers 19, no. 07 (2010): 1423–34. http://dx.doi.org/10.1142/s0218126610006736.
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Homogeneous Boolean functions have many applications in computing systems, e.g., cryptography. This paper presents a factorization algorithm for reducing the quantum cost of the reversible circuits for that class of Boolean functions. The algorithm reduces the multi-calculation of any common parts of the circuit. This allows Homogeneous Boolean related applications to be implemented efficiently on novel computing paradigms such as quantum computers and low power devices.
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Hou, Yue Wei, Xin Xu, Wei Wang, Xiao Bo Tian, and Hai Jun Liu. "Titanium Oxide Memristor Based Digital Encoder Circuit." Applied Mechanics and Materials 644-650 (September 2014): 3430–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3430.
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Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.
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Bardales, Andrea C., Quynh Vo, and Dmitry M. Kolpashchikov. "Singleton {NOT} and Doubleton {YES; NOT} Gates Act as Functionally Complete Sets in DNA-Integrated Computational Circuits." Nanomaterials 14, no. 7 (2024): 600. http://dx.doi.org/10.3390/nano14070600.
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A functionally complete Boolean operator is sufficient for computational circuits of arbitrary complexity. We connected YES (buffer) with NOT (inverter) and two NOT four-way junction (4J) DNA gates to obtain IMPLY and NAND Boolean functions, respectively, each of which represents a functionally complete gate. The results show a technological path towards creating a DNA computational circuit of arbitrary complexity based on singleton NOT or a combination of NOT and YES gates, which is not possible in electronic computers. We, therefore, concluded that DNA-based circuits and molecular computation may offer opportunities unforeseen in electronics.
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Popkov, Kirill A. "Lower bounds for lengths of single tests for Boolean circuits." Discrete Mathematics and Applications 29, no. 1 (2019): 23–33. http://dx.doi.org/10.1515/dma-2019-0004.
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Abstract We obtain nontrivial lower bounds for lengths of minimal single fault detection and diagnostic tests for Boolean circuits in wide classes of bases in presence of stuck-at faults at outputs of circuit gates.
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Mondal, Joyati, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, and Debesh Kumar Das. "Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits." Journal of Circuits, Systems and Computers 28, no. 12 (2019): 1950212. http://dx.doi.org/10.1142/s0218126619502128.
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Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates. One example of reversible gate is Toffoli gate. A Toffoli gate (also known as [Formula: see text]-CNOT) has two components — the control and the target. Initially, stuck-at fault and other fault models were used for modeling defects in quantum reversible circuits. Later, a new fault model known as missing gate fault model was introduced, which is more effective in capturing the errors in quantum reversible circuit. Boolean Difference is already a known technique to detect stuck-at faults in conventional CMOS circuit. In this paper, Boolean Difference method is applied to derive the test set for detecting each stuck-at fault and missing gate fault in a reversible circuit. Then an optimization algorithm is used to derive an optimal test set, which will detect all possible faults in a circuit. The method is valid also for other fault models.
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Khan, Wilayat, Farrukh Aslam Khan, Abdelouahid Derhab, and Adi Alhudhaif. "CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover." Complexity 2021 (May 25, 2021): 1–12. http://dx.doi.org/10.1155/2021/5525539.
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Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of two circuits; however, this requires human effort and expertise to write multiple output functions and carry out interactive proof of their equivalence. In this paper, we (1) define two simple, one formal and the other informal, gate-level hardware description languages, (2) design and develop a formal automatic combinational circuit equivalence checker (CoCEC) tool, and (3) test and evaluate our tool. The tool CoCEC is based on human-assisted theorem prover Coq, yet it checks the equivalence of circuit descriptions purely automatically through a human-friendly user interface. It either returns a machine-readable proof (term) of circuits’ equivalence or a counterexample of their inequality. The interface enables users to enter or load two circuit descriptions written in an easy and natural style. It automatically proves, in few seconds, the equivalence of circuits with as many as 45 variables (3.5 × 10 13 states). CoCEC has a mathematical foundation, and it is reliable, quick, and easy to use. The tool is intended to be used by digital logic circuit designers, logicians, students, and faculty during the digital logic design course.
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ROZUM, JORDAN C., and RÉKA ALBERT. "CONTROLLING THE CELL CYCLE RESTRICTION SWITCH ACROSS THE INFORMATION GRADIENT." Advances in Complex Systems 22, no. 07n08 (2019): 1950020. http://dx.doi.org/10.1142/s0219525919500206.
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Boolean models represent a drastic simplification of complex biomolecular systems, and yet accurately predict system properties, e.g., effective control strategies. Why is this? Parameter robustness has been highlighted as a general feature of biomolecular systems and may play an important role in the accuracy of Boolean models. We argue here that a useful way to view a system’s controllability properties is through its repertoire of self-sustaining positive circuits (stable motifs). We examine attractor control and self-sustaining circuits within the cell cycle restriction switch, a bistable regulatory circuit that allows or prevents entry into the cell cycle. We explore this system using three models: a previously published Boolean model, a Hill kinetics model that we construct from the Boolean model using the HillCube methodology, and a reaction-based model we construct from the literature. We highlight the robustness of stable motifs across these three levels of modeling detail. We also show how consideration of control-robust regulatory circuits can aid in parameter specification.
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Redkin, Nikolay P. "The generalized complexity of linear Boolean functions." Discrete Mathematics and Applications 30, no. 1 (2020): 39–44. http://dx.doi.org/10.1515/dma-2020-0004.
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AbstractWe study generalized (in terms of bases) complexity of implementation of linear Boolean functions by Boolean circuits in arbitrary functionally complete bases; the complexity of a circuit is defined as the number of gates. Let L*(n) be the minimal number of gates sufficient for implementation of an arbitrary linear Boolean function of n variables in an arbitrary functionally complete basis. We show that L*(0) = L*(1) = 3 and L*(n) = 7(n – 1) for any natural n ≥ 2.
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Liu, Hui, Fukun Li, and Yilin Fan. "Optimizing the Quantum Circuit for Solving Boolean Equations Based on Grover Search Algorithm." Electronics 11, no. 15 (2022): 2467. http://dx.doi.org/10.3390/electronics11152467.
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The solution of nonlinear Boolean equations in a binary field plays a crucial part in cryptanalysis and computational mathematics. To speed up the process of solving Boolean equations is an urgent task that needs to be addressed. In this paper, we propose a method for solving Boolean equations based on the Grover algorithm combined with preprocessing using classical algorithms, optimizing the quantum circuit for solving the equations, and implementing the automatic generation of quantum circuits. The method first converted Boolean equations into Boolean expressions to construct the oracle in the Grover algorithm. The quantum circuit was emulated based on the IBM Qiskit framework and then simulated the Grover algorithm on this basis. Finally, the solution of the Boolean equation was implemented. The experimental results proved the feasibility of using the Grover algorithm to solve nonlinear Boolean equations in a binary field, and the correct answer was successfully found under the conditions that the search space was 221 and three G iterations were used. The method in this paper increases the solving scale and solving speed of Boolean equations and enlarges the application area of the Grover algorithm.
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Lozhkin, Sergei A., and Vadim S. Zizov. "Asymptotically sharp estimates for the area of multiplexers in the cellular circuit model." Discrete Mathematics and Applications 34, no. 2 (2024): 103–15. http://dx.doi.org/10.1515/dma-2024-0009.
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Abstract A general cellular circuit of functional and switching elements (CCFSE) is a mathematical model of integral circuits (ICs), which takes into account peculiarities of their physical synthesis. A principal feature of this model distinguishing it from the well-known classes of circuits of gates (CGs) is the presence of additional requirements on the geometry of the circuit which ensure the accounting of the necessary routing resources for IC creation. The complexity of implementation of a multiplexer function of Boolean algebra (FBA) in different classes of circuits has been extensively studied. In the present paper, we give asymptotically sharp upper and lower estimates for the area of a CCFSE implementing a multiplexer FBA of order n. We construct a family of circuit multiplexers of order n of area equal to the halved upper estimate, and provide a method of delivering the corresponding lower estimate.
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Steinbach, Bernd, and Christian Posthoff. "Compact XOR-bi-decomposition for lattices of Boolean functions." Facta universitatis - series: Electronics and Energetics 31, no. 2 (2018): 223–40. http://dx.doi.org/10.2298/fuee1802223s.
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Bi-Decomposition is a powerful approach for the synthesis of multi-level combinational circuits because it utilizes the properties of the given functions to find small circuits, with low power consumption and low delay. Compact bi-decompositions restrict the variables in the support of the decomposition functions as much as possible. Methods to find compact AND-, OR-, or XOR-bi-decompositions for a given completely specified function are well known. Lattices of Boolean Functions significantly increase the possibilities to synthesize a minimal circuit. However, so far only methods to find compact AND- or OR-bi-decompositions for lattices of Boolean functions are known. This gap, i.e., a method to find a compact XOR-bi-decomposition for a lattice of Boolean functions, has been closed by the approach suggested in this paper.
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Sapozhnikov, Valeriy, Vladimir Sapozhnikov, Dmitriy Efanov, and Dmitriy Pyvovarov. "Application of constant-weight code "1-out-if-5" for the organization of combinational circuits check." Proceedings of Petersburg Transport University, no. 2 (June 20, 2017): 307–19. http://dx.doi.org/10.20295/1815-588x-2017-2-307-319.
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Objective: To study specificities of “1-out of-5”equilibrium code application in the process of concurrent error detection of combinational logic circuits organization. Methods: Information and coding theories, as well as technical diagnostics of discrete systems were applied. Results: It was suggested to apply a “1-out of-5”equilibrium code in organizing of combinational circuits control by means of Boolean complement method, the tester of which has a simple structure and needs five testing patterns for its full check. The calculation method of Boolean complement functions was given; the former makes it possible to provide testability of a Boolean complement block and a tester within a checking circuit. The advantages of a “1-out of-5”equilibrium code application were presented, compared to the usage of other equilibrium codes with a shorter length of a code word for organization of combinational circuits’ check. Practical importance: The application of a “1-out of-5”equilibrium code for organization of combinational circuits’ check is promising for self-checking discrete automatic and calculating machines.
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Fan, Austen Z., Paraschos Koutris, and Hangdong Zhao. "Tight Bounds of Circuits for Sum-Product Queries." Proceedings of the ACM on Management of Data 2, no. 2 (2024): 1–20. http://dx.doi.org/10.1145/3651588.
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In this paper, we ask the following question: given a Boolean Conjunctive Query (CQ), what is the smallest circuit that computes the provenance polynomial of the query over a given semiring? We answer this question by giving upper and lower bounds. Notably, it is shown that any circuit F that computes a CQ over the tropical semiring must have size log |F| ≥ (1-ε) · da-entw for any ε >0, where da-entw is the degree-aware entropic width of the query. We show a circuit construction that matches this bound when the semiring is idempotent. The techniques we use combine several central notions in database theory: provenance polynomials, tree decompositions, and disjunctive Datalog programs. We extend our results to lower and upper bounds for formulas (i.e., circuits where each gate has outdegree one), and to bounds for non-Boolean CQs.
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Efanov, Dmitriy, and Eseniya Elina. "Study of algorithms for synthesis of self-checking digital devices based on Boolean correction of signals using weighted Bose – Lin codes." Transport automation research 10, no. 1 (2024): 74–99. http://dx.doi.org/10.20295/2412-9186-2024-10-01-74-99.
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When synthesizing self-checking digital devices based on Boolean correction of signals, it is proposed to use weight-based Bose – Lin codes, the construction principles of which imply preliminary weighting of data symbols by natural numbers. Two “basic” structures are proposed for the synthesis of built-in control circuits for groups of six outputs of the diagnostic object. The structures are based on weight-based Bose – Lin codes with summation in the residue ring modulo M=4. There are 15 such noise-protected codes with the number of data symbols m=4, which allows to select the best option as a base code in the builtin control circuit according to various criteria, including achieving self-checking properties even in cases where this cannot be achieved using traditional approaches, including duplication. Two algorithms for the synthesis of built-in control circuits based on Boolean signal correction have been developed, allowing the use of correction of only two of the six functions in the basic structure. For basic structures, there are 720 ways to construct an integrated control circuit based on Boolean correction of signals using each weight-based Bose – Lin code, which makes it possible to choose the best way to implement a self-checking device, considering various indicators (structural redundancy, testability, etc.). The operation of the algorithms is demonstrated on simple examples. The results of experiments with test digital circuits from the MCNC Benchmars set confirming the efficiency of the developed algorithms are given. It is shown that with a large number of outputs, there is an astronomical number of ways to organize built-in control circuits, which makes it possible to build self-checking devices with various characteristics. The use of Boolean correction of signals using weight-based Bose – Lin codes can be used in the development and design of self-checking digital devices on various element bases.
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Rushdi, Ali Muhammad Ali, and Waleed Ahmad. "Digital Circuit Design Utilizing Equation Solving over ‘Big’ Boolean Algebras." International Journal of Mathematical, Engineering and Management Sciences 3, no. 4 (2018): 404–28. http://dx.doi.org/10.33889/ijmems.2018.3.4-029.
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A task frequently encountered in digital circuit design is the solution of a two-valued Boolean equation of the form h(X,Y,Z)=1, where h: B_2^(k+m+n)→ B_2 and X,Y, and Z are binary vectors of lengths k, m, and n, representing inputs, intermediary values, and outputs, respectively. The resultant of the suppression of the variables Y from this equation could be written in the form g(X,Z)=1 where g: B_2^(k+n)→ B_2. Typically, one needs to solve for Z in terms of X, and hence it is unavoidable to resort to ‘big’ Boolean algebras which are finite (atomic) Boolean algebras larger than the two-valued Boolean algebra. This is done by reinterpreting the aforementioned g(X,Z) as g(Z): B_(2^K)^n→ B_(2^K ), where B_(2^K ) is the free Boolean algebra FB(X_1,X_2…….X_k ), which has K= 2^k atoms, and 2^K elemnets. This paper describes how to unify many digital specifications into a single Boolean equation, suppress unwanted intermediary variables Y, and solve the equation g(Z)=1 for outputs Z (in terms of inputs X) in the absence of any information about Y. The paper uses a novel method for obtaining the parametric general solutions of the ‘big’ Boolean equation g(Z)=1. The parameters used do not belong to B_(2^K ) but they belong to the two-valued Boolean algebra B_2, also known as the switching algebra or propositional algebra. To achieve this, we have to use distinct independent parameters for each asserted atom in the Boole-Shannon expansion of g(Z). The concepts and methods introduced herein are demonsrated via several detailed examples, which cover the most prominent type among basic problems of digital circuit design.
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Yasmin, Rojoba, and Russell Deaton. "Logical computation with self-assembling electric circuits." PLOS ONE 17, no. 12 (2022): e0278033. http://dx.doi.org/10.1371/journal.pone.0278033.
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Inspired by self-assembled biological growth, the Circuit Tile Assembly Model (cTAM) was developed to provide insights into signal propagation, information processing, and computation in bioelectric networks. The cTAM is an abstract model that produces a family of circuits of different sizes that is amenable to exact analysis. Here, the cTAM is extended to the Boolean Circuit Tile Assembly Model (bcTAM) that implements a computationally complete set of Boolean gates through self-assembled and self-controlled growth. The proposed model approximates axonal growth in neural networks and thus, investigates the computational capability of dynamic biological networks, for example, in growing networks of axons. Thus, the bcTAM models the effect of electrical activity on growth and shows how that growth might implement Boolean computations. In this sense, given a set of input voltages, the bcTAM is a system that is able to monitor and make decisions about its own growth.
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Illner, Petr, and Petr Kučera. "A Compiler for Weak Decomposable Negation Normal Form." Proceedings of the AAAI Conference on Artificial Intelligence 38, no. 9 (2024): 10562–70. http://dx.doi.org/10.1609/aaai.v38i9.28926.
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This paper integrates weak decomposable negation normal form (wDNNF) circuits, introduced by Akshay et al. in 2018, into the knowledge compilation map. This circuit type generalises decomposable negation normal form (DNNF) circuits in such a way that they allow a restricted form of sharing variables among the inputs of a conjunction node. We show that wDNNF circuits have the same properties as DNNF circuits regarding the queries and transformations presented in the knowledge compilation map, whilst being strictly more succinct than DNNF circuits (that is, they can represent Boolean functions compactly). We also present and evaluate a knowledge compiler, called Bella, for converting CNF formulae into wDNNF circuits. Our experiments demonstrate that wDNNF circuits are suitable for configuration instances.
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Chen, Bor-Sen, Chih-Yuan Hsu, and Jing-Jia Liou. "Robust Design of Biological Circuits: Evolutionary Systems Biology Approach." Journal of Biomedicine and Biotechnology 2011 (2011): 1–14. http://dx.doi.org/10.1155/2011/304236.
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Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are givenin silicowith the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise.
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Bibilo, P. N., and V. I. Romanov. "Experimental Study of Algorithms for Minimization of Binary Decision Diagrams using Algebraic Representations of Cofactors." Programmnaya Ingeneria 13, no. 2 (2022): 51–67. http://dx.doi.org/10.17587/prin.13.51-67.
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BDD (Binary Decision Diagram) is used for technology-independent optimization, performed as the first stage in the synthesis of logic circuits in the design of ASIC (application-specific integrated circuit). BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph is associated with the complete or reduced Shannon expansion formula. Binary decision diagrams with mutually inverse subfunctions (cofac-tors) are considered. We have developed algorithms for finding algebraic representations of cofactors of the same BDD level in the form of a disjunction or conjunction of other inverse or non-inverse cofactors of the same BDD level. The algorithms make it possible to reduce the number of literals by replacing the Shannon expansion formulas with simpler logical formulas and to reduce the number of literals in the description of a system of Boolean functions. We propose to use the developed algorithms for an additional logical optimization of the constructed BDD representations of systems of Boolean functions. Experimental results of the application of the corresponding programs in the synthesis of logic circuits in the design library of custom VLSI CMOS circuits are presented.
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Bibilo, P. N. "Synthesis of Modular Multipliers." Programmnaya Ingeneria 14, no. 8 (2023): 377–87. http://dx.doi.org/10.17587/prin.14.377-387.
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The results of experiments on the circuit implementation of modular multipliers in the design library of ASIC (Application-Specific Integrated Circuits) and FPGA (Field-Programmable Gate Array) are presented. The initial descriptions of modular multiplier projects were given by systems of not fully defined (partial) Boolean functions and algorithmic VHDL descriptions. Logical optimization was carried out in the class of disjunctive normal forms (DNF) and representations of Boolean function systems by BDD (Binary Decision Diagrams). The synthesized circuits were evaluated by area and time delay. It is established that the use of partial Boolean function models and preliminary logical BDD optimization allows one to improve the parameters of synthesized ASIC and FPGA blocks for small module values, however, the best solutions for large module values can be obtained using algorithmic VHDL descriptions of modular multipliers. In the synthesis of modular multiplier circuits as part of an FPGA and the use of ISE and Vivado design systems it is advisable to use synthesized VHDL operations (a*b) mod p.
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Banik, Subhadeep, and Francesco Regazzoni. "Compact Circuits for Efficient Möbius Transform." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 2 (2024): 481–521. http://dx.doi.org/10.46586/tches.v2024.i2.481-521.
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The Möbius transform is a linear circuit used to compute the evaluations of a Boolean function over all points on its input domain. The operation is very useful in finding the solution of a system of polynomial equations over GF(2) for obvious reasons. However the operation, although linear, needs exponential number of logic operations (around n · 2n−1 bit xors) for an n-variable Boolean function. As such, the only known hardware circuit to efficiently compute the Möbius Transform requires silicon area that is exponential in n. For Boolean functions whose algebraic degree is bound by some parameter d, recursive definitions of the Möbius Transform exist that requires only O(nd+1) space in software. However converting the mathematical definition of this space-efficient algorithm into a hardware architecture is a non-trivial task, primarily because the recursion calls notionally lead to a depth-first search in a transition graph that requires context switches at each recursion call for which straightforward mapping to hardware is difficult. In this paper we look to overcome these very challenges in an engineering sense. We propose a space efficient sequential hardware circuit for the Möbius Transform that requires only polynomial circuit area (i.e. O(nd+1)) provided the algebraic degree of the Boolean function is limited to d. We show how this circuit can be used as a component to efficiently solve polynomial equations of degree at most d by using fast exhaustive search. We propose three different circuit architectures for this, each of which uses the Möbius Transform circuit as a core component. We show that asymptotically, all the solutions of a system of m polynomials in n unknowns and algebraic degree d over GF(2) can be found using a circuit of silicon area proportional to m · nd+1 and circuit depth proportional to 2 · log2(n − d).In the second part of the paper we introduce a fourth hardware solver that additionally aims to achieve energy efficiency. The main idea is to reduce the solution space to a small enough value by parallel application of Möbius Transform circuits over the first few equations of the system. This is done so that one can check individually whether the vectors of this reduced solution space satisfy each of the remaining equations of the system using lower power consumption. The new circuit has area also bound by m · nd+1 and has circuit depth proportional to d · log2 n. We also show that further optimizations with respect to energy consumption may be obtained by using depth-bound Möbius circuits that exponentially decrease run time at the cost of additional logic area and depth.
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Datta, Rajesh Kumar. "CVM: Crossbar-based Circuit Verification through Modeling." Indian Journal of VLSI Design 3, no. 2 (2023): 1–4. http://dx.doi.org/10.54105/ijvlsid.b1219.093223.
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The implementation of Boolean functions using Nano crossbar-based switching lattices has been suggested as a substitute for conventional CMOS-based approaches in digital circuits. This alternative may satisfy the needs of future electronic designs, considering the expected end of Moore’s law. This study introduces CVM, a Crossbar-based circuit Verification through Modeling technique.
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Bach, Bao Gia, Akash Kundu, Tamal Acharya, and Aritra Sarkar. "Visualizing Quantum Circuit Probability: Estimating Quantum State Complexity for Quantum Program Synthesis." Entropy 25, no. 5 (2023): 763. http://dx.doi.org/10.3390/e25050763.
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This work applies concepts from algorithmic probability to Boolean and quantum combinatorial logic circuits. The relations among the statistical, algorithmic, computational, and circuit complexities of states are reviewed. Thereafter, the probability of states in the circuit model of computation is defined. Classical and quantum gate sets are compared to select some characteristic sets. The reachability and expressibility in a space-time-bounded setting for these gate sets are enumerated and visualized. These results are studied in terms of computational resources, universality, and quantum behavior. The article suggests how applications like geometric quantum machine learning, novel quantum algorithm synthesis, and quantum artificial general intelligence can benefit by studying circuit probabilities.
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Berndt, Augusto André Souza, Brunno Abreu, Isac S. Campos, et al. "CGP-based Logic Flow: Optimizing Accuracy and Size of Approximate Circuits." Journal of Integrated Circuits and Systems 17, no. 1 (2022): 1–12. http://dx.doi.org/10.29292/jics.v17i1.546.
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Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Machine learning techniques show high performance in solving specific problems, being an attractive option to improve electronic design tools. We explore Cartesian Genetic Programming (CGP) for logic optimization of exact or approximate Boolean functions in our work. The proposed CGP-based flow receives the expected circuit behavior as a truth-table and either performs the synthesis starting from random circuits or optimizes a circuit description provided in the format of an AND-Inverter Graph. The optimization flow improves solutions found by other techniques, using them for bootstrapping the evolutionary process. We use two metrics to evaluate our CGP-based flow: (i) the number of AIG nodes or (ii) the circuit accuracy. The results obtained showed that the CGP-based flow provided at least 22.6% superior results when considering the trade-off between accuracy and size compared with two other methods that brought the best accuracy and size outcomes, respectively.
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Efanov, D. V., and M. V. Zueva. "Modified Hamming Codes in Computing Devices Technical Diagnostic Systems." Informacionnye Tehnologii 29, no. 1 (2023): 12–22. http://dx.doi.org/10.17587/it.29.12-22.
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Previously unknown error detection characteristics by types and multiplicities in modified Hamming codes code words are established. The rules for constructing this modification of Hamming codes are described. Detailed characteristic tables of codes with data vectors lengths m = 4...16 are given. The considered code's error detection properties brief analysis is given. The results obtained in the study can be effectively used in the digital computing devices with controllable structures synthesis, as well as in the self-checking concurrent error-detection (CED) circuit synthesis using the Boolean complement method. The modified Hamming codes key property is the impossibility of 100 % double error detection in all code word bits when any single and double errors that occur only in data bits are detected. That is why it is recommended, when synthesizing a CED circuit using the Boolean complement method, to convert only those functions that describe the operating functions of the diagnostic object that will form the modified Hamming code control bits, and to separate the converted and non-convertible outputs into two groups of independent outputs. The experiment results with test combinational circuits presented in the article confirm the effectiveness of their use in the CED circuit synthesis by the Boolean complement method.
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Seo, Jinyoung, Sungi Kim, Ha H. Park, Da Yeon Choi, and Jwa-Min Nam. "Nano-bio-computing lipid nanotablet." Science Advances 5, no. 2 (2019): eaau2124. http://dx.doi.org/10.1126/sciadv.aau2124.
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Using nanoparticles as substrates for computation enables algorithmic and autonomous controls of their unique and beneficial properties. However, scalable architecture for nanoparticle-based computing systems is lacking. Here, we report a platform for constructing nanoparticle logic gates and circuits at the single-particle level on a supported lipid bilayer. Our “lipid nanotablet” platform, inspired by cellular membranes that are exploited to compartmentalize and control signaling networks, uses a lipid bilayer as a chemical circuit board and nanoparticles as computational units. On a lipid nanotablet, a single-nanoparticle logic gate senses molecules in solution as inputs and triggers particle assembly or disassembly as an output. We demonstrate a set of Boolean logic operations, fan-in/fan-out of logic gates, and a combinational logic circuit such as a multiplexer. We envisage that our approach to modularly implement nanoparticle circuits on a lipid bilayer will create new paradigms and opportunities in molecular computing, nanoparticle circuits, and systems nanoscience.
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Wille, Robert, and Rolf Drechsler. "BDD-Based Synthesis of Reversible Logic." International Journal of Applied Metaheuristic Computing 1, no. 4 (2010): 25–41. http://dx.doi.org/10.4018/jamc.2010100102.
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Reversible logic became a promising alternative to traditional circuits because of its applications in emerging technologies such as quantum computing, low-power design, DNA computing, or nanotechnologies. As a result, synthesis of the respective circuits is an intensely studied topic. However, most synthesis methods are limited, because they rely on a truth table representation of the function to be synthesized. In this paper, the authors present a synthesis approach that is based on Binary Decision Diagrams (BDDs). The authors propose a technique to derive reversible or quantum circuits from BDDs by substituting all nodes of the BDD with a cascade of Toffoli or quantum gates, respectively. Boolean functions containing more than a hundred of variables can efficiently be synthesized. More precisely, a circuit can be obtained from a given BDD using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, using the proposed approach, theoretical results known from BDDs can be transferred to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
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BIRGET, JEAN-CAMILLE. "FACTORIZATIONS OF THE THOMPSON–HIGMAN GROUPS, AND CIRCUIT COMPLEXITY." International Journal of Algebra and Computation 18, no. 02 (2008): 285–320. http://dx.doi.org/10.1142/s0218196708004457.
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We consider the subgroup lpGk,1 of length preserving elements of the Thompson–Higman group Gk,1 and we show that all elements of Gk,1 have a unique lpGk,1 · Fk,1 factorization. This applies to the Thompson–Higman group Tk,1 as well. We show that lpGk,1 is a "diagonal" direct limit of finite symmetric groups, and that lpTk,1 is a k∞ Prüfer group. We find an infinite generating set of lpGk,1 which is related to reversible boolean circuits. We further investigate connections between the Thompson–Higman groups, circuits, and complexity. We show that elements of Fk,1 cannot be one-way functions. We show that describing an element of Gk,1 by a generalized bijective circuit is equivalent to describing the element by a word over a certain infinite generating set of Gk,1; word length over these generators is equivalent to generalized bijective circuit size. We give some coNP-completeness results for Gk,1 (e.g., the word problem when elements are given by circuits), and [Formula: see text]-completeness results (e.g., finding the lpGk,1 · Fk,1 factorization of an element of Gk,1 given by a circuit).
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Awwad, Mohamad. "FROM BOOLE’S LOGIC TO BOOLEAN APPLICATIONS IN COMPUTER SCIENCE." Educational Discourse: collection of scientific papers, no. 32(4) (May 5, 2021): 18–25. http://dx.doi.org/10.33930/ed.2019.5007.32(4)-2.
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The developments of an algebraic logical language of thoughts by G. Boole are considered using historical and theoretical perspectives. The technical implementations of Boolean logic in combinational circuits and in modern cryptography show strong influences of a 19th century logic on the latest technologies of computing.
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Suman, Dr J. V., and Nekkali Ramya. "Harnessing Tunnel Field-Effect Transistors for Boolean Function Implementation." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (2023): 1–13. http://dx.doi.org/10.55041/ijsrem27821.
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In the pursuit of advancing digital integrated circuits, the exploration of novel transistor technologies has become imperative. It presents a comprehensive exploration of the implementation of Boolean functions utilizing Tunnel Field-Effect Transistors (TFETs). TFETs offer unique advantages over traditional MOSFETs, such as reduced leakage current and lower power consumption, making them a promising candidate for next-generation digital circuitry.The acronym "DGTFET" typically stands for "Double Gate Tunnel Field-Effect Transistor." A Double Gate Tunnel Field-Effect Transistor is a type of transistor that has two gate electrodes instead of one, allowing for better control of the flow of electrical current. This design offers advantages in terms of improved performance, reduced leakage current, and enhanced scalability, making it suitable for advanced semiconductor applications. we also used twin double gate structures when implementing Boolean functions with Tunnel Field-Effect Transistors (TFETs) is like giving TFETs a special setup that makes them work better for making digital circuits. Keywords: Tunnel Field-Effect Transistors (TFETs),Boolean Functions,Digital Circuit Design,Low- Power Implementation,CMOS Integration
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Pashukov, Artem. "Application of Weight-Based Sum Codes at the Synthesis of Circuits for Built-in Control by Boolean Complement Method." Automation on transport 8, no. 1 (2022): 101–14. http://dx.doi.org/10.20295/2412-9186-2022-8-1-101-114.
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This work considers the application of Boolean complement method for the organization of self-checking circuits of built-in control for the devices synthesized on being Field-Programmable Gate Arrays. Review is given for the application of Boolean complement method while using various noise-resistant codes. The example is demonstrated for control circuit synthesis with Boolean complement method. Algorithm for control system synthesis by Boolean complement method with the use of weight-based sum codes by module M is formulated. As an example, weighted codes are considered with the summation of weight categories by module M = 3 and M = 4 for these purposes. The given codes have only two control categories that simplifies their application for task solution on the design of functional diagnostics system by Boolean complement method. The comparative analysis of both codes with their use in the systems with Boolean complement has been pursued. The application of Boolean complement method on the basis of weight-based sum codes for synthesis of discrete devices has been suggested.
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Elliott, Conal. "Timely Computation." Proceedings of the ACM on Programming Languages 7, ICFP (2023): 895–919. http://dx.doi.org/10.1145/3607861.
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This paper addresses the question “what is a digital circuit?” in relation to the fundamentally analog nature of actual (physical) circuits. A simple informal definition is given and then formalized in the proof assistant Agda. At the heart of this definition is the timely embedding of discrete information in temporally continuous signals. Once this embedding is defined (in constructive logic, i.e., type theory), it is extended in a generic fashion from one signal to many and from simple boolean operations (logic gates) to arbitrarily sophisticated sequential and parallel compositions, i.e., to computational circuits. Rather than constructing circuits and then trying to prove their correctness, a compositionally correct methodology maintains specification, implementation, timing, and correctness proofs at every step. Compositionality of each aspect and of their combination is supported by a single, shared algebraic vocabulary and related by homomorphisms. After formally defining and proving these notions, a few key transformations are applied to reveal the linearity of circuit timing (over a suitable semiring), thus enabling practical, modular, and fully verified timing analysis as linear maps over higher-dimensional time intervals. An emphasis throughout the paper is simplicity and generality of specification, minimizing circuit-specific definitions and proofs while highlighting a broadly applicable methodology of scalable, compositionally correct engineering through simple denotations and homomorphisms.
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Dong, Zhekang, Donglian Qi, Yufei He, Zhao Xu, Xiaofang Hu, and Shukai Duan. "Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation." International Journal of Bifurcation and Chaos 28, no. 12 (2018): 1850149. http://dx.doi.org/10.1142/s0218127418501493.
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Memristor is a novel passive electronic element with resistance-switching dynamics. Due to the threshold property and the variable conductivity of the memristive element, its composite circuits are promising for the implementation of logic operations. In this paper, a flexible logic circuit based on the threshold-type memristor and the mature complementary metal-oxide-semiconductor (CMOS) technology is designed for the realization of Boolean logic operations. Specifically, the proposed method is able to perform the NAND, AND, OR, and NOR gate operations through two phases, i.e. the writing operation and the reading operation. In such implementation, the total delay is very small especially for time-sequence inputs. Furthermore, for existing memristor-based logic implementation, a contrastive analysis with relevant computer simulations is carried out. The experimental results indicate that the proposed method is capable of realizing all basic Boolean logic operations, and some more complicated cascaded logic operations with more compact circuit structures, higher efficiency, and lower operating cost.
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Ben-Festus, B. N., M. O. Osinowo, and Ben Festus. "Design and Construction of a Digital Logic Training Module for Laboratory Experimentation." International Journal of Research and Innovation in Applied Science VIII, no. VII (2023): 93–98. http://dx.doi.org/10.51584/ijrias.2023.8511.
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A Digital Logic Trainer is used to train students on experimental verification and implementation of basic logic gates. This research work describes a digital logic training (DLT) module designed and constructed using semiconductor components such as diodes, transistors, and integrated circuits. The DLT module can be used to verify logic gate theorems including Boolean expressions, combinational logic designs and Karnaugh’s reduction techniques for a given logic circuit. The front panel of the DLT module comprises of different Boolean symbols for easy logic gates identification and operates effectively on a 5 V DC rectified from a 220 V AC power supply. The DLT module performs favourably well when compared with commercially available types and comes at a lower production cost.
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K, Alice, and Surya K. "An instance of Satisfiability Problem learnt with Instance based, Decision trees, Naive Bayes." Knowledge Transactions on Applied Machine Learning 01, no. 04 (2023): 21–30. http://dx.doi.org/10.59567/ktaml.v1.04.03.
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Though it is not recommended for mining the data sets produced by any closed-form solution, our approach is very much aiming at the standard satisfiability (SAT) or assignment problem in terms of searching for the existence of learning models and their performance using machine learning algorithms. Here we claim that we do not apply the analytical or theoretical method in the sense it is not based on conventional or well-established minimization rules or circuit synthesis in mind but the application of computational codes for prediction for the given Boolean circuits. The main objectives are to get classification on mapping Boolean literal values to some predefined functional output and to get maximum accuracy of such classifiers. Here we have enumerated the results up to 20 bits majority operator as an instance for constructing the learning models based on machine learning algorithms. The similarity and significance of the results are shown and thus it may open the possibility for extensibility and generalizability to other types of Boolean circuits. The maximum average performance is found to be 80.72% of accuracy and 74.81% of precision based on the selected set of classifiers.
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Repe, Madhavi, and Sanjay Koli. "A Solution to VLSI: Digital Circuits Design in Quantum Dot Cellular Automata Technology." International Journal of Electrical and Electronics Research 11, no. 3 (2023): 696–704. http://dx.doi.org/10.37391/ijeer.110309.
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Quantum Dot Cellular Automata is a Nano device efficient than other devices in nanotechnology for the last two decades. It is beneficial over Complementary Metal Oxide Semiconductor technology like high speed, low energy dissipation, high device density and high computation efficiency. To achieve further optimization different methods like simplifications in Boolean expressions, tile method, clocking scheme, cell placement, cell arrangement, novel input techniques, etc., are in use. These methods improve the performance metrics in terms of QCA Cells, total circuit area, delay in output, power consumption, and coplanar or multilayer layout. This paper is about the novel NOT gate layout designed with efficient parameters compared to existing NOT gates except area parameters with analysis and XOR gate and multiplexer circuits. The novel gate provides an improvement of 55% in the number of cells, polarization raised by 0.33, and an 80.77% improvement in total area. These circuits illustrate further scope in QCA circuit design efficiently. XOR circuit shows area reduction up to 0.006 μm2 with 0.5 clock cycle delay. Further optimization in XOR parameters and with this novel NOT gate researchers can optimize parameters to bring revolution and digitalization.
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Mukherjee, Shyamapada, and Suchismita Roy. "Via-Aware Dogleg Routing Using Boolean Satisfiability." Journal of Circuits, Systems and Computers 26, no. 04 (2016): 1750064. http://dx.doi.org/10.1142/s0218126617500645.
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Boolean Satisfiability (SAT)-based channel routing with via-aware pin doglegging is presented in this paper. The effect of the pin dogleg layout of connecting wires has been tested separately for input–output pins and output pins only with controlled use of vias for dogleg during detailed routing. Dogleg may reduce the channel width required for laying down all nets and hence decrease the total chip area. However, invalid selection of dogleg may increase the channel width or may identify a routable circuit as unroutable. Unwanted dogleg may also increase the use of vias (switches) required for changing the track from one to another and may create a congested area with vias. Congested via may introduce lithographic printing problem during manufacturing and power leakage problem. The proposed technique considers all these constraints to provide an optimal result and gives a compact layout for a circuit with controlled via for doglegging. The results obtained show that pin dogleg layout produces a more compact layout for connecting wires with supervised via when compared to dogleg-free routing or doglegged routing with unsupervised via for some standard benchmark circuits. It yields optimal results with reduced number of tracks in a channel and smaller chip size.
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Constantinides, G. A. "Rethinking arithmetic for deep neural networks." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, no. 2166 (2020): 20190051. http://dx.doi.org/10.1098/rsta.2019.0051.
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We consider efficiency in the implementation of deep neural networks. Hardware accelerators are gaining interest as machine learning becomes one of the drivers of high-performance computing. In these accelerators, the directed graph describing a neural network can be implemented as a directed graph describing a Boolean circuit. We make this observation precise, leading naturally to an understanding of practical neural networks as discrete functions, and show that the so-called binarized neural networks are functionally complete. In general, our results suggest that it is valuable to consider Boolean circuits as neural networks , leading to the question of which circuit topologies are promising. We argue that continuity is central to generalization in learning, explore the interaction between data coding, network topology, and node functionality for continuity and pose some open questions for future research. As a first step to bridging the gap between continuous and Boolean views of neural network accelerators, we present some recent results from our work on LUTNet, a novel Field-Programmable Gate Array inference approach. Finally, we conclude with additional possible fruitful avenues for research bridging the continuous and discrete views of neural networks. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.
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von zur Gathen, Joachim, and Gadiel Seroussi. "Boolean circuits versus arithmetic circuits." Information and Computation 91, no. 1 (1991): 142–54. http://dx.doi.org/10.1016/0890-5401(91)90078-g.
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Kumaresan, Raja Sekar, Marshal Raj, and Lakshminarayanan Gopalakrishnan. "Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology." Journal of Electrical Engineering 73, no. 1 (2022): 1–10. http://dx.doi.org/10.2478/jee-2022-0001.
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Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.
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Rahman, M. Sazadur, Adib Nahiyan, Fahim Rahman, et al. "Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks." ACM Transactions on Design Automation of Electronic Systems 26, no. 4 (2021): 1–27. http://dx.doi.org/10.1145/3444960.
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Logic locking has emerged as a promising solution to protect integrated circuits against piracy and tampering. However, the security provided by existing logic locking techniques is often thwarted by Boolean satisfiability (SAT)-based oracle-guided attacks. Criteria for successful SAT attacks on locked circuits include: (i) the circuit under attack is fully combinational, or (ii) the attacker has scan chain access. To address the threat posed by SAT-based attacks, we adopt the dynamically obfuscated scan chain (DOSC) architecture and illustrate its resiliency against the SAT attacks when inserted into the scan chain of an obfuscated design. We demonstrate, both mathematically and experimentally, that DOSC exponentially increases the resiliency against key extraction by SAT attack and its variants. Our results show that the mathematical estimation of attack complexity correlates to the experimental results with an accuracy of 95% or better. Along with the formal proof, we model DOSC architecture to its equivalent combinational circuit and perform SAT attack to evaluate its resiliency empirically. Our experiments demonstrate that SAT attack on DOSC-inserted benchmark circuits timeout at minimal test time overhead, and while DOSC requires less than 1% area and power overhead.
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Hoiriyah, Hoiriyah. "SIMULASI GERBANG DASAR LOGIKA DALAM APLIKASI." Jurnal Teknik Informatika dan Elektro 2, no. 2 (2022): 01–08. http://dx.doi.org/10.55542/jurtie.v2i2.405.
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It is no longer a secret that all science is currently developing and has technological advances that cannot be denied, especially in digital technology which is currently popular, one of which is a digital electronic system that is composed of logic gates so that it becomes a digital system formed from logic elements. the smallest is the logic gate (Logic Gate): OR, AND and NOT where the circuit work process on this logic gate uses Boolean algebra principles. In its implementation it is rather difficult to provide an understanding of logic gates manually or in theory to the public and the general public in understanding gate circuits electronics to understand the functions and uses of logic gates in electronic circuits with EWB (Electronic WorkBanch) as an electronic computer software that can be used to simulate the workings of an electronic circuit, both analog and digital. The EWB application is very helpful in providing an indirect understanding of understanding basic logic gate circuits as simulations in applications to reduce possible dangerous risks, with this application it makes it easy to know the conditions you want to design and create before implementing them in real form..
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TAYARI, MAHSHID, and MOHAMMAD ESHGHI. "DESIGN OF 3-INPUT REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Journal of Circuits, Systems and Computers 20, no. 02 (2011): 283–97. http://dx.doi.org/10.1142/s0218126611007256.
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In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order to design another Boolean function, with no need for another AND array. The proposed 3-input RPLA is programmed to design three reversible circuits, a 1-bit full adder, a 1-bit full subtractor, and a 2-to-1 line multiplexer. Five figures of merit, including number of gates, number of constant inputs, number of garbage outputs, depth and quantum cost of the circuit are considered to evaluate and compare the designs. A comparison between the proposed reversible AND arrays and the same circuit presented in previous research, against these figures of merit, shows a better performance of our proposed designs. The proposed RPLAs are also evaluated, using these five figures of merit.