Relevant bibliographies by topics / Circuit booléen

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Circuit booléen'

Author: Grafiati
Published: 1 June 2024

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Journal articles on the topic "Circuit booléen"

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Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (February 20, 2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.
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Matrosova, Angela Yu, Victor A. Provkin, and Valentina V. Andreeva. "Masking of Internal Nodes Faults Based on Applying of Incompletely Specified Boolean Functions." Izvestiya of Saratov University. New Series. Series: Mathematics. Mechanics. Informatics 20, no. 4 (2020): 517–26. http://dx.doi.org/10.18500/1816-9791-2020-20-4-517-526.

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Combinational circuits (combinational parts of sequential circuits) are considered. Masking of internal nodes faults with applying sub-circuit, inputs of which are connected to the circuit inputs and outputs — to the circuit proper internal nodes, is suggested. The algorithm of deriving incompletely specified Boolean function for an internal node of the circuit based on using operations on ROBDDs is described. Masking circuit (patch circuit) design for the given internal fault nodes is reduced to covering of the system of incompletely specified Boolean functions corresponding to the fault nodes by the proper SoP system. Then the obtained system of completely specified Boolean functions is applied to derive masking circuit by using ABC system (A System for Sequential Synthesis and Verification). Experiments on bench marks show essential cutting of overhead in the frame of the suggested approach.
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Limaye, Nutan, Srikanth Srinivasan, and Sébastien Tavenas. "Superpolynomial Lower Bounds Against Low-Depth Algebraic Circuits." Communications of the ACM 67, no. 2 (January 25, 2024): 101–8. http://dx.doi.org/10.1145/3611094.

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An Algebraic Circuit for a multivariate polynomial P is a computational model for constructing the polynomial P using only additions and multiplications. It is a syntactic model of computation, as opposed to the Boolean Circuit model, and hence lower bounds for this model are widely expected to be easier to prove than lower bounds for Boolean circuits. Despite this, we do not have superpolynomial lower bounds against general algebraic circuits of depth 3 (except over constant-sized finite fields) and depth 4 (over any field other than F 2 ), while constant-depth Boolean circuit lower bounds have been known since the early 1980s. In this paper, we prove the first superpolynomial lower bounds against algebraic circuits of all constant depths over all fields of characteristic 0. We also observe that our super-polynomial lower bound for constant-depth circuits implies the first deterministic sub-exponential time algorithm for solving the Polynomial Identity Testing (PIT) problem for all small-depth circuits using the known connection between algebraic hardness and randomness.
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Borodina, Yulia V. "Easily testable circuits in Zhegalkin basis in the case of constant faults of type “1” at gate outputs." Discrete Mathematics and Applications 30, no. 5 (October 27, 2020): 303–6. http://dx.doi.org/10.1515/dma-2020-0026.

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AbstractWe consider Boolean circuits in Zhegalkin basis and describe all Boolean functions that can be implemented by a circuit admitting a complete fault detection test of length 1 in case of constant faults of type “1” at gate outputs.
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Agrawal, Nishant. "Automatic Test Pattern Generation using Grover’s Algorithm." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 14, 2021): 2373–79. http://dx.doi.org/10.22214/ijraset.2021.34837.

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Quantum computing is an exciting new field in the intersection of computer science, physics and mathematics. It refines the central concepts from Quantum mechanics into its least difficult structures, peeling away the complications from the physical world. Any combinational circuit that has only one stuck at fault can be tested by applying a set of inputs that drive the circuit to verify the output response. The outputs of that circuit will be different from the one desired if the faults exist. This project describes a method of generating test patterns using the Boolean satisfaction method. First, the Boolean formula is constructed to express the Boolean difference between a fault-free circuit and a faulty circuit. Second, the Boolean satisfaction algorithm is applied to the formula in the previous step. The Grover algorithm is used to solve the Boolean satisfaction problem. The Boolean Satisfiability problem for Automatic Test Pattern Generation(ATPG) is implemented on IBM Quantum Experience. The Python program initially generates the boolean expression from the file and converts it into Conjunctive Normal Form(CNF) which is passed on to Grover Oracle and runs on IBM simulator and produces excellent results on combinational circuits for test pattern generation with a quadratic speedup. Grover’s Algorithm on this problem has a run time of O(√N).
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Li, Hongtao, Chunbiao Li, Zeshi Yuan, Wen Hu, and Xiaochen Zhen. "A New Class of Chaotic Circuit with Logic Elements." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550136. http://dx.doi.org/10.1142/s0218126615501364.

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When signum operation is applied in chaotic systems to realize piecewise-linearity, the original nonlinearity turns to be a kind of Boolean calculation, and correspondingly the chaotic circuit can be implemented by an analog structure embedded with some logic-gate circuits. In this paper, as examples based on the diffusionless Lorenz system we proposed a couple of chaotic flows with signum piecewise-linearity, which experimentally resorts to digital gate circuits. The experimental chaotic circuit with logic elements was built, and the oscillation in the physical circuit agrees well with the numerical simulation.
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Prihozhy, Anatoly A. "Synthesis of quantum circuits based on incompletely specified functions and if-decision diagrams." Journal of the Belarusian State University. Mathematics and Informatics, no. 3 (December 14, 2021): 84–97. http://dx.doi.org/10.33581/2520-6508-2021-3-84-97.

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The problem of synthesis and optimisation of logical reversible and quantum circuits from functional descriptions represented as decision diagrams is considered. It is one of the key problems being solved with the aim of creating quantum computing technology and quantum computers. A new method of stepwise transformation of the initial functional specification to a quantum circuit is proposed, which provides for the following project states: reduced ordered binary decision diagram, if-decision diagram, functional if-decision diagram, reversible circuit and quantum circuit. The novelty of the method consists in extending the Shannon and Davio expansions of a Boolean function on a single variable to the expansions of the same Boolean function on another function with obtaining decomposition products that are represented by incompletely defined Boolean functions. Uncertainty in the decomposition products gives remarkable opportunities for minimising the graph representation of the specified function. Instead of two outgoing branches of the binary diagram vertex, three outgoing branches of the if-diagram vertex are generated, which increase the level of parallelism in reversible and quantum circuits. For each transformation step, appropriate mapping rules are proposed that reduce the number of lines, gates and the depth of the reversible and quantum circuit. The comparison of new results with the results given by the known method of mapping the vertices of binary decision diagram into cascades of reversible and quantum gates shows a significant improvement in the quality of quantum circuits that are synthesised by the proposed method.
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YOUNES, AHMED. "REDUCING QUANTUM COST OF REVERSIBLE CIRCUITS FOR HOMOGENEOUS BOOLEAN FUNCTIONS." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1423–34. http://dx.doi.org/10.1142/s0218126610006736.

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Homogeneous Boolean functions have many applications in computing systems, e.g., cryptography. This paper presents a factorization algorithm for reducing the quantum cost of the reversible circuits for that class of Boolean functions. The algorithm reduces the multi-calculation of any common parts of the circuit. This allows Homogeneous Boolean related applications to be implemented efficiently on novel computing paradigms such as quantum computers and low power devices.
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Hou, Yue Wei, Xin Xu, Wei Wang, Xiao Bo Tian, and Hai Jun Liu. "Titanium Oxide Memristor Based Digital Encoder Circuit." Applied Mechanics and Materials 644-650 (September 2014): 3430–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3430.

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Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.
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Bardales, Andrea C., Quynh Vo, and Dmitry M. Kolpashchikov. "Singleton {NOT} and Doubleton {YES; NOT} Gates Act as Functionally Complete Sets in DNA-Integrated Computational Circuits." Nanomaterials 14, no. 7 (March 28, 2024): 600. http://dx.doi.org/10.3390/nano14070600.

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A functionally complete Boolean operator is sufficient for computational circuits of arbitrary complexity. We connected YES (buffer) with NOT (inverter) and two NOT four-way junction (4J) DNA gates to obtain IMPLY and NAND Boolean functions, respectively, each of which represents a functionally complete gate. The results show a technological path towards creating a DNA computational circuit of arbitrary complexity based on singleton NOT or a combination of NOT and YES gates, which is not possible in electronic computers. We, therefore, concluded that DNA-based circuits and molecular computation may offer opportunities unforeseen in electronics.
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Dissertations / Theses on the topic "Circuit booléen"

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Soyez-Martin, Claire. "From semigroup theory to vectorization : recognizing regular languages." Electronic Thesis or Diss., Université de Lille (2022-....), 2023. http://www.theses.fr/2023ULILB052.

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L'évaluation efficace des expressions régulières constitue un défi persistant depuis de nombreuses décennies. Au fil du temps, des progrès substantiels ont été réalisés grâce à une variété d'approches, allant de nouveaux et ingénieux algorithmes à des optimisations complexes de bas niveau.Les outils de pointe de ce domaine utilisent ces techniques d'optimisation, et repoussent constamment les limites de leur efficacité. Une avancée notoire réside dans l'intégration de la vectorisation, qui exploite une forme de parallélisme de bas niveau pour traiter l'entrée par blocs, entraînant ainsi d'importantes améliorations de performances. Malgré une recherche approfondie sur la conception d'algorithmes sur mesure pour des tâches particulières, ces solutions manquent souvent de généralisabilité, car la méthodologie sous-jacente à ces algorithmes ne peut pas être appliquée de manière indiscriminée à n'importe quelle expression régulière, ce qui rend difficile son intégration dans les outils existants.Cette thèse présente un cadre théorique permettant de générer des programmes vectorisés particuliers capables d'évaluer les expressions régulières correspondant aux expressions rationnelles appartenant à une classe logique donnée. L'intérêt de ces programmes vectorisés vient de l'utilisation de la théorie algébrique des automates, qui offre certains outils algébriques permettant de traiter les lettres en parallèle. Ces outils permettent également d'analyser les langages réguliers plus finement, offrent accès à des optimisations des programmes vectorisés basées sur les propriétés algébriques de ces langages. Cette thèse apporte des contributions dans deux domaines. D'une part, nous présentons des implémentations et des benchmarks préliminaires, afin d'étudier les possibilités offertes par l'utilisation de l'algèbre et de la vectorisation dans les algorithmes d'évaluation des expressions régulières. D'autre part, nous proposons des algorithmes capables de générer des programmes vectorisés reconnaissant les langages appartenant à deux classes d'expressions rationnelles, la logique du premier ordre et sa restriction aux formules utilisant au plus deux variables
The pursuit of optimizing regular expression validation has been a long-standing challenge,spanning several decades. Over time, substantial progress has been made through a vast range of approaches, spanning from ingenious new algorithms to intricate low-level optimizations.Cutting-edge tools have harnessed these optimization techniques to continually push the boundaries of efficient execution. One notable advancement is the integration of vectorization, a method that leverage low-level parallelism to process data in batches, resulting in significant performance enhancements. While there has been extensive research on designing handmade tailored algorithms for particular languages, these solutions often lack generalizability, as the underlying methodology cannot be applied indiscriminately to any regular expression, which makes it difficult to integrate to existing tools.This thesis provides a theoretical framework in which it is possible to generate vectorized programs for regular expressions corresponding to rational expressions in a given class. To do so, we rely on the algebraic theory of automata, which provides tools to process letters in parallel. These tools also allow for a deeper understanding of the underlying regular language, which gives access to some properties that are useful when producing vectorized algorithms. The contribution of this thesis is twofold. First, it provides implementations and preliminary benchmarks to study the potential efficiency of algorithms using algebra and vectorization. Second, it gives algorithms that construct vectorized programs for languages in specific classes of rational expressions, namely the first order logic and its subset restricted to two variables
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Paperman, Charles. "Circuits booléens, prédicats modulaires et langages réguliers." Paris 7, 2014. http://www.theses.fr/2014PA077258.

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La conjecture de Straubing, énoncée dans son livre publié en 1994, suggère qu'un langage régulier définissable par un fragment logique équipé d'une signature arbitraire, est définissable par le même fragment logique mais équipé d'une signature régulière. Les fragments logiques considérés sont des classes de férmules de la logique monadique du second ordre sur les mots finis. Cette thèse est une contribution à l'étude de le conjecture de Straubing. Pour prouver une telle conjecture, il semble nécessaire pour établir cette conjecture de prouver deux résultats de natures différentes : 1. Des caractérisations algébriques de classes de langages réguliers définies par des fragments logiques équipés de prédicats réguliers, 2. Des résultats de non-définissabilité de langages réguliers dans des fragments logiques équipés de prédicats numériques arbitraires. La première partie de cette thèse est dédiée à l'ajout des prédicats réguliers à un fragment logique et en particulier, celui des prédicats modulaires lorsque les fragments logiques disposent de structures algébriques. La seconde partie de cette thèse est dédiée à des résultats de non définissablité, et en particulier l'étude du fragment à deux variables de la logique du premier ordre
The Straubing conjecture, stated in his book published in 1994, suggest that a regular language definable by a fragment of logic and equipped with an arbitrary numerical signature is definable using the same fragment of logic using only regular predicates. The considered fragments of logic are classed of formulas of monadic second order logic over finite words. This thesis is a contribution to the study of the Straubing conjecture. To prove such a conjecture, it seems necessary to obtain two results of two distinct types: 1. Algebraic characterizations of classes of regular languages defined by fragments of logics equipped with regular predicates, 2. Undefinability results of regular languages in fragments of logics equipped with arbitrary numerical predicates. The first part of this thesis is dedicated to the operation of adding regular predicates to a given fragment of logic, with a particular focus on modular predicates in the case where logical fragments have some algebraic structure. The second par of this thesis is dedicated to undefinability results with a particular focus on two-variable first order logic
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Daitch, Samuel Isaac. "Translating alloy using Boolean circuits." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/33129.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 71-72).
Alloy is a automatically analyzable modelling language based on first-order logic. An Alloy model can be translated into a Boolean formula whose satisfying assignments correspond to instances in the model. Currently, the translation procedure mechanically converts each piece of the Alloy model individually into its most straightforward Boolean representation. This thesis proposes a more efficient approach to translating Alloy models. The key is to take advantage of the fact that an Alloy model contains patterns that are used repeatedly. This makes it natural to give a model a more structured Boolean representation, namely a Boolean circuit. Reusable pieces in the model correspond to circuit components. By identifying the most frequently used components and optimizing their corresponding Boolean formulas, the size of the overall formula for the model would be reduced without significant additional work. A smaller formula would potentially decrease the time required to determine satisfiability, resulting in faster analysis overall.
by Samuel Isaac Daitch.
M.Eng.
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Shi, Junhao. "Boolean techniques in testing of digital circuits." [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=98361816X.

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Chattopadhyay, Arkadev. "Circuits, communication and polynomials." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=115660.

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In this thesis, we prove unconditional lower bounds on resources needed to compute explicit functions in the following three models of computation: constant-depth boolean circuits, multivariate polynomials over commutative rings and the 'Number on the Forehead' model of multiparty communication. Apart from using tools from diverse areas, we exploit the rich interplay between these models to make progress on questions arising in the study of each of them.
Boolean circuits are natural computing devices and are ubiquitous in the modern electronic age. We study the limitation of this model when the depth of circuits is fixed, independent of the length of the input. The power of such constant-depth circuits using gates computing modular counting functions remains undetermined, despite intensive efforts for nearly twenty years. We make progress on two fronts: let m be a number having r distinct prime factors none of which divides ℓ. We first show that constant depth circuits employing AND/OR/MODm gates cannot compute efficiently the MAJORITY and MODℓ function on n bits if 'few' MODm gates are allowed, i.e. they need size nW&parl0;1s&parl0;log n&parr0;1/&parl0;r-1&parr0;&parr0; if s MODm gates are allowed in the circuit. Second, we analyze circuits that comprise only MOD m gates, We show that in sub-linear size (and arbitrary depth), they cannot compute AND of n bits. Further, we establish that in that size they can only very poorly approximate MODℓ.
Our first result on circuits is derived by introducing a novel notion of computation of boolean functions by polynomials. The study of degree as a resource in polynomial representation of boolean functions is of much independent interest. Our notion, called the weak generalized representation, generalizes all previously studied notions of computation by polynomials over finite commutative rings. We prove that over the ring Zm , polynomials need Wlogn 1/r-1 degree to represent, in our sense, simple functions like MAJORITY and MODℓ. Using ideas from arguments in communication complexity, we simplify and strengthen the breakthrough work of Bourgain showing that functions computed by o(log n)-degree polynomials over Zm do not even correlate well with MODℓ.
Finally, we study the 'Number on the Forehead' model of multiparty communication that was introduced by Chandra, Furst and Lipton [CFL83]. We obtain fresh insight into this model by studying the class CCk of languages that have constant k-party deterministic communication complexity under every possible partition of input bits among parties. This study is motivated by Szegedy's [Sze93] surprising result that languages in CC2 can all be extremely efficiently recognized by very shallow boolean circuits. In contrast, we show that even CC 3 contains languages of arbitrarily large circuit complexity. On the other hand, we show that the advantage of multiple players over two players is significantly curtailed for computing two simple classes of languages: languages that have a neutral letter and those that are symmetric.
Extending the recent breakthrough works of Sherstov [She07, She08b] for two-party communication, we prove strong lower bounds on multiparty communication complexity of functions. First, we obtain a bound of n O(1) on the k-party randomized communication complexity of a function that is computable by constant-depth circuits using AND/OR gates, when k is a constant. The bound holds as long as protocols are required to have better than inverse exponential (i.e. 2-no1 ) advantage over random guessing. This is strong enough to yield lower bounds on the size of an important class of depth-three circuits: circuits having a MAJORITY gate at its output, a middle layer of gates computing arbitrary symmetric functions and a base layer of arbitrary gates of restricted fan-in.
Second, we obtain nO(1) lower bounds on the k-party randomized (bounded error) communication complexity of the Disjointness function. This resolves a major open question in multiparty communication complexity with applications to proof complexity. Our techniques in obtaining the last two bounds, exploit connections between representation by polynomials over teals of a boolean function and communication complexity of a closely related function.
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Boyd, Mark J. "Complexity analysis of a massive parallel boolean satisfiability implication circuit /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2005. http://uclibs.org/PID/11984.

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PELADEAU, PIERRE. "Classes de circuits booleens et varietes de monoides." Paris 6, 1990. http://www.theses.fr/1990PA066265.

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Ce travail porte sur l'etude de la complexite du calcul parallele dans le modele des circuits booleens et ses liens avec la classification algebrique des monoides finis. Barrington a montre qu'un langage est reconnu par une suite de circuits nc#1 ssi il est reconnu par une suite de programmes de longueur polynomiale sur un monoide fini. Ceci nous permet d'utiliser la classification algebrique des monoides finis, en termes de varietes, afin d'etudier la structure interne de la classe nc#1. Nous donnons des caracterisations algebriques detaillees des sous-classes de nc#1, reliant plus precisement la nature des portes et la profondeur des circuits a la complexite des varietes de monoides. Contrairement a la reconnaissance par morphismes, deux varietes distinctes de monoides peuvent, avec des programmes de longueur polynomiale, reconnaitre la meme classe de langages. Ceci nous amene, a travers une etude des proprietes du probleme du mot, a definir une nouvelle division entre monoides finis et une nouvelle notion de variete de monoides finis, adaptee a la reconnaissance par programmes. A l'aide de cette notion, nous demontrons que pour toutes les classes de circuits (sauf une) contenues dans nc#1, si deux classes sont separables, alors elles sont separees par un langage rationnel. Les classes de complexite a l'interieur de nc#1 ont egalement des caracterisations en logique, tout comme les langages rationnels. La seule difference est l'utilisation de predicats numeriques non-uniformes dans le cas des circuits, un predicat numerique etant un predicat qui definit un sous-ensemble de n#k. Nous demontrons qu'il existe une unique classe maximale de predicats numeriques telle que les langages, definis par des formules n'utilisant que des predicats numeriques de cette classe, sont rationnels. Ce resultat, avec les caracterisations algebriques, permet d'enoncer une conjecture tres forte concernant
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Bowen, Richard Strong. "Minimal Circuits for Very Incompletely Specified Boolean Functions." Scholarship @ Claremont, 2010. https://scholarship.claremont.edu/hmc_theses/18.

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In this report, asymptotic upper and lower bounds are given for the minimum number of gates required to compute a function which is only partially specified and for which we allow a certain amount of error. The upper and lower bounds match. Hence, the behavior of these minimum circuit sizes is completely (asymptotically) determined.
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Barato, Matteo. "Sulla Conversione di Circuiti Booleani in Circuiti Quantistici." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2018.

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Sengupta, Rimli. "Lower bounds for natural functions in restricted boolean circuits." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/8269.

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Books on the topic "Circuit booléen"

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Lam, Tak-Kei, Wai-Chung Tang, Xing Wei, Yi Diao, and David Yu-LiangWu. Boolean Circuit Rewiring. Singapore: John Wiley & Sons Singapore Pte. Ltd, 2016. http://dx.doi.org/10.1002/9781118750124.

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Stanković, Radomir S., and Jaakko Astola. From Boolean Logic to Switching Circuits and Automata. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-11682-7.

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Communication complexity: A new approach to circuit depth. Cambridge, Mass: MIT Press, 1989.

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The complexity of Boolean functions. Stuttgart: B.G. Teubner, 1987.

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Boolean functions in coding theory and cryptography. Providence, R.I: American Mathematical Society, 2012.

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Noam, Nisan, ed. Communication complexity. New York: Cambridge University Press, 1997.

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Stanković, Radomir S. From Boolean logic to switching circuits and automata: Towards modern information technology. Berlin: Springer Verlag, 2011.

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Vollmer, Heribert. Introduction to Circuit Complexity: A Uniform Approach. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999.

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Shalyto, A. A. Logicheskoe upravlenie: Metody apparatnoĭ i programmnoĭ realizat︠s︡ii algoritmov. Sankt-Peterburg: Nauka, 2000.

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Kunz, Wolfgang. Reasoning in Boolean Networks: Logic Synthesis and Verification using Testing Techniques. Boston, MA: Springer US, 1997.

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Book chapters on the topic "Circuit booléen"

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Kitaev, A., A. Shen, and M. Vyalyi. "Boolean circuits." In Graduate Studies in Mathematics, 17–27. Providence, Rhode Island: American Mathematical Society, 2002. http://dx.doi.org/10.1090/gsm/047/04.

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Hromkovič, Juraj. "Boolean Circuits." In Texts in Theoretical Computer Science An EATCS Series, 151–240. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/978-3-662-03442-2_3.

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Paterson, Mike. "Boolean circuit complexity." In Algorithms and Computation, 187. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-56279-6_71.

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Sikkel, Klaas. "Boolean circuit parsing." In Texts in Theoretical Computer Science An EATCS Series, 311–44. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/978-3-642-60541-3_14.

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Lam, William K. C., and Robert K. Brayton. "Exact Circuit Performance Validation." In Timed Boolean Functions, 189–242. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2688-9_6.

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Clote, Peter, and Evangelos Kranakis. "Circuit Lower Bounds." In Boolean Functions and Computation Models, 61–154. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/978-3-662-04943-3_2.

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Clote, Peter, and Evangelos Kranakis. "Circuit Upper Bounds." In Boolean Functions and Computation Models, 155–205. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/978-3-662-04943-3_3.

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Brown, Frank Markham. "Recursive Realizations of Combinational Circuits." In Boolean Reasoning, 211–37. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4757-2078-5_9.

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Sengupta, Rimli, and H. Venkateswaran. "Non-cancellative Boolean circuits: A generalization of monotone Boolean circuits." In Lecture Notes in Computer Science, 298–309. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-62034-6_58.

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Wallis, W. D. "Boolean Algebras and Circuits." In A Beginner’s Guide to Discrete Mathematics, 65–89. Boston, MA: Birkhäuser Boston, 2003. http://dx.doi.org/10.1007/978-1-4757-3826-1_3.

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Conference papers on the topic "Circuit booléen"

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Kombarov, Yury Anatolievich. "Improvement of circuit complexity lower bound for parity function in one infinite basis." In Academician O.B. Lupanov 14th International Scientific Seminar "Discrete Mathematics and Its Applications". Keldysh Institute of Applied Mathematics, 2022. http://dx.doi.org/10.20948/dms-2022-14.

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We consider circuits of functional elements in a basis of generalized conjunctors (that is, conjunctors with an arbitrary number of inputs, any input of which can be inverted). It is proved that any circuit that implements a linear Boolean function of n variables consists of at least 2.125n + С elements.
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Audemard, Gilles, Frédéric Koriche, and Pierre Marquis. "On Tractable XAI Queries based on Compiled Representations." In 17th International Conference on Principles of Knowledge Representation and Reasoning {KR-2020}. California: International Joint Conferences on Artificial Intelligence Organization, 2020. http://dx.doi.org/10.24963/kr.2020/86.

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One of the key purposes of eXplainable AI (XAI) is to develop techniques for understanding predictions made by Machine Learning (ML) models and for assessing how much reliable they are. Several encoding schemas have recently been pointed out, showing how ML classifiers of various types can be mapped to Boolean circuits exhibiting the same input-output behaviours. Thanks to such mappings, XAI queries about classifiers can be delegated to the corresponding circuits. In this paper, we define new explanation and/or verification queries about classifiers. We show how they can be addressed by combining queries and transformations about the associated Boolean circuits. Taking advantage of previous results from the knowledge compilation map, this allows us to identify a number of XAI queries that are tractable provided that the circuit has been first turned into a compiled representation.
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Di Crescenzo, Giovanni, Jeyavijayan Rajendran, Ramesh Karri, and Nasir Memon. "Boolean Circuit Camouflage." In CCS '17: 2017 ACM SIGSAC Conference on Computer and Communications Security. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3139324.3139331.

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Kuehlmann, Andreas, Malay K. Ganai, and Viresh Paruthi. "Circuit-based Boolean Reasoning." In the 38th conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/378239.378470.

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Craig, R. G. A., G. S. Buller, F. A. P. Tooley, H. Ichikawa, S. D. Smith, A. C. Walker, and B. S. Wherrett. "An All-Optical Programmable Logic Gate." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1989. http://dx.doi.org/10.1364/optcomp.1989.pd6.

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Experimental results are presented showing all-optical programmability and operation of a multi-function Boolean logic circuit. All eight symmetric two input logic functions have been demonstrated. Comments on the practical implementation and usage of this circuit are made.
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Yao-Hsin Chou, I-Ming Tsai, and Sy-Yen Kuo. "Quantum boolean circuit is 1-testable." In 2007 7th IEEE Conference on Nanotechnology (IEEE-NANO). IEEE, 2007. http://dx.doi.org/10.1109/nano.2007.4601419.

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Ciencialova, Lucie. "MEMBRANE AGENTS SIMULATING BOOLEAN CIRCUITS." In 17th International Multidisciplinary Scientific GeoConference SGEM2017. Stef92 Technology, 2017. http://dx.doi.org/10.5593/sgem2017/21/s07.053.

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Terui, K. "Proof nets and Boolean circuits." In Proceedings of the 19th Annual IEEE Symposium on Logic in Computer Science, 2004. IEEE, 2004. http://dx.doi.org/10.1109/lics.2004.1319612.

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Sedighi, Behnam, Joseph J. Nahas, Michael Niemier, and Xiaobo Sharon Hu. "Boolean circuit design using emerging tunneling devices." In 2014 32nd IEEE International Conference on Computer Design (ICCD). IEEE, 2014. http://dx.doi.org/10.1109/iccd.2014.6974705.

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Cavalar, Bruno Pasqualotto, and Yoshiharu Kohayakawa. "Sunflower Theorems in Monotone Circuit Complexity." In Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação, 2021. http://dx.doi.org/10.5753/ctd.2021.15761.

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Alexander Razborov (1985) developed the approximation method to obtain lower bounds on the size of monotone circuits deciding if a graph contains a clique. Given a "small" circuit, this technique consists in finding a monotone Boolean function which approximates the circuit in a distribution of interest, but makes computation errors in that same distribution. To prove that such a function is indeed a good approximation, Razborov used the sunflower lemma of Erd\H{o}s and Rado (1960). This technique was improved by Alon and Boppana (1987) to show lower bounds for a larger class of monotone computational problems. In that same work, the authors also improved the result of Razborov for the clique problem, using a relaxed variant of sunflowers. More recently, Rossman (2010) developed another variant of sunflowers, now called "robust sunflowers", to obtain lower bounds for the clique problem in random graphs. In the following years, the concept of robust sunflowers found applications in many areas of computational complexity, such as DNF sparsification, randomness extractors and lifting theorems. Even more recent was the breakthrough result of Alweiss, Lovett, Wu and Zhang (2020), which improved Rossman's bound on the size of hypergraphs without robust sunflowers. This result was employed to obtain a significant progress on the sunflower conjecture. In this work, we will show how the recent progress in sunflower theorems can be applied to improve monotone circuit lower bounds. In particular, we will show the best monotone circuit lower bound obtained up to now, breaking a 20-year old record of Harnik and Raz (2000). We will also improve the lower bound of Alon and Boppana for the clique function in a slightly more restricted range of clique sizes. Our exposition is self-contained. These results were obtained in a collaboration with Benjamin Rossman and Mrinal Kumar.
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Reports on the topic "Circuit booléen"

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Barnett, Janet Heine. Applications of Boolean Algebra: Claude Shannon and Circuit Design. Washington, DC: The MAA Mathematical Sciences Digital Library, July 2013. http://dx.doi.org/10.4169/loci004000.

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Mahooti, Rabe'eh. A CMOS circuit generator using differential pass transistors for implementing Boolean functions. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.5689.

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