Dissertations / Theses on the topic 'CIP failure'
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Michel, Kenan. "Failure Behaviour of Masonry under Compression Based on Numerical and Analytical Modeling." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191765.
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In this work the compression behavior of masonry was investigated. After a detailed review of code approaches and different research works, a new formula was suggested to describe the compression strength of masonry, based on the mechanical and geometrical properties of its components, when deformation properties of units are larger than the ones of mortar.
Later on, a new model, Extended Drucker-Prager Cap Yielding Function, is suggested to describe the three axial compression stress state of mortar in masonry in case deformation properties of mortar are larger than the ones of mortar, and to describe the three axial compression stress state of brick in the other case. This includes defining its parameters based on test diagrams of the mortar material, implementing the model in the numerical software ANSYS, and the numerical results are evaluated for simple cube example.
The controlling equations of creep based on the visco-elastic creep theory are presented in the general case of three axial creep under three axial loading conditions. The special case of three axial creep under axial loading is also presented. The “transversal creep” relevant for the compression strength of masonry was discussed and numerical examples have been added to show the effect of changed time-dependent Poisson’s ratio.
In another chapter, many examples are presented showing the application of the suggested material models and discontinuous numerical method named eXtended finite element method. Conclusions and recommendations are given in the last chapter.
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Muncy, Jennifer V. "Predictive Failure Model for Flip Chip on Board Component Level Assemblies." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5131.
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Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set.
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Tsai, Wen-Kai Mike. "High yield flip chip processing and failure mode analysis for surface mount applications." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17063.
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Beckler, Matthew Layne. "On-Chip Diagnosis of Generalized Delay Failures using Compact Fault Dictionaries." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/906.
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Integrated Circuits (ICs) are an essential part of nearly every electronic device. From toys to appliances, spacecraft to power plants, modern society truly depends on the reliable operation of billions of ICs around the world. The steady shrinking of IC transistors over past decades has enabled drastic improvements in IC performance while reducing area and power consumption. However, with continued scaling of semiconductor fabrication processes, failure sources of many types are becoming more pronounced and are increasingly affecting system operation. Additionally, increasing variation during fabrication also increases the difficulty of yielding chips in a cost-effective manner. Finally, phenomena such as early-life and wear-out failures pose new challenges to ensuring robustness. One approach for ensuring robustness centers on performing test during run-time, identifying the location of any defects, and repairing, replacing, or avoiding the affected portion of the system. Leveraging the existing design-for-testability (DFT) structures, thorough tests that target these delay defects are applied using the scan logic. Testing is performed periodically to minimize user-perceived performance loss, and if testing detects any failures, on-chip diagnosis is performed to localize the defect to the level of repair, replacement, or avoidance. In this dissertation, an on-chip diagnosis solution using a fault dictionary is described and validated through a large variety of experiments. Conventional fault dictionary approaches can be used to locate failures but are limited to simplistic fail behaviors due to the significant computational resources required for dictionary generation and memory storage. To capture the misbehaviors expected from scaled technologies, including early-life and wear-out failures, the Transition-X (TRAX) fault model is introduced. Similar to a transition fault, a TRAX fault is activated by a signal level transition or glitch, and produces the unknown value X when activated. Recognizing that the limited options for runtime recovery of defective hardware relax the conventional requirements for defect localization, a new fault dictionary is developed to provide diagnosis localization only to the required level of the design hierarchy. On-chip diagnosis using such a hierarchical dictionary is performed using a new scalable hardware architecture. To reduce the computation time required to generate the TRAX hierarchical dictionary for large designs, the incredible parallelism of graphics processing units (GPUs) is harnessed to provide an efficient fault simulation engine for dictionary construction. Finally, the on-chip diagnosis process is evaluated for suitability in providing accurate diagnosis results even when multiple concurrent defects are affecting a circuit.
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Mohammadi, Panah Mahshid. "Thermo-mechanical Analysis of Bump Joints for Packages in Flip Chip Assemblies." Thesis, Blekinge Tekniska Högskola, Institutionen för maskinteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10918.
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Oh, Yoonchan. "Multi-physics investigation on the failure mechanism and short-time scale wave motion in flip-chip configuration." Texas A&M University, 2004. http://hdl.handle.net/1969.1/2719.
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The demands for higher clock speeds and larger current magnitude in high-performance flip-chip electronic packaging configurations of small footprint have inevitably raised the concern over rapid thermal transients and large thermal spatial gradients that could severely compromise package performance. Coupled electrical-thermal-mechanical multi-physics were explored to evaluate the concern and to establish the knowledge base necessary for improving flip-chip reliability. It was found that within the first few hundred nanoseconds upon power-on, there were fast attenuating, dispersive shock waves of extremely high frequency propagating in the package. The notions of high cycle fatigue, power density and joint time-frequency analysis were employed to characterize the waves and the various failure modes associated with the moving of these short-lived dynamical disturbances in bulk materials and along interfaces. A qualitative measure for failure was also developed which enables the extent of damages inflicted by short-time wave propagation to be calculated in the probability sense. Failure modes identified in this study are all in agreement with what have been observed in industry. This suggests that micron cracks or interfacial flaws initiated at the short-time scale would be further propagated by the CTE-induced thermal stresses at the long-time scale and result in eventual electrical disruptions.
Although epoxy-based underfills with fillers were shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity was found to be insignificant in attenuating short-time scale wave propagation. On the other hand, the inclusion of Cu interconnecting layers in flip-chips was shown to perform significantly better than Al layers in suppressing short-time scale effects. These results imply that, if improved flip-chip reliability is to be achieved, all packaging constituent materials need to be formulated to have well-defined short-time scale and long-time scale properties. In addition, the results also suggest that the composition and layout of all packaging components be optimized to achieve discouraging or suppressing short-time scale dynamic effects. In summary, results reported herein and numerical procedures developed for the research would not just render higher packaging manufacturing yield, but also bring out significant impact on packaging development, packaging material formulation and micro-circuit layout design.
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Tambara, Lucas Antunes. "Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/164461.
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O recente avanço da indústria de semicondutores tem possibilitado a integração de componentes complexos e arquiteturas de sistemas dentro de um único chip de silício. Atualmente, FPGAs do estado da arte incluem, não apenas a matriz de lógica programável, mas também outros blocos de hardware, como processadores de propósito geral, blocos de processamento dedicado, interfaces para vários periféricos, estruturas de barramento internas ao chip, e blocos analógicos. Estes novos dispositivos são comumente chamados de Sistemasem-Chip Totalmente Programáveis (APSoCs). Uma das maiores preocupações acerca dos efeitos da radiação em APSoCs é o fato de que erros induzidos pela radiação podem ter diferente probabilidade e criticalidade em seus blocos de hardware heterogêneos, em ambos os níveis de dispositivo e projeto. Por esta razão, este trabalho realiza uma investigação profunda acerca dos efeitos da radiação em APSoCs e da correlação entre a sensibilidade de recursos de hardware e software na performance geral do sistema. Diversos experimentos estáticos e dinâmicos inéditos foram realizados nos blocos de hardware de um APSoC a fim de melhor entender as relações entre confiabilidade e performance de cada parte separadamente. Os resultados mostram que há um comprometimento a ser analisado entre o desempenho e a área de choque de um projeto durante o desenvolvimento de um sistema em um APSoC. Desse modo, é fundamental levar em consideração cada opção de projeto disponível e todos os parâmetros do sistema envolvidos, como o tempo de execução e a carga de trabalho, e não apenas a sua seção de choque. Exemplificativamente, os resultados mostram que é possível aumentar o desempenho de um sistema em até 5.000 vezes com um pequeno aumento na sua seção de choque de até 8 vezes, aumentando assim a confiabilidade operacional do sistema. Este trabalho também propõe um fluxo de análise de confiabilidade baseado em injeções de falhas para estimar a tendência de confiabilidade de projetos somente de hardware, de software, ou de hardware e software. O fluxo objetiva acelerar a procura pelo esquema de projeto com a melhor relação entre performance e confiabilidade dentre as opções possíveis. A metodologia leva em consideração quatro grupos de parâmetros, os quais são: recursos e performance; erros e bits críticos; medidas de radiação, tais como seções de choque estáticas e dinâmicas; e, carga de trabalho média entre falhas. Os resultados obtidos mostram que o fluxo proposto é um método apropriado para estimar tendências de confiabilidade de projeto de sistemas em APSoCs antes de experimentos com radiação.The recent advance of the semiconductor industry has allowed the integration of complex components and systems’ architectures into a single silicon die. Nowadays, state-ofthe-art FPGAs include not only the programmable logic fabric but also hard-core parts, such as hard-core general-purpose processors, dedicated processing blocks, interfaces to various peripherals, on-chip bus structures, and analog blocks. These new devices are commonly called of All Programmable System-on-Chip (APSoC) devices. One of the major concerns about radiation effects on APSoCs is that radiation-induced errors may have different probability and criticality in their heterogeneous hardware parts at both device and design levels. For this reason, this work performs a deep investigation about the radiation effects on APSoCs and the correlation between hardware and software resources sensitivity in the overall system performance. Several static and dynamic experiments were performed on different hardware parts of an APSoC to better understand the trade-offs between reliability and performance of each part separately. Results show that there is a trade-off between design cross section and performance to be analyzed when developing a system on an APSoC. Therefore, today it is mandatory to take into account each design option available and all the parameters of the system involved, such as the execution time and the workload of the system, and not only its cross section. As an example, results show that it is possible to increase the performance of a system up to 5,000 times by changing its architecture with a small impact in cross section (increase up to 8 times), significantly increasing the operational reliability of the system. This work also proposes a reliability analysis flow based on fault injection for estimating the reliability trend of hardware-only designs, software-only designs, and hardware and software co-designs. It aims to accelerate the search for the design scheme with the best trade-off between performance and reliability among the possible ones. The methodology takes into account four groups of parameters, which are the following: area resources and performance; the number of output errors and critical bits; radiation measurements, such as static and dynamic cross sections; and, Mean Workload Between Failures. The obtained results show that the proposed flow is a suitable method for estimating the reliability trend of system designs on APSoCs before radiation experiments.
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Weiss, Alexander. "Effiziente externe Beobachtung von CPU-Aktivitäten auf SoCs." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-184227.
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Die umfassende Beobachtbarkeit von System‐on‐Chips (SoCs) ist eine wichtige Voraussetzung für das effiziente Testen und Debuggen eingebetteter Systeme. Ausgehend von einer Analyse verschiedener Anwendungsfälle ergibt sich ein Katalog von Anforderungen an die Beobachtbarkeit von SoCs. Ein wichtiges Kriterium ist hier die Vollständigkeit der Beobachtung und umfasst die Aktivitäten der CPU (ausgeführte Instruktionen, gelesene und geschriebene Daten, Verhalten des Caches, Ausführungszeiten), des Bussystems und von Umgebungsbedingungen.
Weitere Kriterien sind die Echtzeitfähigkeit und die Kontinuität der Beobachtung sowie die gleichzeitige Durchführung verschiedener Beobachtungsaufgaben. Dabei soll es zu einer möglichst geringen Beeinflussung des SoCs kommen. Weitere wichtige Aspekt sind die Kosten der Lösung, die Universalität, die Skalierbarkeit sowie die Latenz der Verfügbarkeit der Beobachtungsergebnisse.
Für viele Anwendungen, besonders in sicherheitskritischen Bereichen, muss zudem nachgewiesen werden, dass das Beobachtungsverfahren kein Fehlverhalten des SoCs bewirkt bzw. ein solches maskiert. Eine besondere Herausforderung stellen Multiprozessor‐SoCs (MPSoCs) dar, da hier die Kommunikation zwischen den einzelnen CPUs im Inneren des SoC stattfindet und entsprechend schwierig für einen externen Bobachter sichtbar zu machen ist.
Der Stand der Technik zur Beobachtung von SoCs wird im Wesentlichen durch zwei Verfahren dargestellt. Bei der Software‐Instrumentierung wird zum funktionalen Programmcode zusätzlicher Code hinzugefügt, welcher zur Beobachtung des Programms dient. Diese Methode ist einfach und universell anwendbar, erfüllt aber die genannten Kriterien nur sehr eingeschränkt. Nachteilig ist hier der Ressourcenverbrauch im Falle des Verbleibs der Instrumentierung im fertigen Produkt. Wird die Instrumentierung nur temporär dem Code hinzugefügt, muss sichergestellt werden, dass das Beobachtungsergebnis auch für den finalen Code anwendbar ist – was besonders bei ressourcen‐abhängigen Integrationstests nur schwierig erfüllbar ist.
Eine alternative Lösung stellt eine spezielle Hardware‐Unterstützung in SoCs („embedded Trace“) dar. Hier werden im SoC Zustandsinformationen (z.B. Taskwechsel, ausgeführte Instruktionen, Datentransfers) gesammelt und mittels Trace‐Nachrichten an den Beobachter übermittelt. Dabei stellt die Bandbreite, die zur Ausgabe der Trace‐Nachrichten vom SoC verfügbar ist, ein entscheidendes Nadelöhr dar ‐ im SoC sind viel mehr den Beobachter interessierende Informationen verfügbar als nach außen transferiert werden können.
Damit haben beide dem gegenwärtige Stand der Technik entsprechende Beobachtungsverfahren eine Reihe von Einschränkungen, die sich besonders bei der Vollständigkeit der Beobachtung, der Flexibilität, der Kontinuität und der Unterstützung von MPSoCs zeigen.
In dieser Arbeit wird nun ein neuer Ansatz vorgestellt, welcher gegenüber dem Stand der Technik in einigen Bereichen deutliche Verbesserungen bietet. Dabei werden die Trace‐Daten nicht vom zu beobachtenden SoC direkt, sondern aus einer parallel mitlaufenden Emulation gewonnen. Die Bandbreite der für die Synchronisation der Emulation erforderlichen Daten ist in vielen Fällen deutlich geringer als bei der Ausgabe von umfassenden Trace‐Nachrichten mittels „embedded Trace“‐Lösungen. Gleichzeitig ist eine vollständige, äußerst detaillierte Beobachtung der Vorgänge innerhalb des SoC möglich. Das neue Beobachtungsverfahren wurde mittels verschiedener FPGA-basierter Implementierungen evaluiert, hier konnte auch die Anwendbarkeit für MPSoCs gezeigt werden.
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Gamal, Wesam. "Real-time bioimpedance measurements of stem cellbased disease models-on-a-chip." Thesis, University of Edinburgh, 2016. http://hdl.handle.net/1842/20444.
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In vitro disease models are powerful platforms for the development of drugs and novel therapies. Stem-cell based approaches have emerged as cutting-edge tools in disease modelling, allowing for deeper insights into previously unknown disease mechanisms. Hence the significant role of these disease-in-a-dish methods in therapeutics and translational medicine. Impedance sensing is a non-invasive, quantitative technique that can monitor changes in cellular behaviour and morphology in real-time. Bioimpedance measurements can be used to characterize and evaluate the establishment of a valid disease model, without the need for invasive end-point biochemical assays. In this work, two stem cell-based disease models-on-a-chip are proposed for acute liver failure (ALF) and age-related macular degeneration (AMD). The ALF disease model-on-a-chip integrates impedance sensing with the highly-differentiated HepaRG cell line to monitor in real-time quantitative and dynamic response to various hepatotoxins. Bioimpedance analysis and modelling has revealed an unknown mechanism of paracetamol hepatotoxicity; a temporal, dose-dependent disruption of tight junctions (TJs) and cell-substrate adhesion. This disruption has been validated using ultrastructural imaging and immunostaining of the TJ-associated protein ZO-1. Age-related macular degeneration (AMD) is the leading cause of blindness in the developed world with a need for disease models for its currently incurable forms. Human induced pluripotent stem cells (hiPSCs) technology offers a novel approach for disease modelling, with the potential to impact translational retinal research and therapy. Recent developments enable the generation of Retinal Pigment Epithelial cells from patients (hiPSC-RPE), thus allowing for human retinal disease in vitro studies with great clinical and physiological relevance. In the current study, the development of a tissue-on- a-chip AMD disease model has been established using RPE generated from a patient with an inherited macular degeneration (case cell line) and from a healthy sibling (control cell line). A reproducible Electric Cell-substrate Impedance Sensing (ECIS) electrical wounding assay was conducted to mimic RPE damage in AMD. First, a robust and reproducible real-time quantitative monitoring over a 25-day period demonstrated the establishment and maturation of RPE layers on microelectrodes. A spatially-controlled RPE layer damage that mimicked cell loss in AMD was then initiated. Post recovery, significant differences in migration rates were found between case and control cell lines. Data analysis and modelling suggested this was due to the lower cell-substrate adhesion of the control cell line. These findings were confirmed using cell adhesion biochemical assays. Moreover, different-sized, individually-addressed square microelectrode arrays with high spatial resolution were designed and fabricated in-house. ECIS wounding assays were performed on these chips to study immortalized RPE migration. Migration rates comparable to those obtained with ECIS circular microelectrodes were determined. The two proposed disease-models-on-a-chip were then used to explore the therapeutic potential of the antioxidant N-Acetyl-Cysteine (NAC) on hiPSC-RPE and HepaRG cell recovery. Addition of 10 mM NAC at the end of a 24h paracetamol challenge caused a slight increase in the measured impedance, suggesting partial cell recovery. On the other hand, no effect on case hiPSC-RPE migration has been observed. More experiments are needed to examine the effect of different NAC concentrations and incubation periods. The therapeutic potential of electrical stimulation has also been explored. A preliminary study to evaluate the effect of electrical stimulation on RPE migration has been conducted. An externally applied direct current electric field (DC EF) of 300 mV/mm was found to direct the migration of the immortalized RPE cell line (hTERT-RPE1) perpendicular to the EF. The cells were also observed to elongate and to realign their long axes perpendicular to the applied EF. The proposed tissue-on-a-chip disease models are powerful platforms for translational studies. The potential of such platforms has been demonstrated through revealing unknown effects of acetaminophen on the liver as well as providing deeper insights into the underlying mechanisms of macular degeneration. Combining stem cell technology with impedance sensing provides a high throughput platform for studying patient-specific diseases and evaluating potential therapies.
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Bredin, Fredrik. "Passive volume reduction heart surgery using the Acorn cor cap cardiac support device /." Stockholm : Karolinska institutet, 2007. http://diss.kib.ki.se/2007/978-91-7357-284-2/.
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Vejmola, Tomáš. "Systém identifikace poruch pájeného spoje." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220224.
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This paper describes the draft and implementation of a system for identifying failures on the soldered joints from already existing system, which is, however, limited by dependence of the operating system of the human factor. The innovated system provides us an automatic testing of soldered joints using a computer, with subsequent processing of data electronically using the corresponding software. The first part is devoted to the theory of the formation of flaws on the soldered joints and to the familiarization with uninnovated system. Subsequently, work continues with the practical part, which introduces us the procedure and implementation of the innovated system for identifying failures on the soldered joints. The final part of this paper is an evaluation of the results and fulfilment of work requirements.
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Burke, Patrick William. "A New Look at Retargetable Compilers." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699988/.
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Consumers demand new and innovative personal computing devices every 2 years when their cellular phone service contracts are renewed. Yet, a 2 year development cycle for the concurrent development of both hardware and software is nearly impossible. As more components and features are added to the devices, maintaining this 2 year cycle with current tools will become commensurately harder. This dissertation delves into the feasibility of simplifying the development of such systems by employing heterogeneous systems on a chip in conjunction with a retargetable compiler such as the hybrid computer retargetable compiler (Hy-C). An example of a simple architecture description of sufficient detail for use with a retargetable compiler like Hy-C is provided. As a software engineer with 30 years of experience, I have witnessed numerous system failures. A plethora of software development paradigms and tools have been employed to prevent software errors, but none have been completely successful. Much discussion centers on software development in the military contracting market, as that is my background. The dissertation reviews those tools, as well as some existing retargetable compilers, in an attempt to determine how those errors occurred and how a system like Hy-C could assist in reducing future software errors. In the end, the potential for a simple retargetable solution like Hy-C is shown to be very simple, yet powerful enough to provide a very capable product in a very fast-growing market.
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Oliveira, Georges Willeneuwe de Sousa. "?n?lise da capacidade funcional e da distribui??o regional da ventila??o pulmonar em pacientes com doen?a de chagas." Universidade Federal do Rio Grande do Norte, 2010. http://repositorio.ufrn.br:8080/jspui/handle/123456789/16693.
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Previous issue date: 2010-08-31INTRODUCTION: Cardiac and pulmonary manifestations of the Chagas disease (CD) affect between 20-30% of the infected subjects. The chronic Chagas cardiomyopathy (CCC) has some peculiarities such as arrhythmias and, especially heart failure (HF) and is potentially lethal due to left ventricular dysfunction. How respiratory disorders, patients get progressive loss of functional capacity, which contributes to a poor quality of life related to disease. Measurements of lung volume by the movement of the chest wall surface are an alternative evaluation of lung function and kinematics of complex thoracoabdominal for these patients. OBJECTIVE: evaluate the kinematics of the thoracoabdominal complex through the regional pulmonary volumes and to correlate with functional evaluation of the cardiorrespiratory system in patients with Chagas disease at rest. MATERIALS AND METHODS: a cross-section study with 42 subjects had been divided in 3 groups, 15 composed for patients with CCC, 12 patients with HF of different etiologies and 15 healthful presented control group. An optoelectronic plethysmography (POE), Minnesota questionnaire, six minute walk test, spirometer and manovacuometer was used. RESULTS: It was observed in the 6MWT where group CRL presented greater distance 464,93?44,63m versus Group HF with 399,58? 32,1m (p=0,005) and group CCC 404?68,24m (p=0,015), both the groups presented difference statistics with regard to Group CRL. In the manovacuometer 54,59?19,98; of the group CCC and 42,11?13,52 of group IC found group CRL presented 81,31?15,25 of the predicted versus, presenting in relation to group CRL. In the POE it observed a major contribution in abdominal compartment in patients with IC if compared like CCC and control groups. On the basis of the questionnaire of quality of life of Minessota, verified a low one groups CCC and IC 43,2?15,2 and 44,4?13,1, respectively (p<0,05) when compared with the control group (19,6?17,31). CONCLUSION: it seems that the patients with CCC possess same functional and respiratory characteristics, observed for the POE, 6MWT, manovacuometer and spirometer to the patients of group HF, being able to consider similar interventions for this complementary group as therapeutical of this neglected disease
INTRODU??O: As manifesta??es pulmonares e card?acas da Doen?a de Chagas (DC) afetam entre 20 a 30% dos indiv?duos infectados. A Cardiomiopatia Chag?sica Cr?nica (CCC) possui algumas particularidades tais como arritmias e, principalmente a Insufici?ncia Card?aca (IC), sendo potencialmente letal devido a disfun??o ventricular esquerda. Como altera??es respirat?rias, os pacientes adquirem progressivo preju?zo da capacidade funcional, o que contribui para uma pobre qualidade de vida relacionada ? doen?a. As medidas dos volumes pulmonares atrav?s do movimento da superf?cie caixa tor?cica surgem como alternativa de avalia??o da fun??o pulmonar e da cinem?tica do complexo t?raco-abdominal para estes pacientes. OBJETIVO: analisar a cinem?tica do complexo t?raco-abdominal atrav?s dos volumes pulmonares regionais e correlacionar com avalia??o funcional do sistema cardiorrespirat?rio em pacientes com Doen?a de Chagas durante o repouso. MATERIAIS E M?TODOS: estudo transversal com 42 sujeitos que foram alocados em 3 grupos, sendo 15 composta por pacientes com CCC, 12 pacientes com IC de diferentes etiologias e 15 idosos saud?veis. Foi utilizado um pletism?grafo opto eletr?nico (POE), question?rio de Minessota, teste de caminhada 6 minutos, espirometria e manovacuometria. RESULTADOS: Observou-se no TC6min onde o grupo idosos apresentou maior dist?ncia percorrida 464,93?44,63m vs Grupo IC com 399,58? 32,1m (p=0,005) e grupo CCC 404?68,24m (p=0,015), ambos os grupos apresentam diferen?a estat?stica com rela??o ao Grupo Idosos. Na manovacuometria o grupo idosos apresentou 81,31%?15,25 do predito vs 54,59%?19,98 do grupo CCC e 42,11%?13,52 do grupo IC, apresentando (p<0,05) em rela??o ao grupo Idosos. Na POE observou-se uma maior contribui??o do compartimento abdominal no grupo IC o que n?o aconteceu com os grupos CCC e controle. Com base no question?rio de qualidade de vida de Minessota, verificou-se um baixo escore nos grupos CCC e IC 43,2?15,2 e 44,4?13,1, respectivamente (p<0,05) quando comparados ao grupo controle (19,6?17,31). CONCLUS?O: os dados sugerem que os pacientes com CCC possuem mesmas caracter?sticas funcionais e respirat?rias, observadas pela POE, TC6min, manovacuometria e espirometria aos pacientes do grupo IC, a capacidade funcional apresentou-se diminu?da, podendo considerar interven??es semelhantes para esse grupo como terap?utica complementar dessa doen?a negligenciada
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Bonner, J. K. "Kirk", and Silveira Carl de. "Thermal Cycling Fatigue Investigation of Surface Mounted Components with Eutectic Tin-Lead Solder Joints." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611418.
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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, CaliforniaEutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is important to realize that its homologous temperature, defined as the temperature in degrees Kelvin over its melting point temperature (T(m)), also in degrees Kelvin, is defined as T/T(m). At room temperature (25°C = 298K), eutectic solder's homologous temperature is 0.65. It is widely acknowledged that materials having a homologous temperature ≥ 0.5 are readily subject to creep, and the solder joints of printed wiring assemblies are routinely exposed to temperatures above room temperature. Hence, solder joints tend to be subject to both thermal fatigue and creep. This can lead to premature failures during service conditions. The geometry, that is, the lead configuration, of the joints can also affect failure. Various geometries are better suited to withstand failure than others. The purpose of this paper is to explore solder joint failures of dual in-line (DIP) integrated circuit components, leadless ceramic chip carriers (LCCCs), and gull wing and J-lead surface mount components mounted on PWBs.
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Jullien, Jean-Baptiste. "Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14604/document.
Full textAbstract:
Ce travail s'intègre dans les domaines de l'analyse et de la prédiction de la fiabilité des assemblages Multi-Chip Module. Il présente l'étude de fiabilité de microcâblages filaires (wire bonding) en très haute température à partir d'essais de vieillissement et d'analyses expérimentales. Les résultats permettent d'identifier les mécanismes de dégradation et d'évaluer les températures limites d'utilisation de ces interconnexions. Il développe une étude du comportement thermomécanique des joints collés à partir d'essais de caractérisation mécanique, d'essais de vieillissement accéléré et de simulations numériques par éléments finis. Ces méthodes permettent d'évaluer la criticité des assemblages dès la phase de conceptionThis work is performed in analysis and prediction areas of Multi-Chip Module package reliability. It presents a reliability study on wire bonding in high temperature environment from aging tests and experimental analyzes. Results permit to identify degradation mechanisms and evaluate temperature limits of these interconnections. It develops a study of the thermomechanical behavior of adhesive joints from mechanical characterization tests, accelerated aging tests and finite element simulations. These methods are used to assess the criticality of packages from the design phase
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Attia, Thomas. "Interfaces between pavement layers in bituminous mixtures." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSET001.
Full textAbstract:
Afin que les structures de chaussée présentent une bonne résistance mécanique, les couches qui les composent sont liées entre elles à l’aide de « couches d’accrochage ». Un nouvel appareil, nommé 2T3C (Torsion-Traction‑Compression sur Cylindre Creux), a été conçu dans cette thèse pour caractériser le comportement thermomécanique des interfaces entre couches de chaussées en enrobé bitumineux. La Corrélation d’Images Numériques en trois dimensions (CIN 3D) a notamment été utilisée pour trouver les sauts de déplacement au niveau de l’interface. Le comportement de différentes configurations d’interfaces a été étudié dans le domaine des petites déformations, pour lequel un nouveau modèle a été introduit pour les décrire, et dans le domaine des grandes déformations à l’aide d’essais de rupture monotone en cisaillementTo ensure that road structures present a good mechanical strength, the layers that compose them are bonded together with tack coats. A new device, named 2T3C Hollow Cylinder Apparatus (2T3C HCA), has been designed in this thesis to characterise the thermomechanical behaviour of interfaces between pavement layers in bituminous mixtures. 3D Digital Image Correlation (3D DIC) has been used to find the displacement gaps at the interface. The behaviour of different interface configurations has been studied in the small strain domain, for which a new model was introduced to describe them, and in the large strain domain thanks to monotonic shear failure tests
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Bučinskas, Giedrius. "BŽŪP reformų poveikis daugiafunkcinio žemės ūkio plėtotei." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2006. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2006~D_20060522_114822-92137.
Full textAbstract:
The aim of work – evaluate the Effect of the CAP Reforms on the Development of Multifunctional Agriculture. Seeking the aim, the tasks are: 1) analyze the objective presumptions and essence of the formation of the concept of multifunctional agriculture; 2) analyze the reforms of the CAP and evaluate their effect on the development of multifunctional agriculture; 3) reveal the possibilities of the development of multifunctional agriculture in Tauragė region; 4) analyze the measures of the CAP support, stimulating multifunctional agriculture in Tauragė region and evaluate their practice; 5) evaluate the ways and perspectives of the development of multifunctional agriculture in Lithuania. Methods of research – the analysis and synthesis of scientific literature and the EU and Lithuanian agricultural and rural development documents, comparable analysis, induction, deduction, questionnaire survey, correlation, statistical analysis, graphical depiction methods. On the bases of positive and normative concept of multifunctional agriculture, the analysis of the EU regulations of the CAP and their reforms, analyzed the main stages of the CAP reforms, designated their effect on the development of multifunctional agriculture. Thereby, designated the main CAP measures stimulating multifunctional agriculture and evaluated their practice in Tauragė region and revealed the possibilities of the development of multifunctional agriculture in this region.
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Klenowski, Paul Mark. "Molecular and structural requirements of the ß1L-adrenoceptor." Thesis, Queensland University of Technology, 2012.
Find full textAbstract:
Noradrenaline which occurs naturally in the body binds to beta-adrenoceptors on the heart, causing the heart to beat faster and with greater force in response to increased demand. This enables the heart to provide oxygenated blood to vital organs. Prolonged overstimulation by noradrenaline can be harmful to the heart and lead to the progression of heart disease. In these circumstances beta-adrenoceptors are blocked with drugs called beta-blockers. Beta-blockers block the effects of noradrenaline by binding to the same site on the beta-adrenoceptor. Some beta-blockers such as CGP12177 can also cause increases in heart rate. Therefore it was proposed that CGP12177 could bind in a different place to noradrenaline. The aim of this study was to determine where CGP12177 binds to on the beta-adrenoceptor. The results have revealed a separate binding site named beta-1-low. These results may lead to the development of improved -blockers for the management of heart conditions.
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Durand, Camille. "Etude thermomécanique expérimentale et numérique d'un module d'électronique de puissance soumis à des cycles actifs de puissance." Thesis, Valenciennes, 2015. http://www.theses.fr/2015VALE0007/document.
Full textAbstract:
De nos jours, la durée de vie des modules d’électronique de puissance est désormais limitée par les technologies standards de conditionnement, telles que le câblage par fils et le brasage. Ainsi une optimisation des technologies actuellement employées n’est pas suffisante pour satisfaire les futures exigences de fiabilité. Pour dépasser ces limites, un nouveau module de puissance remplaçant les fils de connexion par des clips en cuivre a été développé. Ce design innovant vise à améliorer la fiabilité du module puisqu’il empêche la dégradation des fils de connexion, constituant bien souvent la principale source de défaillance. La contrepartie de ce gain de fiabilité réside dans la complexification de la structure interne du module. En effet, l’emploi d’un clip en cuivre nécessite une brasure supplémentaire fixant le clip à la puce. Ainsi, le comportement thermomécanique et les différents modes de rupture auxquels le composant est soumis lors de son utilisation doivent être caractérisés. Cette étude utilise la simulation numérique pour analyser avec précision le comportement de chaque couche de matériaux lors des cycles actifs de puissance. De plus, une étude de sensibilité à la fois expérimentale et numérique concernant les paramètres de tests est réalisée. Les zones critiques du module ainsi que les combinaisons critiques des paramètres de tests pour les différents modes de rupture sont mis en évidence. Par ailleurs, une analyse en mécanique de la rupture est conduite et la propagation des fissures à différentes zones clés est analysée en fonction des différents paramètres de tests. Les résultats obtenus permettent la définition de modèles de prédiction de durée de vieToday a point has been reached where safe operation areas and lifetimes of power modules are limited by the standard packaging technologies, such as wire bonding and soft soldering. As a result, further optimization of used technologies will no longer be sufficient to meet future reliability requirements. To surpass these limits, a new power module was designed using Cu clips as interconnects instead of Al wire bonds. This new design should improve the reliability of the module as it avoids wire bond fatigue failures, often the root cause of device failures. The counterpart for an improved reliability is a quite complicated internal structure. Indeed, the use of a Cu clip implies an additional solder layer in order to fix the clip to the die. The thermo-mechanical behavior and failure mechanisms of such a package under application have to be characterized. The present study takes advantage of numerical simulations to precisely analyze the behavior of each material layer under power cycling. Furthermore an experimental and numerical sensitivity study on tests parameters is conducted. Critical regions of the module are pointed out and critical combinations of tests parameters for different failure mechanisms are highlighted. Then a fracture mechanics analysis is performed and the crack growth at different locations is analyzed in function of different tests parameters. Results obtained enable the definition of lifetime prediction models
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Deobarro, Mikaël. "Etude de l'immunité des circuits intégrés face aux agressions électromagnétiques : proposition d'une méthode de prédiction des couplages des perturbations en mode conduit." Thesis, Toulouse, INSA, 2011. http://www.theses.fr/2011ISAT0002/document.
Full textAbstract:
Avec les progrès technologiques réalisés au cours de ces dernières décennies, la complexité et les vitesses de fonctionnement des circuits intégrés ont beaucoup été augmentées. Bien que ces évolutions aient permis de diminuer les dimensions et les tensions d’alimentations des circuits, la compatibilité électromagnétique (CEM) des composants a fortement été dégradée. Identifiée comme étant un verrou technologique, la CEM est aujourd’hui l’une des principales causes de « re-design » des circuits car les problématiques liées aux mécanismes de génération et de couplage du bruit ne sont pas suffisamment étudiées lors de leur conception.Ce manuscrit présente donc une méthodologie visant à étudier la propagation du bruit à travers les circuits intégrés par mesures et par simulations. Afin d’améliorer nos connaissances sur la propagation d’interférences électromagnétiques (IEM) et les mécanismes de couplage à travers les circuits, nous avons conçu un véhicule de test développé dans la technologie SMOS8MV® 0,25 µm de Freescale Semiconductor. Dans ce circuit, plusieurs fonctions élémentaires telles qu’un bus d’E/S et des blocs numériques ont été implémentées. Des capteurs de tensions asynchrones ont également été intégrés sur différentes alimentations de la puce pour analyser la propagation des perturbations injectées sur les broches du composant (injection DPI) et sur les conducteurs permettant d’alimenter ce dernier (injection BCI). En outre, nous proposons différents outils pour faciliter la modélisation et les simulations d’immunité des circuits intégrés (extraction des modèles de PCB, approches de modélisation des systèmes d’injection, méthode innovante permettant de prédire et de corréler les niveaux de tension/ de puissance injectés lors de mesures d’immunité conduite, flot de modélisation). Chaque outil et méthode de modélisation proposés sont évalués sur différents cas test. Enfin, pour évaluer notre démarche de modélisation, nous l’appliquons sur un bloc numérique de notre véhicule de test et comparons les résultats de simulations aux différentes mesures internes et externes réalisées sur le circuitWith technological advances in recent decades, the complexity and operating speeds of integrated circuits have greatly increased. While these developments have reduced dimensions and supply voltages of circuits, electromagnetic compatibility (EMC) of components has been highly degraded. Identified as a technological lock, EMC is now one of the main causes of circuits re-designs because issues related to generating and coupling noise mechanisms are not sufficiently studied during their design. This manuscript introduces a methodology to study propagation of electromagnetic disturbances through integrated circuits by measurements and simulations. To improve our knowledge about propagation of electromagnetic interferences (EMI) and coupling mechanisms through integrated circuits, we designed a test vehicle developed in the SMOS8MV® 0.25µm technology from Freescale Semiconductor. In this circuit, several basic functions such as I/O bus and digital blocks have been implemented. Asynchronous on-chip voltage sensors have also been integrated on different supplies of the chip to analyze propagation of disturbances injected on supply pins and wires of the component (DPI and BCI injection). In addition, we propose various tools to facilitate modeling and simulations of Integrated Circuit’s immunity (PCB model extraction, injection systems modeling approaches, innovative method to predict and correlate levels of voltage / power injected during conducted immunity measurements, modeling flow). Each tool and modeling method proposed is evaluated on different test cases. To assess our modeling approach, we finally apply it on a digital block of our test vehicle and compare simulation results to various internal and external measurements performed on the circuit
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Chandrakash, Saravanan. "A new risk analysis of clean-in-place (CIP) milk processing." Thesis, 2012. http://hdl.handle.net/2440/76140.
Full textAbstract:
The food and pharmaceutical industry are generally a nation’s largest manufacturing sector – and importantly one of the most stable. Clean-In-Place (CIP)² is a ubiquitous process in milk processing as thorough cleaning of wet surfaces of equipment is an essential part of daily operations. Faulty cleaning can have serious consequences as milk acts as an excellent substrate in which unwanted micro-organisms can grow and multiply rapidly. Davey & Cerf (2003) introduced the notion of Friday 13th Syndrome³ i.e. the unexpected failure of a well-operated process plant by novel application of Uncertainty Failure Modelling (Davey, 2010; 2011). They showed that failure cannot always be put down to human error or faulty fittings but could be as a result of stochastic changes inside the system itself. In this study a novel CIP failure model based on the methodology of Davey and co-workers is developed using the published models of Bird & Fryer (1991); Bird (1992) and Xin (2003); Xin, Chen & Ozkan (2004) for the first time. The aim was to gain insight into conditions that may lead to unexpected failure of an otherwise well-operated CIP plant. CIP failure is defined as failure to remove proteinaceous deposits on wet surfaces in the auto-set cleaning time. The simplified two-stage model of Bird & Fryer (1991) and Bird (1992) was initially investigated. This model requires input of the thickness of the deposit (δ = 0.00015 m) and the temperature and Re of the cleaning solution (1.0-wt% NaOH). The deposit is considered as two layers: an upper layer of swelled deposit which can be removed (xδ) by the shear from the circulating cleaning solution and a lower layer (yδ) that is not yet removable. The output parameters of particular interest are the rate of deposit removal (R) and total cleaning time (t[subscript]T) needed to remove the deposit. The more elaborate three-stage model of Xin (2003) and Xin, Chen & Ozkan (2004) is based on a polymer dissolution process. This model requires input values of temperature of the cleaning solution (T), critical mass of the deposit (m[subscript]c) and cleaning rate (R[subscript]m). The output parameters of particular interest are the rate of removal during swelling and uniform stage (R[subscript]SU), the rate of removal during decay stage (R[subscript]D) and the total cleaning time needed to remove the deposit (t[subscript]T). The two CIP models are appropriately formatted and simulations used to validate them as a unit-operation. A risk factor (p) together with a practical process tolerance is defined in terms of the auto-set CIP time to remove a specified deposit and the actual cleaning time as affected by stochastic changes within the system (t[subscript]T'). This is computationally convenient as it can be articulated so that all values p > 0 highlight an unwanted outcome i.e. a CIP failure. Simulations for the continuous CIP unit-operation are carried out using Microsoft Excel™ spreadsheet with an add-in @Risk™ (pronounced ‘at risk’) version 5.7 (Palisade Corporation) with some 100,0004 iterations from Monte Carlo sampling of input parameters. A refined Latin Hypercube sampling is used because ‘pure’ Monte Carlo samplings can both over- and under-sample from various parts of a distribution. Values of the input parameters took one of the two forms. The first was the traditional Single Value Assessment (SVA) as defined by Davey (2011) in which a single, ‘best guess’ or mean value of the parameter is used. The output therefore is a single value. The alternate form was a Monte Carlo Assessment (MCA) (Davey, 2011) in which the ‘best guess’ values take the form of a probability distribution around the mean value. Many thousands of randomly sampled values for each input parameter are obtained using Monte Carlo sampling. Generally, in QRA the input parameters take the form of a distribution of values. The output therefore is a distribution of values with each assigned a probability of actually occurring. The values of all inputs are carefully chosen for a realistic simulation of CIP. Results reveal that a continuous CIP unit-operation is actually a mix of successful cleaning operations along with unsuccessful ones, and that these can tip unexpectedly. For example for the unit-operations model of Bird & Fryer (1991) and Bird (1992) failure to remove a proteinaceous milk deposit (δ = 0.00015 m) can occur unexpectedly in 1.0% of all operations when a tolerance of 6% is allowed on the specified auto-set cleaning time (t[subscript]T = 914 s) with a cleaning solution temperature of 60 °C. Using Xin, Chen & Ozkan (2004) model as the underlying unit-operation some 1.9% of operations at a nominal mid-range cleaning solution temperature of 75 °C could fail with a tolerance of 2% on the auto-set CIP time (t[subscript]T = 448 s). Extensive analyses of comparisons of the effect of structure of the two CIP unit-operations models on predictions at similar operating conditions i.e. 2% tolerance on the auto-set clean time (~ 656 s) and 1%-sd in the nominal mean temperature of the NaOH cleaning solution at 65 °C, highlighted that the underlying vulnerability to failure of the simplified model of Bird & Fryer (1991) and Bird (1992) was 1.8 times that of the more elaborate model of Xin (2003) and Xin, Chen & Ozkan (2004). The failure analysis presented in this thesis represents a significant advance over traditional analysis in that all possible practical scenarios that could exist operationally are computed and rigorous quantitative evidence is produced to show that a continuous CIP plant is actually a mix of failed cleaning operations together with successful ones. This insight is not available from traditional methods (with or without sensitivity analysis). Better design and operating decisions can therefore be made because the engineer has a picture of all possible outcomes. The quantitative approach and insight presented here can be used to test re-designs to reduce cleaning failure through changes to the plant including improved temperature and auto-set time control methods.
2 see Appendix A for a definition of some important terms used in this research.
3 Unexpected (unanticipated) failure in plant or product of a well-operated, well-regulated unit-operation.
4 Experience with the models highlighted that stable output values would be obtained with 100,000 iterations (or CIP ‘scenarios’).Thesis (M.Eng.Sc.) -- University of Adelaide, School of Chemical Engineering, 2012
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Jim_Lin and 林柏奇. "Flip Chip Underfill Evaluation, Reliability and Failure Analysis." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/47514806283751991036.
Full textAbstract:
碩士國立清華大學
材料科學工程學系
89
Abstract The target for this thesis is discussing underfill material , reliability and failure analysis in Flip Chip process.The best combination of material and pattern were found .The followed reliability and failure analysis after dispensing had been well discussed to be a direction of choosing underfill material.In thsis, we sucessfully discribed underfill process and failure mode by the aid of SAT, Cross-section, SEM and EDS.
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Ou, Shi-Ming, and 歐士銘. "The Failure Analysis for the Chip Capacitor Cutter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/79966866226100278554.
Full textAbstract:
碩士國立屏東科技大學
機械工程系
93
The aim of this study is to analyze the thermal stress and strain for the cutter of the chip capacitor cutter machine and to discuss the broken problem of the cutter. First of all, we heated an aluminum cantilever beam and record the displacement of the cantilever beam by means of the correlation matching method of image processing validate the acceptance of the aluminum beam model of ANSYS analysis. After that, we analyzed the chip capacitor cutter by FEA expecting to predict where the displacement and strain occurred then we also measured the strain of the cutter’s holder by strain measuring system. Compared the simulated results from FEA model with the results from strain measuring system can prove the FEA model. Using this FEA model can further simulated the thermal-structure couple field of the FEA model, compared the result with real cutter failure position in order to find the reason of the failure and can improve the wearing for cutter. This effective analyze method can optimum the design of the cutter’s holder in order to reduce the cost of the cutter in internal. Then it can promote the products ability of MLCC valid.
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Shao, Tung Liang, and 邵棟樑. "Failure Mechanism of Electromigration for Flip-Chip SnAg3.5 Solder Joints." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/08288625847433983410.
Full textAbstract:
博士國立交通大學
材料科學與工程系所
94
Electromigration behavior of lead-free SnAg3.5 solder joints was investigated under the average current densities of 1 �e 104 A/cm2 and 5 �e 103 A/cm2 at 150℃. Different failure modes were observed for the above two stressing conditions. When stressed at 1 �e 104 A/cm2, damage occurred in both anode/chip side and cathode/chip sides. However, failure happened only in the cathode/chip under the stressing of 5 �e 103 A/cm2. Three-dimensional simulation of current density distribution by finite element method was performed to provide better understanding of current crowding behavior in the solder joint. The local maximum current density of flip chip solder joint was as high as 1.24×105 A/㎝2 under the stressing of 1 �e 104 A/cm2. And the location of the maximum current density occurred in the vicinity of the Al entrance into the solder joint. In addition, both temperature increases and thermal gradients were measured during the two stressing conditions. The measured temperature increase due to Joule heating was as high as 54.5 ℃, and the thermal gradients reached 365 ℃/cm when stressed by 1 �e 104 A/cm2. Joule heating plays an important role in the failure mechanism during higher current stressing. Possible mechanisms responsible for the different failure modes are proposed.
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Michel, Kenan. "Failure Behaviour of Masonry under Compression Based on Numerical and Analytical Modeling." Doctoral thesis, 2015. https://tud.qucosa.de/id/qucosa%3A29140.
Full textAbstract:
In this work the compression behavior of masonry was investigated. After a detailed review of code approaches and different research works, a new formula was suggested to describe the compression strength of masonry, based on the mechanical and geometrical properties of its components, when deformation properties of units are larger than the ones of mortar.
Later on, a new model, Extended Drucker-Prager Cap Yielding Function, is suggested to describe the three axial compression stress state of mortar in masonry in case deformation properties of mortar are larger than the ones of mortar, and to describe the three axial compression stress state of brick in the other case. This includes defining its parameters based on test diagrams of the mortar material, implementing the model in the numerical software ANSYS, and the numerical results are evaluated for simple cube example.
The controlling equations of creep based on the visco-elastic creep theory are presented in the general case of three axial creep under three axial loading conditions. The special case of three axial creep under axial loading is also presented. The “transversal creep” relevant for the compression strength of masonry was discussed and numerical examples have been added to show the effect of changed time-dependent Poisson’s ratio.
In another chapter, many examples are presented showing the application of the suggested material models and discontinuous numerical method named eXtended finite element method. Conclusions and recommendations are given in the last chapter.
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Huff, Mathew. "Emissions Policy in Canada: Past Failures and Future Promises." Thesis, 2014. http://hdl.handle.net/1828/5707.
Full textAbstract:
Climate change represents a challenging problem in public policy. This project examines various policy solutions to rising emissions, and suggests one that might be best suited to Canada, a highly-integrated, highly-developed economy which relies on natural resources, including fossil fuels, for its balance of payments, governmental revenues, and a small portion of its GDP. It adopts a public policy framework from Simpson, Rivers and Jaccard (2008) to analyze policy solutions using the following criteria: political acceptability, economic efficiency, administrative feasibility and effectiveness at reducing emissions. Additionally, it offers substantial discussion relating to the potential constraints and opportunities to climate change policy presented by NAFTA, compliance with which is key to the viability of any emissions regime. It advocates an upstream cap-and-trade system, integrated with the NAFTA area and regulated by an empowered Commission for Environmental Cooperation (CEC), as well as complementary policies to lower emissions in inelastic sectors.Graduate
mat.huff@gmail.com
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Lin, Yen-Liang, and 林彥良. "Study of the Failure Mechanisms of Flip Chip Solder Joints under Current Stressing." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/u3xgs6.
Full textAbstract:
博士國立中央大學
化學工程與材料工程研究所
96
This dissertation investigated the reliability of eutectic PbSn flip chip solder joints under applied current of 0.32 A at 150°C. It includes the discussion of the failure mechanisms and two feasible methods for prolonging the lifetime of solder joints. We propose a new failure mechanism in this dissertation. Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became non-conductive and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever larger non-conductive region. The solder joint eventually failed when the nonconductive region became too large, making the effective current density very high. To prolong the lifetime of solder joints under current stressing, two kinds of experimental setups were used. One is to experiment the solder joints with different Ni UBM thickness. In this part, three different Ni thicknesses in the Cu/Ni/Al UBM (0.3, 0.5, and 0.8 μm) were used in order to investigate the effect of the Ni thickness on the reliability. The solder joints with 0.8μm Ni UBM have the longest lifetime more than 1000 hours. The failure model is also able to support the observation that the joints with a thicker Ni tended to have a longer average lifetime. The other is to experiment the solder joint with different UBM and surface finish combinations. In this part, two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150 oC ambient temperature. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 vs. 530 hrs). The key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate. Besides the study of the reliability of flip chip solder joints under current stressing, we also discuss the existence of melting solder at the last stage of current stressing. By microstructure examination and 3-D coupled thermoelectric simulation, it was found that due to the fact that Ni UBM has been completely consumed and almost replaced by the non-conductive porous structure that the local resistance abruptly raised at the region where there is almost no conduct area and caused excessive Joule heating generation to melt solder joint.
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Po-YuanHsiao and 蕭博元. "Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/47329231332951484870.
Full textAbstract:
碩士國立成功大學
工程科學系
102
In recent years, with the continuous progress and innovation of the electronic products progress, the requirements for frivolous short, high frequency, high speed and the high heat emission to the IC chip has increased. As a result, the flip chip and some similar packages which are facilitated to reduce the IC area become the mainstream product in the market. By adopting the Direct Chip Attach Package, this paper aims to investigate the stress condition at the conducting layer of the package so as to figure out the fragile location of the conducting layer and ensure the stability of product quality. The ANSYS 12.0 finite element analysis is employed as well as the Direct Chip Attach Package is subjected by the thermal cycle of -45℃~125℃. The solder ball is considered as elasticplastic while other components are treated as elastic. The Global/Local Method is adopted for analysis. The material properties of the conducting layer is replaced by equivalent parameters in the global model and the original parameters are restored to each conducting layer in the local model so as to achieve certain accuracy and convergence, and then the stress behaviors of the conducting layer are investigated. It is found that the maximum Y component of stress is -231.06Mpa located at the bottom of oxide layer in high temperature while the maximum Y component of stress is -371.448Mpa located at the top of the copper layer in low temperature. It seems that the two locations are easy to delaminate and crack. The above model is regarded as the standard model. Secondly, the temperature cycle loading, such as high temperature, low temperature, time of constant temperature and the heat rate, is changed to compare with the standard model in which the stress changing and the failure mode in the conducting layer are observed. Finally, the structure of the conducting layer is changed, such as the increase of the amount of copper layers, to analyze its difference from the standard model. By comparing with those factors, the amount of copper layers is more significant factor which is changed from 4 copper layers to the 8 copper layers for the structure of the conducting layer, it shows that more copper layers in conducting layers, higher Y component of stress happening in each part of conducting layers in low temperature. Y component of stress is 31.7% increasing in copper layers and 23.3% increasing in oxide layers. It also shows the opposite results in high temperature where Y component of stress is 102% decreasing in copper layers and 128% decreasing in oxide layers.
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Huang, Chang-Chia. "Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration." 2009. http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7037.
Full textAbstract:
The demand for high performance microelectronic products drives the
development of 3-D chip-stacking structure. By the introduction of through-silicon-via
(TSV) into 3-D flip-chip packages, microelectronic performance is improved by
increasing circuit capacity and diminishing signal delay. However, TSV-embedded
structure also raises concerns over many reliability issues that come with the steep
thermal and mechanical transient responses, increasing numbers of bi-material interfaces
and reduced component sizes. In this research, defect initiation induced by thermalmechanical
phenomena is studied to establish the early failure modes within 3-D flip-chip
packages. It is found that low amplitude but extremely high frequency thermal
stress waves would occur and attenuate rapidly in the first hundreds of nanoseconds
upon power-on. Although the amplitude of these waves is far below material yielding
points, their intrinsic characteristics of high frequency and high power density are
capable of compromising the integrity of all flip-chip components. By conducting
spectral analysis of the stress waves and applying the methodology of accumulated
damage evaluation, it is demonstrated that micron crack initiation and interconnect debond are highly probable in the immediate proximity of the heat source. Such a
negative impact exerted by the stress wave in the early, while brief, transient period is
recognized as the short time scale dynamic effect. Researched results strongly indicate
that short-time scale effects would inflict very serious reliability issues in 3-D flip-chip
packages. The fact that 3-D flip-chip packages accommodate a large amount of
reduced-size interconnects makes it vulnerable to the attack of short time scale
propagating stress waves. In addition, the stacking structure also renders shearing effect
extremely detrimental to 3-D flip-chip integrity. Finally, several guidelines effective in
discouraging short-time scale effects and thus improving TSV flip-chip package
reliability are proposed
30
Bedairi, Badr. "Numerical Failure Pressure Prediction of Crack-in-Corrosion Defects in Natural Gas Transmission Pipelines." Thesis, 2010. http://hdl.handle.net/10012/5368.
Full textAbstract:
The aim of this study was to use the finite element method to model crack, corrosion, and Crack-in-Corrosion defects in a pipeline. The pipe material under investigation for this study was API 5L X60, 508 mm diameter with a wall thickness of 5.7 mm. The pipe material was evaluated using Tensile, Charpy, and J testing in order to model the defects and to establish the numerical failure criteria.
Corrosion defects were modeled as flat-bottomed grooves. The collapse pressure was predicted when the deepest point in the bottom of the defect reached a critical stress. Based on this criterion, the FE corrosion failure pressure predictions were conservative compared to the experimental failure pressures, conducted by Hosseini [9], with an average error of 10.13%.
For crack modeling, the failure criteria were established considering the plastic collapse limit and the fracture limit. Both the Von Mises stress in the crack ligament and the J-integral values around the crack were monitored to predict the failure pressure of the model. The crack modeling was done based on two approaches, the uniform depth profile and the semi-elliptical profile. The crack with uniform depth profile was done because the uniform shape is the logical equivalent shape for a colony of cracks. The crack with the semi-elliptical profile was done to have a less conservative results and because the experiments were done with semi-elliptical cracks. The FE crack modeling results were conservative compared to the experimental collapse pressure with an average error of 19.64% for the uniform depth profile and 5.35% for the semi-elliptical profile.
In crack-in-corrosion (CIC) defect modeling, the crack was modeled with uniform depth because it was very difficult to model the semi-elliptical crack profile when the crack defect is coincident with a corrosion defect. The results were conservative compared to the experimental results with an average error of 22.18%.
In general, the FE modeling provides the least conservative failure pressure prediction over the existing analytical solutions for pipe with longitudinal corrosion, crack, and CIC defects.
31
Liao, Chih-Jen, and 廖志仁. "Temperature-Dependence Electromigration Failure for Flip-Chip SnAg Solder bumps with 5μm Cu metallization." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/nqb386.
Full textAbstract:
碩士國立交通大學
工學院半導體材料與製程設備學程
102
As the consumer electronic products move toward lightly, thin, short and smaller, we need higher solder input/output joint density. Therefore, the evolution of the bonding technology has moved from “Wire Bonding” to “Flip Chip technology”. Along with the solder bump shrinking and current density increased, electromigration phenomenon had become a crucial reliability concern. Pb-containing solder bump will cause environment pollution, and European Union and the US already forbade to use the Pb-containing solder bumps through the law at Y2006. Thus, the electrical industry is hurry to find the substitute to replace eutectic SnPb solder bump. Pb free solders become the basic requirement for the future electronic product. In recent years, Pb free solder bump research and development as become an important part of the electrical industry. SnAg is one of potential Pb free solder alloys. The Sn-Ag alloy's melting point is about 220°C, and its good mechanical property makes it become a candidate of Pb free solder bump materials. In this study, we investigate the Electromigration behavior stressed by 0.8A at 100℃ and 160℃. The electromigration behavior and the failure mechanism of the bump are monitored at various stages of electromigration. The microstructure of the solder bumps were observed as the bump resistance increased 20%, 100%, 200%, and Opened of its original value. It is found that void formation is mainly responsible for the increase in bump resistance.
32
Liao, Pei-lan, and 廖珮嵐. "Flip-Chip Cu Pad Consumed at the Cathode Side and Electromigration (EM) Failure Modes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/29635852557484320751.
Full textAbstract:
碩士國立中央大學
化學工程與材料工程研究所
95
To study electromigration (EM), flip-chip Cu-Sn-Cu structures were prepared. This study investigates on effect of current density induced Cu pad consumption at the cathode side and interfacial metallic compound. EM test were carried under three temperatures, which are 80, 100 and 125 ℃ for 4 days, respectively. Current densities were 1~6×103 A/cm2 passed through the solder bumps. After EM test, the Cu consumption increased with current density linearly. Therefore, we modified kinetics of the Cu consumption equation as Δh=Bexp( )tnj. By this expression, the Cu consumption will be predicted under any current density. Besides, Solder bump were under 5×103 A/cm2 at 55 ℃ for 10 days. Different phenomenons were observed at the both side. Cu pad consumed very seriously at the current entry point. On another corner which distant from the current entry point, voids formed at the IMC/solder cathode interface. At the anode side, the Kirkendall voids were found to occur at the anode Cu3Sn/Cu interface. No Kirkendall voids found at the cathode side.
33
Chen, Shih-Hung, and 陳世宏. "Design Optimization and Failure Analysis of On-Chip ESD Protection in CMOS Integrated Circuits." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/60688421017219325054.
Full textAbstract:
博士國立交通大學
電子工程系所
97
With the era of the advanced nanoscale CMOS technology and the development of system-on-chip (SoC) application, electrostatic discharge (ESD) protection has become a tough challenge on the product reliability of CMOS integrated circuits. ESD protection must be taken into consideration during the design phase of all IC products. In order to prevent the ESD failures and damages in IC products, all pads which connect the IC and the external world need to be provided with ESD protection circuits, including the input/output (I/O) pads, VDD pads, and VSS pads. However, the ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path. If the parasitic effects on the signal path are too large, the circuit performance will be seriously degraded. In other words, the parasitic effects which are induced by ESD protection on the signal paths need to be minimized, especially in analog I/O interface circuits and internal transmission interface circuit between separated power domains. The power-rail ESD clamp circuit is an efficient design to achieve whole-chip ESD protection in IC products. It not only can enhance ESD robustness of VDD-to-VSS ESD stress, but also can significantly improve ESD robustness of the ESD stresses between input/output and VDD/VSS or pin-to-pin combinations. A turn-on efficient power-rail ESD clamp circuit between VDD and VSS is co-constructed into the analog ESD protection circuit to improve the overall ESD level of the analog I/O interface circuits. Moreover, the ESD issues of interface circuits between separated power domains also can be solved by turn-on efficient power-rail ESD clamp circuit cooperated with active cross-power-domain ESD protection designs. With efficient on-chip ESD protection designs, the integrated circuits with nanoscale CMOS technology can be safely used and provide moderate life time. NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In Chapter 2, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector. Besides controlling circuit in NMOS-based power-rail ESD clamp circuit, a power-rail ESD clamp circuit with a new proposed ESD-transient detection circuit of ultra small capacitor has been presented and verified to possess a long turn-on duration and high turn-on efficiency in chapter 3. In addition, the power-rail ESD clamp circuit with the proposed ESD-transient detection circuit also showed an excellent immunity against the mis-trigger and the latch-on event under the fast power-on condition. In chapter 4, a novel SCR design with “initial-on” function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes to enhance the applications of SCR devices for deep-submicron or nanoscale CMOS technology. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-μm CMOS process. In chapter 5, the channel length of the embedded MOS transistor in the MOS-triggered SCR device has been demonstrated to dominate the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. MOS-triggered SCR devices have been reported to achieve efficient on-chip ESD protection in deep-submicron or nanoscale CMOS technology. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection. In chapter 6, different ESD protection schemes have been investigated to find the optimal ESD protection design for analog I/O buffer in a 0.18-µm 1.8-V and 3.3-V CMOS technology. Three power-rail ESD clamp devices, which are gate-driven NMOS, substrate-triggered field-oxide device (STFOD), and substrate-triggered NMOS (STNMOS) with dummy gate, are used for power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable design for analog I/O buffer in the 0.18-�慆 CMOS process. Each ESD failure mechanism was inspected by SEM photograph in all analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic npn bipolar transistor between ESD clamp device and guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress. Chapter 7 presents several complex ESD failure mechanisms in the interface circuits of an IC product with multiple separated power domains. In this case, the MM ESD robustness can not achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV HBM ESD test. The ND-mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, junction filament, and contact destroy of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events in chapter 7. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-�慆 CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively. Chapter 8 concludes the achievement in this dissertation, and suggests several future works in this research field. In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of fabricated test chips have demonstrated the performance improvement. The achievement of this dissertation has been published in several international journal and conference papers. Several innovative designs have been applied for patents.
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Chi-Ming, Chan, and 詹啟明. "An Investigation on the Failure Modes of Reliability Tests on Microelectronic Packaging-Chip on Film." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/91891383450326928823.
Full textAbstract:
碩士義守大學
材料科學與工程學系
91
Abstract COF( Chip On Foil ) is the technical that flips the chip then bond it onto the flex circuit board. It also means to bond the LCD driver IC and SMD components onto the flex circuit board directly without using the rigid board, in order to reach the application goals of slight weight and small product outline. The ranges of major applications are subjected to a mobile phone and small size LCD products. The study purpose of this paper was investigating the defects mode of COF micro packaging by Chemical reaction on Cu trace during high temperature, high humidity and bias aging experiment point of view. This reaction was resulting the Cu ion dissolved in above environments and the major media elements were from both Halogen content of encapsulation and thin film surface. In the meantime, the driving force of electric filed will increase the dissolving speed of Cu ion from Cu trace then make the Cu ion migration from positive leads to negative leads, especially in the high temperature environment. These activities caused the electrodes insulation resistance decreasing rapidly, and influenced to the product electrical function in the meantime. On the other hand, Cu trace corrosion was also occurred by the same conditions above, high temperature and high humidity. Although the influence of corrosion is not so serious as Cu migration in product function point of view. But this phenomenon perhaps causes the both defects of conductor resistance increasing and product cosmetic concern. In these experiments, we implement some pre-treatment conditions that are focusing as follows: 1, To increase the adhesive strength of interface between the encapsulation material and foil by surface roughness modification. This modification will decrease the moisture penetration into the gap between the encapsulation material and foil surface. 2, To remove the residual ion on foil surface by ultrasonic energy within DI water. The critical bond strength between ion and foil surface was easily removed by proper ultrasonic energy. 3, The different plating material of Cu trace affects the reliability results.. 4, The different base material and suppliers of COF affects the reliability results The specimens were treated by above conditions (Plasma / Ultrasonic DI water cleaning) then applying high temperature (135 o C) and high humidity (85% RH) with bias (40V DC) in the environment of two times atmosphere pressure and 96 hours.. Take observation by Scanning Electrical Microscope (SEM) to find the mechanism of ion migration and copper corrosion for further improvement considerations.
35
Vogt, Johannes. "Die Untersuchung der putativen Mechanosensor-Komponenten Melusin und T cap und deren Einfluss auf die elektromechanische Kopplung im Kardiomyozyten bei adaptiver und maladaptiver Hypertrophie." Doctoral thesis, 2017. http://hdl.handle.net/11858/00-1735-0000-0023-3EEE-A.
Full text
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Chuang, Yao-Chun, and 莊曜群. "Study of EM(Electromigration) failure modes at Sn/Cu cathode interface in Flip-chip solder joint." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/88675413014183696974.
Full textAbstract:
博士國立中央大學
化學工程與材料工程研究所
96
As the speed and function of the CPU continuous to increase, I/O count (Input-Output) also increases dramatically. According to the semiconductor roadmap, by 2007 the current density for each C4 solder bump will exceed 104 A/cm2. Two EM failure modes have been reported. The first one is voiding, which occurs at the solder/compound interface. The second EM failure mode is the EM-induced dissolution of the Cu metal bond pad or the Cu trace lines. The current density and the stressing temperature are the critical parameters for various EM failure modes. We found that the critical EM parameters, the current density and the stressing temperature, significantly influence various EM failure modes, for example, Cu consumption, voids formation and asymmetric interfacial compound formation in our experimental results. From the experimental results in this study, we build up a detail mechanism of EM effect on flip-chip Cu/Sn solder joint by analyzing the Cu atomic flux step by step. EM-induced Cu consumption, voids formation, and asymmetric interfacial compound formation can be well-defined and explained by this mechanism. Finally, we can define Z* of Cu in the Sn matrix is around 130 and establish a map for EM failure mode. The failure map is of important to those who design the flip-chip joint structure with an excellent reliability. In chapter 2, we investigate the Cu/Sn interface of flip-chip solder joints under current stressing. From the experimental results with different current densities at different temperatures, we find out the critical factors influence on flip-chip Cu/Sn solder joints and obtain important parameters for calculating EM flux. In chapter 3, we successfully fabricate crystalline Cu3Sn and Cu6Sn5 bulk compounds by liquid-electromigration method. Also, we observe EM effect on the Cu6Sn5 compound. Then, we discuss the detail mechanism of EM effect on Sn/Cu flip-chip solder joint and show how the atomic flux be calculted in every step in chapter 4. Moreover, voids formation, EM-induced Cu consumption, and asymmetric IMC formation can be well-defined by the equating atomic fluxes. Finally, we can define Z* of Cu and establish a failure map for EM failure mode in chapter 5.
37
Ho, Ping-Ju, and 何秉儒. "Study of electromigration failure mode in flip-chip solder joints with copper columns using Kelvin bump." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/80332312184141863188.
Full textAbstract:
碩士國立交通大學
加速器光源科技與應用碩士學位學程
101
As electronic products become smaller but have higher performance, three-dimensional integrate circuit（3DIC）has received more attention recently. Low bump height microbump is the key interconnection technology to build up the 3DIC. However, the electromigration（EM）behavior in the low bump height solder is still unclear. In this study, the Sn2.3Ag solder joint which bump height is 15 μm were used to observe the failure mode in the low bump height case. To precisely monitor the different stages of failure during accelerated EM testing, a specific Kelvin bump structure is designed and fabricated in these samples. While a 1.17 x 104 A/cm2 current density was applied at 150℃,the microstructures at different stages with the 3%、5%、10% and 20% resistance increase were obtained by scanning electron microscopy（SEM）. The resistance obtained by Kelvin bump structure showed three different stages, which differs from the results of traditional flip-chip solder joints. Voids formed in the interface of under-bump-metallization（UBM）and intermetallic compounds. With the proper designed Kelvin bump structure and well controlled test conditions, the different stages during EM test can be studied systematically. In this study, we also use x-ray diffraction in National Synchrotron Radiation Research Center`（NSRRC）to study the strain change of silicon die after different current stressing time, to find out the relationship between strain and failure mode.
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Pai, Hsiang-Ting, and 白祥廷. "HFSS Simulation for Predicting the Failure Factors in Plasma Treatment and Chip Delamination in Semiconductor Industry." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/xjc4aq.
Full textAbstract:
碩士國立中山大學
機械與機電工程學系研究所
107
There are many processes in the semiconductor wire packaging process, including conductive adhesive dripping, die attaching, oven baking, plasma cleaning, die wire bonding and compound packaging. The semiconductor packaging factory found that under the same process conditions, some manufacturers'' dies were delam after the package was completed. Semiconductor manufacturers did not get a systematic factor in unanticipated grain delamination, so this study sought to understand the cause of delamination and propose a model for correlation prediction. In order to understand the delamination of the dies, this study found that the plasma system carrier in the semiconductor packaging process line is a stainless-steel conductor rail. This study presents a hypothesis for the stainless steel rail. This hypothesis is that when the conductor rail is in electrical contact with the copper lead frame, the conductor rail and the copper lead frame are at equipotential. When plasma processing the wafer, the plasma generated by the plasma machine will be relatively uneven on the die surface and the plasma will tend to be applied to the corner. This phenomenon can seriously cause uneven surface treatment on the wafer and insufficient application in some areas of dies. This hypothesis was verified by experiments on the production line, and the problem of the production line was fully solved by replacing the metal conductor rail to the insulated rail. This study measured the surface morphology and surface energy of the four kinds of dies provided by the manufacturer. As a result, it was found that the cause of the delamination was caused by the metal rail, and the microstructure on the surface of the dies surface caused uneven plasma distribution. For the above findings, this study uses the finite element analysis ANSYS® HFSS for systematic analysis. This systematic analysis of the electric field distribution is equivalent to the actual situation of the plasma distribution. The four parameters include different material rails and different forms of rails, different sizes of dies in the fixed size of the die pad and the different microstructure density of the dies surface. The results show that when the insulating rail and the surface microstructure are less than 60.68%, we can find that the variation of the electric field distribution is less than 3694.24 V/m. Below this certain value, the risk of delamination of the dies is relatively low. In addition, this study has developed a method to quickly analyze the presence or absence of microstructure on the dies surface. This method uses the principle of reflective grating to achieve rapid analysis by discriminating the optical diffraction pattern. Therefore, this study has three major contributions. The first is to find that the track material has a great influence on the plasma and electric field gradient. The second is to predict the delamination relationship between the epoxy molding compound and the dies in the packaging process industry by means of a finite element analysis and measurement of the surface topography. The third is the development of an optical diffraction method for this study to quickly predict whether the dies has a high risk of delamination.
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Chao, Chia-Hung, and 趙家宏. "Electromigration Failure Modes Study in Flip-Chip SnAg Solder Joints under Constant-Temperature / Different-Current Density Condition." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/57204567152493953226.
Full textAbstract:
碩士國立交通大學
工學院半導體材料與製程設備學程
100
As the size of consumptive electronic products continues to shrink, Flip Chip ICs also have to miniaturization. However, shrinking the size of solder bump is similar to the change of current density. We will discuss the effect of solder bump by elecromigration under different current density. In this study, we applied current stress of 0.8A、1.0A and 1.2A respectively on lead-free SnAg solder joints at 100℃. And we observed the cross-section of specimen for various stages and analyzed the failure modes for each solder bump . In experimental result, for the bump without current stressing, we found the formation of void causing by Cu UBM consumption which was affected by thermomigration effect. And we demonstrated (Cu,Ni)6Sn5 accumulation in current crowding region for the bump with an upward electron flow. Then, we found not only the formation of pancake-type void, but also destruction of IMC on the bump with a higher current density downward electron flow.
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Lin, Chung-Kuang, and 林宗寬. "Electromigration in flip-chip solder joints: Effect of temperature on failure mechanism and analysis of bump resistance curves." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/3ysq4b.
Full textAbstract:
博士國立交通大學
材料科學與工程學系所
102
Temperature-dependent electromigration failure was investigated in solder joints with Cu metallization at 126°C, 136°C, 158°C, 172°C, and 185°C. At 126°C and 136°C, voids formed at the interface of Cu6Sn5 intermetallic compounds and the solder layer. However, at temperatures equal 158°C or greater than, extensive Cu dissolution and thickening of Cu6Sn5 occurred, and few voids were observed. We proposed a model considering the flux divergence at the interface. At temperatures below 131°C, the electromigration flux leaving the interface is larger than the in-coming flux. Therefore, voids formed at the interface. Yet, the in-coming Cu electromigration flux surpasses the out-going flux at temperatures above 131°C. This model successfully explains the experimental results. This study also examines the formation of Sn-rich phases in the matrix of Cu-Sn-Ni intermetallic compounds (IMCs) after current stressing of 1.2 × 104 A/cm2 at 160°C. The Sn-rich phases were formed at the cathode end of the solder joints with Cu metallization, and this formation was attributed to the decomposition of Cu6Sn5 IMCs. When the Cu6Sn5 IMCs were transformed into Cu3Sn during current stressing, Sn atoms were released. Due to the insufficient supply of Cu atoms, Sn atoms accumulated to form Sn-rich phases among the Cu-Sn-Ni IMCs. Resistance curves play a crucial role in detecting damage of solder joints during electromigration. In general, resistance increases slowly in the beginning, and then rises abruptly in the very late stage; i.e., the resistance curve behaves concave-up. However, several recent studies have reported concave-down resistance curves in solder joints with no satisfactory explanation for the discrepancy. In this study, electromigration failure mode in Sn2.5Ag solder joints was experimentally investigated. The bump resistance curve exhibited concave-down behavior due to formation of IMCs. In contrast, the curve was concave-up when void formation dominated the failure mechanism. Finite element simulation was carried out to simulate resistance curves due to formation of IMCs and voids, respectively. The simulation results indicated that the main reason causing the concave-down curve is rapid formation of resistive Cu6Sn5 IMCs in the current-crowding region, where resistivity is nine times larger than that of Cu. Therefore, when Cu reacted with Sn to form Cu6Sn5 IMCs, the resistance increased abruptly, resulting in the concave-down resistance curve. Cu3Sn was constantly found in the solder joint after current stressing. In this study, two different types of Cu3Sn formed according to the stressing temperature of solder joints. The solder joint was under 1.30 × 104 A/cm2 current stressing test at 170°C, the solder joint could transform to layer Cu3Sn joints. However, when the stressing temperature increased to 222°C and the current density was 2.27 × 104 A/cm2, an interesting porous Cu3Sn formed at the solder joint. The formation mechanism of porous Cu3Sn, Could be explained by the phase transformation and side wall wetting phenomenon.
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Lin, Kun. "Atomic Force Microscopy (AFM) based Method Applications in Ultra Large Scale Integrated Chip (ULSI) for Semiconductor Failure Analysis." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1601200800182600.
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Lin, Kun, and 林坤. "Atomic Force Microscopy (AFM) based Method Applications in Ultra Large Scale Integrated Chip (ULSI) for Semiconductor Failure Analysis." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/17885638944989278453.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
96
Atomic Force Microscopy (AFM) based method of this thesis was indicated and established for its possible applications in semiconductor investigation. Based on three successful published papers (ISTFA: International Symposium for Testing and Failure Analysis), the AFM system is clear and accurate to identify the semiconductor failure root cause and summarize these results. Multiple scanning probing microscopy methods were maturely developed and accomplished for advanced nanometer process investigation. E.g. Magnetic Force Microscopy, Scanning Capacitance Microscopy, Current-Mapping Conductive-AFM applications would be introduced and applied in this thesis. Six published semiconductor failure analysis cases were detailed described for each experiment in this thesis. Case-1: Thin LOCOS did not block implant induced P+ bridge caused DC standby high current failure. Case-2: N type dopant was found at P+ area caused single device fail. Case-3: Possible solution for well inspection in advanced nanometer process. Case-4: Bipolar Vertical PNP Beta Loss by silicide margin short fail issue. Case-5: CMOS Chip Power Leakage by photo-resistor bubble fail issue. Case-6: Nano-scale extra-shallow junctions suffered silicide roughness induced vertical junction leakage failure issue. Based on these real applications and evidences, AFM has been becoming a powerful and new generation technique for physical failure analysis investigation. This thesis would like to introduce each detail and research in the AFM based method application.
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譚志祥. "Electromigration Failure Time and Micro-structure Study in Flip-Chip SnPb Solder Joints by Different Pre-aging Times." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/37265075355241590503.
Full textAbstract:
碩士國立交通大學
工學院碩士在職專班半導體材料與製程設備組
99
Flip-chip technology has become a mainstream trend in advanced electronic packaging because of its capability of higher I/O density and smaller package size. With higher current and smaller size trends, electromigration in flip-chip solder has become an critical of reliability concern. The effect of pre-aging on electromigration is investigated in this study using flip-chip SnPb solder joints. The solder joints were pre-aged at 170°C for 25 h, 50 h, and 100 h, and then they were subjected to electromigration tests of 1.0 A at 150°C. It was found that the average failure time increased when the joints were pre-aged for no pre-aged, 25 h, 50 h and 100 h. It is proposed that the major contributor to the prolonged failure time may be the densification of the nickel and copper under-bump metallization (UBM) and the solder due to the aging treatment. The pre-aging treatment at 170°C may stabilize the microstructure of the solder. The vacancies in the solder might be annihilated during the heat treatment, causing a slower diffusion rate. In addition, the IMC structure became thicker after the pre-aging process. Thus, the thicker IMC structure may lead to smaller current crowding effect and slower consumption rates of the nickel and copper layers, resulting in the enhancement of electromigration resistance.
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LIN, YU-TING, and 林予婷. "In-situ Observation of Electromigration Induced Failure and Intermetallic Compounds Growth Mechanisms for Chip Scale Packages with Different Structures." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/nx5ke9.
Full textAbstract:
碩士國立高雄應用科技大學
化學工程與材料工程系碩士在職專班
104
In this study we observed the electromigration-induced (EM-induced) failure and intermetallic compound (IMC) growth mechanism in-situ with six different structures. The Chip Scale Packages (CSPs) were mounted with printed circuit boards (PCB) then tested in EM testing system and monitored the resistances with 0.7 A at 160℃. Two kinds of typical failure modes were observed for the samples without UBM after current stressing. One is the Cu trace dissolution and the other is the voids formation at IMC and SnAgCu solder ball (SAC) interface due to unbalance atomic fluxes. Some UBM consumed for the samples with UBM after current stressing. The current were spread by UBM and reduced 54%~73% current crowding effect as the simulation results. The Cu6Sn5 and Cu3Sn IMCs growth mechanism is quite different when Ni atoms participate in the interfacial reaction. The lower chemical potential (Cu,Ni)6Sn5 IMC formed and induced more Cu atoms diffused from Cu3Sn into (Cu,Ni)6Sn5 IMC then retarded the growth rate of Cu3Sn IMC. The current spreading simulation, detailed mechanisms of two failure modes and Cu6Sn5/Cu3Sn IMCs growth mechanisms were investigated in this study. Finally the calculation of the effective charge number (Z*) for Ni in SAC was between at -1.62 to -5.10. Keywords: Electromigration(EM), Intermetallic compound(IMC), Chip scale packages(CSPs), Under Bump Metallization(UBM), Effective charge number (Z*)
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Weiss, Alexander. "Effiziente externe Beobachtung von CPU-Aktivitäten auf SoCs." Doctoral thesis, 2014. https://tud.qucosa.de/id/qucosa%3A28996.
Full textAbstract:
Die umfassende Beobachtbarkeit von System‐on‐Chips (SoCs) ist eine wichtige Voraussetzung für das effiziente Testen und Debuggen eingebetteter Systeme. Ausgehend von einer Analyse verschiedener Anwendungsfälle ergibt sich ein Katalog von Anforderungen an die Beobachtbarkeit von SoCs. Ein wichtiges Kriterium ist hier die Vollständigkeit der Beobachtung und umfasst die Aktivitäten der CPU (ausgeführte Instruktionen, gelesene und geschriebene Daten, Verhalten des Caches, Ausführungszeiten), des Bussystems und von Umgebungsbedingungen.
Weitere Kriterien sind die Echtzeitfähigkeit und die Kontinuität der Beobachtung sowie die gleichzeitige Durchführung verschiedener Beobachtungsaufgaben. Dabei soll es zu einer möglichst geringen Beeinflussung des SoCs kommen. Weitere wichtige Aspekt sind die Kosten der Lösung, die Universalität, die Skalierbarkeit sowie die Latenz der Verfügbarkeit der Beobachtungsergebnisse.
Für viele Anwendungen, besonders in sicherheitskritischen Bereichen, muss zudem nachgewiesen werden, dass das Beobachtungsverfahren kein Fehlverhalten des SoCs bewirkt bzw. ein solches maskiert. Eine besondere Herausforderung stellen Multiprozessor‐SoCs (MPSoCs) dar, da hier die Kommunikation zwischen den einzelnen CPUs im Inneren des SoC stattfindet und entsprechend schwierig für einen externen Bobachter sichtbar zu machen ist.
Der Stand der Technik zur Beobachtung von SoCs wird im Wesentlichen durch zwei Verfahren dargestellt. Bei der Software‐Instrumentierung wird zum funktionalen Programmcode zusätzlicher Code hinzugefügt, welcher zur Beobachtung des Programms dient. Diese Methode ist einfach und universell anwendbar, erfüllt aber die genannten Kriterien nur sehr eingeschränkt. Nachteilig ist hier der Ressourcenverbrauch im Falle des Verbleibs der Instrumentierung im fertigen Produkt. Wird die Instrumentierung nur temporär dem Code hinzugefügt, muss sichergestellt werden, dass das Beobachtungsergebnis auch für den finalen Code anwendbar ist – was besonders bei ressourcen‐abhängigen Integrationstests nur schwierig erfüllbar ist.
Eine alternative Lösung stellt eine spezielle Hardware‐Unterstützung in SoCs („embedded Trace“) dar. Hier werden im SoC Zustandsinformationen (z.B. Taskwechsel, ausgeführte Instruktionen, Datentransfers) gesammelt und mittels Trace‐Nachrichten an den Beobachter übermittelt. Dabei stellt die Bandbreite, die zur Ausgabe der Trace‐Nachrichten vom SoC verfügbar ist, ein entscheidendes Nadelöhr dar ‐ im SoC sind viel mehr den Beobachter interessierende Informationen verfügbar als nach außen transferiert werden können.
Damit haben beide dem gegenwärtige Stand der Technik entsprechende Beobachtungsverfahren eine Reihe von Einschränkungen, die sich besonders bei der Vollständigkeit der Beobachtung, der Flexibilität, der Kontinuität und der Unterstützung von MPSoCs zeigen.
In dieser Arbeit wird nun ein neuer Ansatz vorgestellt, welcher gegenüber dem Stand der Technik in einigen Bereichen deutliche Verbesserungen bietet. Dabei werden die Trace‐Daten nicht vom zu beobachtenden SoC direkt, sondern aus einer parallel mitlaufenden Emulation gewonnen. Die Bandbreite der für die Synchronisation der Emulation erforderlichen Daten ist in vielen Fällen deutlich geringer als bei der Ausgabe von umfassenden Trace‐Nachrichten mittels „embedded Trace“‐Lösungen. Gleichzeitig ist eine vollständige, äußerst detaillierte Beobachtung der Vorgänge innerhalb des SoC möglich. Das neue Beobachtungsverfahren wurde mittels verschiedener FPGA-basierter Implementierungen evaluiert, hier konnte auch die Anwendbarkeit für MPSoCs gezeigt werden.
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Chang, Yuan-Wei, and 張元蔚. "Study of Failure Mechanisms in Flip-Chip Solder Joints and Microbumps under Electromigration Using Kelvin Bump Structures and Finite-Element Analysis." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/25573236318844434993.
Full textAbstract:
博士國立交通大學
材料科學與工程學系所
102
In this study, three types of solder bump samples with Kelvin bump structures were employed to monitor non-destructively the evolution of resistance during electromigration (EM) testing. The first type of sample was flip-chip bumps. The bump resistance was found to be less than 1 mΩ and increase as a concave-up curve. After the bump resistance increased to more than 10 times its initial value, it started to grow rapidly and then failure. The corresponding microstructure showed void nucleation and propagation. The void first formed near the current crowding spot and then grew along the interface between the intermetallic compound (IMC) and the solder. At the end stage of EM testing, phase coarsening caused by EM retarded the failure, and the void split into two parts. The relation between the remaining contact area and the bump resistance was calculated. The second type of sample was 6-μm microbumps. The microbump resistance curve was concave-down. It started around 15 mΩ, increased rapidly in the beginning, and then reached a constant value after 400 hr of testing. The increase in the early stage of testing was around 5 mΩ, which was reasonable when compared with the results of finite-element models (FEMs). During EM testing, the cathode-side under-bump-metallization (UBM) reacted with the solder and transformed the entire microbump into Ni3Sn4. Ni3Sn4 has better EM resistance than the solder and caused the bump resistance to remain at a constant value. The bump resistances at different angles indicated that current crowding still took place, but in the Cu UBM and not in the solder. The complete voltage drop across the microbump was the value obtained at 0°. However, the bump resistance obtained at 0° was 7 times larger than that measured at 180°. That is, the RC delay caused by microbump is actually very large. For simplicity of description on the relation between microbump resistances, crowding ratio, and structural dimensions, a numerical model was built. The expressions of microbump resistance and the crowding ratio were also obtained. The last type of sample was the 10-μm microbumps. The resistance behaved first concave-down and then concave-up because the solder was too much for the interposer-side UBM to consume. The concave-down curve was first observed for the same reason as that of the low-bump-height case. However, the height of the solder was around 10 μm, which was too high for the interposer-sider UBM to react with. When the electrons flow upward (from interposer to chip), the interposer-side UBM, 2-μm Ni, was the cathode side. Driven by EM, the-2μm Ni quickly dissolved into the solder. After the 2-μm Ni ran out, the void was formed, causing the bump resistance curve to become concave-up again. The solder height affected the failure mechanism. When the solder height was 25 μm, void propagation was the main failure mechanism. When the solder height decreased to 10 μm, the mechanism became the combination of void propagation and IMC growth. When it was 6 μm, the failure mechanism changed to IMC growth only. The FEM described clearly the evolution of current density distribution at various stages of EM and therefore helped predict accurately the failure mechanism. Moreover, the Kelvin bump structure is compatible with the generally used daisy chain structure. Both bump resistance and daisy chain resistance could be obtained at the same time.
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Kuo, Shih-Hua, and 郭士華. "A Statistical Approach for Identifying System-Level Failures based on Stressed On-Chip-Clock Test Mismatch Count Analysis." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/3284ee.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
103
We describe a novel scheme where scan patterns are applied under stress conditions to force incorrect outputs from digital chips. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip’s “analog” failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins.
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Ribeiro, Inês Tomé. "Breaking the barriers of HFpEF: a New "Blood Vessel on a Chip" Model." Master's thesis, 2018. http://hdl.handle.net/10316/82677.
Full textAbstract:
Dissertação de Mestrado em Investigação Biomédica apresentada à Faculdade de MedicinaUma das grandes conquistas na sociedade prende-se com o aumento da esperança de vida e, consequentemente, com o envelhecimento. No entanto, as doenças relacionadas com a idade, tal como a insuficiência cardíaca, tornaram-se um sério problema de saúde pública, com um fardo nos sistemas de saúde e a nível socioeconómico. Metade dos doentes com insuficiência cardíaca apresentam fração de ejeção preservada (ICFEp) constituindo, assim, um novo fenótipo deste síndrome. O envelhecimento e a elevada prevalência de comorbilidades nos doentes com ICFEp, especialmente obesidade e hipertensão, induzem um estado inflamatório sistémico que culmina com disfunção endotelial e stress oxidativo. Apesar no surgimento deste novo paradigma, a sua fisiopatologia não é completamente entendida, particularmente no que concerne ao endotélio vascular. Além do mais, poucos são os biomarcadores específicos descritos na literatura e a falta de terapêuticas eficazes. Recentemente, o rato obeso ZSF1 foi descrito como um novo modelo cardiometabólico para o estudo da ICFEp, por apresentar todas as características da doença.Nesta tese induzimos inflamação em células endoteliais utilizando meio condicionado de ratos ZSF1 e soro de doentes com ICFEp, salientando o papel do secretoma para o desencadeamento da doença. Além do mais, confirmarmos que existe disfunção do miocárdio em ratos obesos ZSF1 e em doentes com ICFEp, apesar do endotélio não ser o único interveniente. De facto, a comunicação intercelular ocorre e pode ser uma característica essencial para a progressão da doença. Finalmente, descrevemos uma nova abordagem para desenvolver um modelo in vitro utilizando células progenitoras endoteliais adultas. Ao representarem uma fonte mais fidedigna e retratarem o que acontece na condição humana, abrem um novo caminho para estudos sobre a fisiopatologia da ICFEp e estudo de fármacos.No geral, apresentamos novas abordagens in vitro para desencadear a doença em células endoteliais normais e os nossos dados fornecem novos conhecimentos sobre o endotélio vascular na ICFEp.
One of the greatest achievements in society was the prolongation of life expectancy and progressive ageing. However, aged-related diseases such as heart failure emerged as a serious public health problem, with an increased socio-economic and healthcare burden. Half of the patients with heart failure have preserved ejection fraction (HFpEF), constituting a new phenotype of this syndrome. Ageing and high prevalence comorbidities in HFpEF patients, especially obesity and hypertension, are known to induce a systemic inflammatory state that results on endothelial dysfunction and oxidative stress. Although a new paradigm for HFpEF development has emerged, its pathophysiology is still not completely understood, particularly regarding the vascular endothelium. In addition, few specific biomarkers have been described and currently there are no effective therapies available. Recently, a new animal model of ZSF1 obese rats have been used as a cardiometabolic model for study the disease, since they have shown to develop all the features of HFpEF.In this thesis we induced inflammation on endothelial cells using conditioned media from ZSF1 rats and serum from HFpEF patients, pointing out the role of secretome on triggering the disease. In addition, we confirmed that myocardial dysfunction is present on ZSF1 obese rats and HFpEF patients, but endothelium is not the only player. In fact, cell-cell communication occurs and might be an important feature for progression of the disease. Finally, we described a new approach for developing an in vitro model using adult endothelial progenitor cells. This represent a more reliable source of what is happening in the human condition and open new opportunities for biological studies regarding pathophysiology of HFpEF and drug screening.Overall, we presented several in vitro approaches for priming the disease on healthy endothelial cells and our data provided new insights on the vascular endothelium field of HFpEF.