Dissertations / Theses on the topic 'CHIRP INPUT'

In order to cope up with the ever increasing demand for larger transmission bandwidth, Radio over Fiber technology is a very beneficial solution. These systems are expected to play a major role within future fifth generation wireless networks due to their inherent capillary distribution properties. Nonlinear compensation techniques are becoming increasingly important to improve the performance of telecommunication channels by compensating for channel nonlinearities. Indeed, significant bounds on the technology usability and performance degradation occur due to nonlinear characteristics of optical transmitter, nonlinear generation of spurious frequencies, which, in the case of RoF links exploiting Directly Modulated Lasers , has the combined effect of laser chirp and optical fiber dispersion among its prevailing causes. The purpose of the research is to analyze some of the main causes of harmonic and intermodulation distortion present in Radio over Fiber (RoF) links, and to suggest a solution to reduce their effects, through a digital predistortion technique. Predistortion is an effective and interesting solution to linearize and this allows to demonstrate that the laser’s chirp and the optical fiber’s dispersion are the main causes which generate harmonic distortion. The improvements illustrated are only theoretical, based on a feasibility point of view. The simulations performed lead to significant improvements for short and long distances of radio over fiber link lengths. The algorithm utilized for simulation has been implemented on MATLAB. The effects of chirp and fiber nonlinearity in a directly modulated fiber transmission system are investigated by simulation, and a cost effective and rather simple technique for compensating these effects is discussed. A detailed description of its functional model is given, and its attractive features both in terms of quality improvement of the received signal, and cost effectiveness of the system are illustrated.

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (page 49).
This thesis describes the design of a novel on-chip input driver for a SAR ADC. The driver achieves performance gains relative to off-chip alternatives by being integrated into the signal path of the ADC between the sampling switches and sampling capacitor. This placement allows for auto-zeroing the offset of the driver and reducing flicker noise. Additional performance benefits are possible because the driver can be optimized for the specific load and timings of the ADC. The most important benefit of an on-chip input driver is that it simplifies the design process for the ADC user by eliminating the external op-amp and reducing the constraints on the external filter by reducing input current load. Design simplicity is especially important to users in high-voltage SAR ADC applications, so the input driver is designed for an ADC with a +/- 10.24 V input range and +/- 15 V supply rails. This high-voltage input relaxes noise and headroom constraints, but makes device overvoltage a significant concern. The driver is designed in a BiCMOS process, and simulation results with a computer-modeled ADC are presented here. In these simulations, the driver achieves a THD of -124.7 dB at 2 kHz and a noise voltage spectral density of 5.5 nV / [square root of] Hz with a power consumption of 27.6 mW. The LT1469, an example of a state-of-the-art external input driver, has a THD of -123 dB at 2 kHz, a noise voltage spectral density of 5 nV / [square root of] Hz, and a power consumption of 123 mW.
by Kevin Robert Linke.
M. Eng.

Epigenetic modifications, such as DNA methylation and histone modifications, play important roles in gene expression and regulation, and are highly involved in cellular processes such as stem cell pluripotency/differentiation and tumorigenesis. Chromatin immunoprecipitation (ChIP) is the technique of choice for examining in vivo DNA-protein interactions and has been a great tool for studying epigenetic mechanisms. However, conventional ChIP assays require millions of cells for tests and are not practical for examination of samples from lab animals and patients. Automated microfluidic chips offer the advantage to handle small sample sizes and facilitate rapid reaction. They also eliminate cumbersome manual handling. In this report, I will talk about three different projects that utilized microfluidic immunoprecipitation followed by next genereation sequencing technologies to enable low input and high through epigenomics profiling. First, I examined RNA polymerase II transcriptional regulation with microfluidic chromatin immunoprecipitation followed by next generation sequencing (ChIP-seq) assays. Second, I probed the temporal dynamics in the DNA methylome during cancer development using a transgenic mouse model with microfluidic methylated DNA immunoprecipitation followed by next generation sequencing (MeDIP-seq) assays. Third, I explored negative enrichment of circulating tumor cells (CTCs) followed by microfluidic ChIP-seq technology for studying temporal dynamic histone modification (H3K4me3) of patient-derived tumor xenograft on an immunodeficient mouse model during the course of cancer metastasis. In the first study, I adapted microfluidic ChIP-seq devices to achieve ultrahigh sensitivity to study Pol2 transcriptional regulation from scarce cell samples. I dramatically increased the assay sensitivity to an unprecedented level (~50 K cells for pol2 ChIP-seq). Importantly, this is three orders of magnitude more sensitive than the prevailing pol2 ChIP-seq assays. I showed that MNase digestion provided better ChIP-seq signal than sonication, and two-steps fixation with MNase digestion provided the best ChIP-seq quality followed by one-step fixation with MNase digestion, and lastly, no fixation with MNase digestion. In the second study, I probed dynamic epigenomic changes during tumorigenesis using mice often require profiling epigenomes using a tiny quantity of tissue samples. Conventional epigenomic tests do not support such analysis due to the large amount of materials required by these assays. In this study, I developed an ultrasensitive microfluidics-based methylated DNA immunoprecipitation followed by next-generation sequencing (MeDIP-seq) technology for profiling methylomes using as little as 0.5 ng DNA (or ~100 cells) with 1.5 h on-chip process for immunoprecipitation. This technology enabled me to examine genome-wide DNA methylation in a C3(1)/SV40 T-antigen transgenic mouse model during different stages of mammary cancer development. Using this data, I identified differentially methylated regions and their associated genes in different periods of cancer development. Interestingly, the results showed that methylomic features are dynamic and change with tumor developmental stage. In the last study, I developed a negative enrichment of CTCs followed by ultrasensitive microfluidic ChIP-seq technology for profiling histone modification (H3K4Me3) of CTCs to resolve the technical challenges associated with CTC isolation and difficulties related with tools for profiling whole genome histone modification on tiny cell samples.
Ph. D.

Most modern control systems use digital controllers to ensure safe operation. We modify the traditional digital control system architecture to integrate a new component known as a trusted input/output processor (TIOP). TIOP interface to the inputs (sensors) and outputs (actuators) of the system through existing communication protocols. The TIOP also interface to the application processor (AP) through a simple message passing protocol. This removes any direct input/output (I/O) interaction from taking place in the AP. By isolating this interaction from the AP, system resilience against malware is increased by enabling the ability to insert run-time monitors to ensure correct operation within provided safe limits. These run-time monitors can be located in either the TIOP(s) or in independent hardware. Furthermore, monitors have the ability to override commands from the AP should those commands seek to violate the safety requirements of the system. By isolating I/O interaction, formal methods can be applied to verify TIOP functionality, ensuring correct adherence to the rules of operation. Additionally, removing sequential I/O interaction in the AP allows multiple I/O operations to run concurrently. This reduces I/O latency which is desirable in many control systems with large numbers of sensors and actuators. Finally, by utilizing a hierarchical arrangement of TIOP, scalable growth is efficiently supported. We demonstrate this on a Xilinx Zynq-7000 programmable system-on-chip device.
Master of Science
Complex modern systems, from unmanned aircraft system to industrial plants are almost always controlled digitally. These digital control systems (DCSes) need to be verified for correctness since failures can have disastrous consequences. However, proving that a DCS will always act correctly can be infeasible if the system is too complex. In addition, with the growth of inter-connectivity of systems through the internet, malicious actors have more access than ever to attempt to cause these systems to deviate from their proper operation. This thesis seeks to solve these problems by introducing a new architecture for DCSes that uses isolated components that can be verified for correctness. In addition, safety monitors are implemented as a part of the architecture to prevent unsafe operation.

This Master’s thesis process list of different finite element programs, which allows us to simulate process of material separation. We estimated their advantages and disadvantages in the end. In program ANSYS Ls-Dyna was created 3D model, in which we simulate process of orthogonal splinter machining and we study dependence of changes different input parameters (tool geometry, depth of cut, cutting speed) on the chip form and forces rate between tool and workpiece.

The use of full wave electromagnetic modeling and simulation tools allows for accurate performance predictions of unique RF structures that exhibit multi-dimensional scales. Full wave simulation tools need to cover the broad range of frequency including RF and terahertz bands that is focused as RF technology is developed. In this dissertation, three structures with multi-dimensional scales and different operating frequency ranges are modeled and simulated. The first structure involves nanostructured solar cells. The silicon solar cell design is interesting research to cover terahertz frequency range in terms of the economic and environmental aspects. Two unique solar cell surfaces, nanowire and branched nanowire are modeled and simulated. The surface of nanowire is modeled with two full wave simulators and the results are well-matched to the reference results. This dissertation compares and contrasts the simulators and their suitability for extensive simulation studies. Nanostructured Si cells have large and small dimensional scales and the material characteristics of Si change rapidly over the solar spectrum. The second structure is a reconfigurable four element antenna array antenna operating at 60 GHz for wireless communications between computing cores in high performance computing systems. The array is reconfigurable, provides improved transmission gain between cores, and can be used to create a more failure resilient computing system. The on-chip antenna array involves modeling the design of a specially designed ground plane that acts as an artificial magnetic conductor. The work involves modeling antennas in a complex computing environment. The third structure is a unique collar integrated zig-zag antenna that operates at 154.5 MHz for use as a ground link in a GPS based location system for wildlife tracking. In this problem, an intricate antenna is modeled in the proximity of an animal. Besides placing a low frequency antenna in a constricted area (the collar), the antenna performance near the large animal body must also be considered. Each of these applications requires special modeling details to take into account the various dimensional scales of the structures and interaction with complex media. An analysis of the challenges and limits of each specific problem will be presented.

ABSTRACT The behaviour of the control system under parameter uncertainties is of utmost importance in industrial applications. For designing a robust control system, a necessary effort has to be carried out for achieving desirable control characteristics irrespective of the operating conditions. With the shortcomings in the design of a conventional controller, a theory with proper mathematical background is of imminent need for a control designer. The application of a high speed switching with a suitable switching logic provides attractive feature of possessing a new property which is not present in the substructures. This fundamental idea developed into Variable Structure theory. Having derived from variable structure, sliding mode control is the operational tool of variable structure control. The design of sliding surface is important for control of the system during sliding mode. The distinguishing feature of sliding mode is the independence of the system against model dynamics which testifies the robustness with respect to parametric uncertainties, bounded disturbances and noise. Numerous applications of sliding mode in controller design is already proposed. The requirement of all states of the system for effective control was an inherent drawback with respect to practical system. Estimation of non-measurable states using the input and information of any measurable state is the fundamental idea of an observer. Luenberger observer for estimation of states is not robust to handle parametric variations and nonlinearities present in the system. Hence, the fundamental idea of sliding mode for observer design is used. This thesis describes the general framework for the design of sliding mode observer with focus on nuclear reactor system. Point Reactor Kinetics (PRK) model which is derived from the neutron diffusion equation is the model to be considered. With only nuclear reactor power as a measurable quantity, the delayed neutron precursor concentration, reactivity, external neutron source, xenon and iodine concentration is estimated. Out of large number of applications of sliding mode, fault detection in a nuclear and non-nuclear component with actuator and sensor faults is carried out. Residual evaluation is carried out using sliding mode observer while validating the residual signal at different instances where fault occurs. The inherent drawback of chattering due to formulation of first order sliding mode is minimized by using smooth functions. This method would forgo the fundamental idea of robustness of sliding mode. An attempt is made to present the application of higher order sliding mode which minimizes or sometimes eliminates chattering without compromising the robustness. The state estimation of a nuclear reactor system using Super Twisting algorithm is in good agreement with simulated state from PRK model. The independence of states with respect to initial conditions along with faster convergence time is achieved by the application of uniform second order sliding mode algorithm validated using the PRK model.

碩士
國立臺灣大學
電子工程學研究所
91
The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as well as the delay skew of the paths. In this thesis, we propose a hierarchical top-down method for the block and input/output buffer placement in flip-chip design. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the following two steps: the alternating and interacting global optimization step and the partitioning step. The global optimization step places modules based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the modules are divided into two groups according to their coordinates and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of modules, defined by the ratio of the total module area to the chip area. At last, we refine the placement by perturbing modules inside a subregion as well as in different subregions. Compared with the placement using the B*-tree alone, our method obtains significantly better results, with an average cost of only 48.4\% of that obtained by using the B*-tree alone.

碩士
國立臺北科技大學
電子工程系
106
End user usual has two devices used for works and communications today, first one was Notebook and the other was smart mobile device. Both has 3.5mm Audio Jack functions with earphone, but notebook doesn’t support this earphone control circuit. Thus, this paper proposed a chip design of passive input device signal detection for earphone controller. Chip works by detecting the microphone bias voltage. Each of bottoms has different resistor connection between microphone and ground. Once the bottom was triggered, the comparators sense the input voltage comparing with reference voltage to decide the proper region. Basically, this architecture uses the bandgap for reference voltage and using comparators to generate four digital control signals (GPIO). And thus, the notebook can use these signals to carry out different operations predefined by user. For verifying, this chip is implemented with TSMC 0.18μm 1P4M CMOS process, which power consumption is 16.1 mW and chip size is 0.63 x 0.63 mm2 (including PAD). The experimental results show that we can easily control NB by earphone controller with low cost and this architecture can be applied to future smart devices.

As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC routers for better performance and power efficiency, Spin-Torque Transfer Magnetic RAM (STT-MRAM) is regarded as a promising solution due to its nature of high density and near-zero leakage power. Previous work that adopts STT-MRAM in designing NoC router input buffer shows a limitation in minimizing the overhead of power consumption, even though it succeeds to some degree in achieving high network throughput by the use of SRAM to hide the long write latency of STT-MRAM. In this thesis, we propose a novel input buffer design that depends solely on STT-MRAM without the need of SRAM to maximize the benefits of low leakage power and area efficiency inherent in STT-MRAM. In addition, we introduce power-efficient buffer refreshing schemes synergized with age-based switch arbitration that gives higher priority to older flits to remove unnecessary refreshing operations. On an average, we observed throughput improvements of 16% on synthetic workloads and benchmarks.

碩士
國立臺灣大學
電子工程學研究所
92
The flip-chip package gives the highest chip density of any packaging methods to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first-stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as well as the delay skew of the paths. In this thesis, we propose a two-stage placement method for the block and input/output buffer placement in flip-chip design. In the first stage, we apply simulated annealing using the B*-tree representation to minimize the maximum wirelength and obtain an initial feasible placement. In the second stage, we apply an iterative algorithm to improve the initial solution. In each iteration, we find the zero-skew position for each buffer to minimize the signal delay skew between the buffer and one with the maximum signal delay. The iterative improvement terminates when all of the signal delay skews of input/output buffers are under an user-specified range. Compared with the placement using the B*-tree alone and the work in [16], our method obtains significantly better results. The B*-tree based algorithm ([16]) results in overall cost of 32.23 times (14.08 times) of that of our algorithm. In terms of running time, the B*-tree based algorithm ([16]) needs 15.34 times (10.47 times) of our CPU time. In particular, setting an appropriate grid size and a signal skew range, we can even get a placement with zero signal skews for all input/output buffers.

碩士
國立臺灣科技大學
電子工程系
102
This paper presents a 1.8-V 10-bit 20MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in the TSMC 0.18-um CMOS process. By applying a single-sided switching method that reduces DAC switching energy, the proposed SAR ADC achieves lower power consumption. In order to avoid using an external high frequency clock to drive the ADC, asynchronous control logic is used. A pre-amplifier based comparator reduces the kickback noise from the logic circuit. A bootstrapped switch increases the sample linearity of the ADC. The SAR ADCs were simulated by HSPICE and SpectreRF. The 10-bit ADC was taped out by TSMC. The measured results for differential and integral nonlinearity of the 10-bit ADC are within 1.2/-0.4 LSB (Least Significant Bit) and -1.54~1.1LSB respectively at full sampling rate. The measurement results show an effective number of bits (ENOB) of 8.85-bits with a sampling frequency of 20 MHz at a 10 KHz input frequency. The chip area, including pads, is 0.57 mm2. Power consumption of this ADC is 910μW with a 1.8 V supply voltage.

碩士
國立臺北科技大學
電腦與通訊研究所
95
In the first part of this thesis, we present an integrated buck converter using hysteresis current controlled (HCC) techniques without slope compensation. The proposed current sensing circuit is very simple and only consists of few components, which can be designed easily. The designed buck converter using the current sensing circuit and HCC techniques can be stable even if the duty cycle is greater than 50%. The buck converter is implemented with 3.3-V TSMC 0.35μm CMOS DPQM processes, and the chip area is 2.33mm2 with PAD. In the second part of this thesis, we present a low-dropout linear regulator (LDO) with negative in-out voltage. The characteristic of proposed LDO is its very low quiescent current and ultra high DC gain. Therefore, the line/load regulation of designed LDO is great than other design. The LDO is implemented with 3.3-V TSMC 0.35μm CMOS DPQM processes, and the chip area is 0.45mm2 with PAD.

碩士
中華大學
工業管理學系碩士班
102
The LED industry involves four kinds of production processes which includeraw material side, upstream, midstream, and downstream. The LED Chip Manufacturers (LED-CM) is a part of the midstream and is a key role of the LED industry. In order to satisfy the various requirements of the downstream, the LED Chip Manufacturers (LED-CMs) are always the type ofMTO production. Their productionprocessesare not only complicated but also uncertain which makes low Hit Target Ratio (HT) and with a lot of variation. Therefore the critical issue of LED manufacturersusually confrontwith how to plan complementary inputs, during an insufficient output of a Make Order (MO) that means productionmanagers should make a decision for complementary inputs which specification of Epitaxy Wafer(EPI), and how many chip should put in, that could both reduce production cost and inventory burden.This thesis proposes a material model of complementary inputs, and to explore the optimal complementaryput in model. First, this study explains LED-CMs’various outputs and issues of HT, second uses a real-life LED-CM case to discuss feasible complementary input model todesign simulation and experiment scenario, toverify effectiveness of different models, and finally discover the optimal complementary inputs model, to offer the application for practitioners.

碩士
國立交通大學
電信工程研究所
99
This paper proposes three designs of antennas. One is the research of the on-chip antenna, another is the research of the novel structure for the decreasing side-lobe and increasing beam steering range leaky-wave antenna, the other is the search of the low relationship multi-input multi-output antenna (MIMO). For the first topic, a broadband millimeter-wave on-chip antenna is presented here. We design the proposed antenna by using the construction of monopole antenna. To reach the End-Fired radiation pattern, the reflector of the Yagi-Uda construction is used in the research. The proposed on-chip antenna has the combination of two constructions about monopole antenna and the part of the reflector in Yagi-Uda. Then, the second topic, a novel structure for leaky-wave antenna, is introduced here. To decrease back lobe, we can design slots on conventional leaky-wave antenna, and utilize the energy of the reflected wave of the leaky-wave antenna. Here, we design the monopole antenna on the open end of leaky-wave antenna. It can utilize the energy of the reflected wave of the leaky-wave antenna to composite the radiation pattern of leaky-wave antenna to increase frequency scanning range. Due to the reflected wave is guided to the monopole, the back lobe level can be decreased by the method. Finally, the third topic, the high isolation multi-input multi-output (MIMO) antenna is presented. We use some method to decrease the relationship between two antennas like orthogonal quadrature hybrid and resonator. Because the MIMO antenna is designed to apply to the personal motion communication device, the radiation pattern is designed to be omni-directional.