Journal articles on the topic 'Chip-compression ratio'
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1
Zhou, Jun, and Rong Di Han. "Experimental Investigation of Turning with Magnetized Cutting Emulsion." Key Engineering Materials 426-427 (January 2010): 225–29. http://dx.doi.org/10.4028/www.scientific.net/kem.426-427.225.
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The purpose of this study is to clarify the possibility of the turning process with the magnetized cutting emulsion. In particular, the effect of the magnetized cutting emulsion in turning process were examined through observation and measurement of the shape of the generated chips, machined surface integrity, cutting force and chip thickness compression ratio in a series of turning experiments. As a result, compared with dry turning and turning with cutting emulsion, the application of the magnetized cutting emulsion can decrease cutting force and chip thickness compression ratio, increases machined surface integrity.
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Deng, Wen Jun, Ping Lin, Zi Chun Xie, and Qing Li. "Analysis of Large-Strain Extrusion Machining with Different Chip Compression Ratios." Journal of Nanomaterials 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/851753.
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Large-Strain Extrusion Machining (LSEM) is a novel-introduced process for deforming materials to very high plastic strains to produce ultra-fine nanostructured materials. Before the technique can be exploited, it is important to understand the deformation behavior of the workpiece and its relationship to the machining parameters and friction conditions. This paper reports finite-element method (FEM) analysis of the LSEM process to understand the evolution of temperature field, effective strain, and strain rate under different chip compression ratios. The cutting and thrust forces are also analyzed with respect to time. The results show that LSEM can produce very high strains by changing in the value of chip compression ratio, thereby enabling the production of nanostructured materials. The shape of the chip produced by LSEM can also be geometrically well constrained.
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Li, Guo Ning, Yan Yan Liu, Shuang Li Han, and Long Xu Jin. "Design of the JPEG2000 Compression System Based on ADV212." Applied Mechanics and Materials 602-605 (August 2014): 2761–64. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2761.
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This article in detail on the basis of the algorithm of JPEG2000 standard upon, is put forward based on the FPGA embedded processor MicroBlaze and ADV212 compression chip with the combination of high speed, real time image compression scheme. Experiments show that the scheme can realize the data rate of 520 Mbps largest real-time compression of image data, when the image compression ratio is 53:1, reconstruction image PSNR value can reach 36 dB.
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Pawade, Raju, Avinash Khadtare, Dhanashree Dhumal, and Vishal Wankhede. "Machinability Assessment in High Speed Turning of High Strength Temperature Resistant Superalloys." Journal of Advanced Manufacturing Systems 18, no. 04 (November 19, 2019): 595–623. http://dx.doi.org/10.1142/s021968671950032x.
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The paper discusses the effect of cutting parameters and cutting tool material on chip compression ratio, cutting forces and surface roughness in turning of high strength temperature resistant superalloys (HSTR). The experiments were performed in dry cutting environment on precision CNC lathe with fixed depth of cut of 0.5[Formula: see text]mm. Analytical model is developed to determine chip segmentation frequency, shear angle and shear strain and it is correlated with the machining parameters. The machinability of the selected superalloys is assessed in terms of cutting force, chip compression ratio and surface roughness. It is found from the experimental analysis cutting force magnitude is less at higher cutting speed for all the superalloys. Chip compression ratio is found maximum in case of Inconel 718 due to precipitation hardening of alloy and followed by Inconel 600 and Inconel 800. The chip segmentation frequency is high at lower cutting speed for Inconel 600 due significant strain hardening. Serrated chips are produced during machining of three selected superalloys and it is found that serrated tooth spacing decreases with cutting speed. Shear plane angle increases on cutting speed increases which effect tool workpiece contact length during machining resulted thin, short and snarled chips was produced. From analytical modeling it shows that shear strain decreases with cutting speed which indicate that at higher cutting speed material deformed elastically than plastically. The effect of cutting tool material is observed on the surface roughness. The better surface finish is obtained with coated carbide inserts as compared to ceramic inserts for all the selected superalloys. However, Inconel 800 shows higher surface roughness due to combination of (Ni–Cr–Fe) alloying element which is responsible for carburization of surface layer during machining.
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Pervaiz, Salman, Sathish Kannan, Saqib Anwar, and Dehong Huo. "Machinability analysis of dry and liquid nitrogen–based cryogenic cutting of Inconel 718: experimental and FE analysis." International Journal of Advanced Manufacturing Technology 118, no. 11-12 (October 18, 2021): 3801–18. http://dx.doi.org/10.1007/s00170-021-08173-1.
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Abstract Inconel 718 is famous for its applications in the aerospace industry due to its inherent properties of corrosion resistance, wear resistance, high creep strength, and high hot hardness. Despite the favorable properties, it has poor machinability due to low thermal conductivity and high hot hardness. To limit the influence of high cutting temperature in the cutting zone, application of cutting flood is recommended during the cutting operation. Cryogenic cooling is the recommended method when machining Inconel 718. However, there is very limited literature available when it comes to the numerical finite element modeling of the process. This current study is focused on the machinability analysis of Inconel 718 using numerical approach with experimental validations. Dry and cryogenic cooling methods were compared in terms of associated parameters such as chip compression ratio, shear angle, contact length, cutting forces, and energy consumption for the primary and secondary deformation zones. In addition, parameters related to chip morphology were also investigated under both lubrication methods. Chip formation in cryogenic machining was well captured by the finite element assisted model and found in good agreement with the experimental chip morphology. Both experimental and numerical observations revealed comparatively less chip compression ratio in the cryogenic cooling with larger value of shear plane angle. This results in the smaller tool–chip contact length and better comparative lubrication.
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Bhuvaneshwari, P., and T. R. Jaya Chandra Lekha. "Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 4 (April 1, 2020): 1852–56. http://dx.doi.org/10.1166/jctn.2020.8453.
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This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.
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Wu, Xian, Yu Zhou, Congfu Fang, Laifa Zhu, Feng Jiang, Ke Sun, Yuan Li, and Yiyang Lin. "Experimental Investigation on the Machinability Improvement in Magnetic-Field-Assisted Turning of Single-Crystal Copper." Micromachines 13, no. 12 (December 4, 2022): 2147. http://dx.doi.org/10.3390/mi13122147.
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The single-point diamond-turning operation is a commonly used method for ultra-precision machining of various non-ferrous materials. In this paper, a magnetic field was introduced into a single-point diamond-turning system, and magnetic-field-assisted turning experiments were carried out. The results revealed that the magnetic field affects the metal-cutting process in the form of the cutting force, chip morphology, and surface quality. Compared with traditional turning, magnetic-field assisted turning increases the cutting force by 1.6 times, because of the additional induced Lorentz force, and reduces the cutting-force ratio and friction coefficient on the rake surface by 16%, with the improved tribological property of the tool/chip contact-interface. The chip morphology in the magnetic-field-assisted turning shows the smaller chip-compression ratio and the continuous side-morphology. With the magnetoplasticity effect of the metal material and the friction reduction, magnetic-field-assisted turning is helpful for improving metal machinability and achieving better surface-quality.
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Liu, Yan Yan, Yin Han Gao, Guo Ning Li, Wen Hua Wang, Ran Feng Zhang, and Long Xu Jin. "Design of High Speed and Parallel Compression System Used in the Big Area CCD of High Frame Frequency." Advanced Materials Research 411 (November 2011): 488–96. http://dx.doi.org/10.4028/www.scientific.net/amr.411.488.
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According to the area CCD camera of characteristics, such as high resolution capacity and high frame frequency, this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly, according to the work principle of the area CCD, FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly, with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip, real time image compression and the high speed area CCD are realized. Finally, by detecting the analog signal of the area CCD output, the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15, the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated, which reduces the data transmission between them and improves systematic integration degree.
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Jackson, Mark J., Jameson K. Nelson, Michael D. Whitfield, Jonathan S. Morrell, Rodney G. Handy, and Peter L. Schmidt. "Chip formation and similarity in the plano-grinding of explosive surrogates." Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture 232, no. 12 (January 6, 2017): 2071–82. http://dx.doi.org/10.1177/0954405416683972.
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The processing of polymer-bonded explosives is not widely reported in the literature, especially the machining of explosive surrogates in the combined planing and grinding operation known as plano-grinding. The process of machining long pieces of an inert substitute using a wax binder to hold sugar particles together and then subjecting the surrogate material to a linear cutting motion to generate chip fragments is described. The aim and purpose of this work is to analyze the machining of explosive surrogates in terms of chip formation models (oscillating and stress ratio models) and similarity models (chip compression ratio, Poletica, and Peclet numbers). The analysis of machining is compared to standard engineering materials so that the explosives engineer can benchmark machining performance of explosive surrogates to standard materials. The article concludes with statements on how to improve the understanding of machining of explosive surrogates with specifically engineered abrasive cutting tools.
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Huang, Guilin, Zhengjin Zhang, Honghai Wang, Jiabao Jiang, and Qilin Wu. "Encoding Test Pattern of System-on-Chip (SOC) Using Annular Scan Chain." Security and Communication Networks 2022 (September 2, 2022): 1–7. http://dx.doi.org/10.1155/2022/6974101.
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With the improvement of System-on-Chip integration, the chip requires an increasingly large amount of test data. To solve the contradiction between the storage capacity and bandwidth of automatic test equipment (ATE), a new method of test data compression/decompression is proposed based on an annular scan chain. Corresponding fault bits of different test patterns are incompatible, moving test patterns in an annular scan chain, makes all of the new corresponding bits of different test patterns be compatible or backward-compatible, so different adjacent test patterns form a new relation that are indirectly compatible or indirectly backward-compatible, achieves the purpose of test data compression by encoding these indirectly compatible test patterns or indirectly backward-compatible test patterns. According to experimental results, the average compression ratio increases by %6.94 to % 15.1 compared with the other schemes, relative decompression architecture is simple. In the annular scan chain, the test pattern moves clockwise with the minimal bits, generating subsequent test patterns quickly, it is advantageous to reduce the test application time of a single IP core.
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Gao, Chong Yang, Bin Fang, and Yuan Tong Gu. "Theoretical Analysis of Serrated Chip Formation Based on Ideal Models in High Speed Cutting." Advanced Materials Research 154-155 (October 2010): 239–45. http://dx.doi.org/10.4028/www.scientific.net/amr.154-155.239.
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In this paper, two ideal formation models of serrated chips, the symmetric formation model and the unilateral right-angle formation model, have been established for the first time. Based on the ideal models and related adiabatic shear theory of serrated chip formation, the theoretical relationship among average tooth pitch, average tooth height and chip thickness are obtained. Further, the theoretical relation of the passivation coefficient of chip’s sawtooth and the chip thickness compression ratio is deduced as well. The comparison between these theoretical prediction curves and experimental data shows good agreement, which well validates the robustness of the ideal chip formation models and the correctness of the theoretical deducing analysis. The proposed ideal models may have provided a simple but effective theoretical basis for succeeding research on serrated chip morphology. Finally, the influences of most principal cutting factors on serrated chip formation are discussed on the basis of a series of finite element simulation results for practical advices of controlling serrated chips in engineering application.
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Pi, Yunyun, Xiaolong Yin, Wenjun Deng, and Wei Xia. "Study on Surface Hardness and Microstructure of Pure Copper Chip Strips Prepared by LSEM." Advances in Materials Science and Engineering 2019 (July 8, 2019): 1–9. http://dx.doi.org/10.1155/2019/5254892.
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Large strain extrusion machining (LSEM) is one of the severe plastic deformation (SPD) methods that can improve the mechanical properties of materials. The purpose of this experiment is to study the surface hardness and microstructure of the pure copper chip strips. It was found that most of the grains of the chip strips had been refined to the ultrafine grain grade. Finite element analysis (FEA) simulations were conducted to predict the von Mises equivalent strains. Based on the analysis of variance (ANOVA), further study indicated that the surface hardness of the chip strips was decided by several key parameters including the chip thickness compression ratio, rake angle, and uncut chip thickness during LSEM. Through this analysis, a set of parameters which have the greatest impact on the properties of the material can be found. This set of parameters helps us to achieve the strip with the best performance.
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Rajak, Abdul, Vilas H. Gaidhane, and Aaron D’costa. "Design and Implementation of a Network Security Chip with Improved Compression Approach." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 4 (July 5, 2020): 507–15. http://dx.doi.org/10.2174/2352096512666190423111018.
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Background: Network security is used to secure data transmission over the wireless network. Encryption of information plays a vital role in communication since it protects the sender and receiver from the hackers trying to access the information. Objectives: In recent years, protecting the information data has become a challenging task for the researchers. Hence, there is a need to improve the existing methods of secure data transmission. Method: In this paper, a new approach is proposed to implement a better security chip for secured data transmission. It is based on the combination of encryption and description as well as the compression techniques. The proposed design focuses on the reduction of delay in the circuit using the compression approach. Results: The various simulations are carried out using the Xilinx, and MATLAB software. The timing signals are observed on Xilinx and the proposed algorithm has been simulated and tested on MATLAB. Conclusion: The presented approach performed better and achieved a good compression ratio and hence the loss of information was less at the receiving end.
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Mostafa, Gody, Abdelhalim Zekry, and Hatem Zakaria. "FPGA implementation of Lempel-Ziv data compression." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 2 (July 1, 2021): 99. http://dx.doi.org/10.11591/ijres.v10.i2.pp99-108.
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When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. One of the most lossless data compression algorithms commonly used is Lempel-Ziv. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates and space-saving percentage as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs.
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Kim, Mi-Song, Won Sik Hong, and Myeongin Kim. "Flip Chip - Chip Scale Package Bonding Technology with Type 7 Solder Paste Printing." Journal of Welding and Joining 39, no. 4 (August 30, 2021): 359–67. http://dx.doi.org/10.5781/jwj.2021.39.4.3.
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In this study, thermo-compression(TC) and vacuum reflow(VR) bonding processes of fine pitch interconnection were optimized using Type 7 Sn-3.0Ag-0.5Cu solder paste. A chip with Cu pillar Sn-2.5Ag bumps and BT substrate with ENEPIG surface finish were used, and the thickness and the aperture ratio of the metal mask were 30 ㎛/50 ㎛ and 70%/100%, respectively. As a result of optimizing the printing process, a metal mask with a thickness of 30 ㎛ and an aperture ratio of 100% was selected. As a result of the TC and VR bonding processes optimization, Cu6Sn5 and (Cu,Ni)6Sn5 IMC layers were formed on the top and bottom of the solder joint, respectively. In the conventional TC process sample, the thickness of the solder was measured to be 4.1 ㎛, and the IMC thickness ratio was calculated to be 40%. Also, in the TC and VR process samples with solder paste, the thickness of the solder was measured to be 6.5 ㎛ and 10.3 ㎛, respectively, and the ratio of the IMC thickness was calculated to be about 32% and 43%. It was expected that it would be beneficial to reliability by reducing the occurrence and propagation of cracks in the solder joint due to the effect of lowering the IMC thickness ratio as the volume of the solder becomes larger than that of the conventional TC process.
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Leksycki, Kamil, and Eugene Feldshtein. "On the analysis of chip shaping after finishing turning of Ti6Al4V titanium alloy under dry, wet and MQL conditions." Archives of Mechanical Technology and Materials 39, no. 1 (January 1, 2019): 36–40. http://dx.doi.org/10.2478/amtm-2019-0007.
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Abstract The shape and type of chip give general information about the cutting process. This paper presents the results of testing the shape and type of chips of Ti6Al4V titanium alloy after it finishes turning. The process was carried out under dry, wet and MQL (Minimum Quantity Lubrication) conditions at variable cutting speeds and feed rates and a constant depth of cutting. For planning the tests, the PSI (Parameter Space Investigation) method was used, which allows the experiment to be carried out while minimizing the number of experience points. It was found that the cutting speed and feed affect the type and shape of the chip, and clear differences were observed between dry and wet cooling conditions, and MQL conditions. During turning, the intensity of the cutting speed and feed influence on the chip compression ratio was changed. It was similar for dry and wet cooling conditions but smaller for MQL conditions. The purpose of this research is to analyze the chip shaping when Ti6Al4V titanium alloy finishes turning under dry, wet and MQL cooling conditions.
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Qu, Wei, and Xiao Xin Sun. "Design and Hardware Implementation of Image Compression Denoising Based on Median Filter and Wavelet Transform." Applied Mechanics and Materials 602-605 (August 2014): 3218–22. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.3218.
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An image compression denoising method based on median filter and wavelet transform is proposed in order to overcoming shortcomings of traditional methods of image processing in this paper. This method combined hardware parallelism with software technology is enable to achieve image compression denoising and take into account algorithm validation, and fast response of the system. An real-time image processing system is design by this method. Design and hardware implementation of fast median filtering algorithm based on EP1C12 FPGA chip is realized and software simulation of median filter and wavelet transform is done. The experimental results show that this system has advantages of fast response characteristic, less time consuming and high signal to noise ratio.
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Yoon, Sungchul, Sungho Jun, Yongkwon Cho, Kilwhan Lee, Hyukjae Jang, and Tae Hee Han. "Optimized Lossless Embedded Compression for Mobile Multimedia Applications." Electronics 9, no. 5 (May 23, 2020): 868. http://dx.doi.org/10.3390/electronics9050868.
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Power consumption is a critical design factor in modern mobile chip design, in which the memory system with dynamic random-access memory (DRAM) consumes more than half of the entire system’s power. Without DRAM bandwidth compression, extreme multimedia operations such as 8K high dynamic range (HDR) recording and 8K video conference calling are not possible without sacrificing image quality or trimming because of thermal limitations or battery time sustainability constraints. Since heterogeneous processors are substantially involved in managing various types of fallbacks or software solutions, complicated compression algorithms for high-compression ratios are not actually adaptable owing to timing closure problems or high throughput requirements. In this paper, we propose evaluation metrics to assess lossless embedded compression (LEC) algorithms to reflect realistic design considerations for mobile multimedia scenarios. Furthermore, we introduce an optimized LEC implementation for contemporary multimedia applications in mobile devices based on the proposed metrics. The proposed LEC implementation enhances the compression ratio of LEC algorithms in other commercial application processors for contemporary premium smartphones by up to 9.2% on average, while maintaining the same timing closure condition.
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Léger, Éric, Benoit Landry, and Gabriel LaPlante. "High flow compression molding for recycling discontinuous long fiber thermoplastic composites." Journal of Composite Materials 54, no. 23 (March 26, 2020): 3343–50. http://dx.doi.org/10.1177/0021998320913625.
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An investigation into high flow compression molding for recycling thermoplastic discontinuous long fiber composites is presented. High flow recycled panels and conventional low flow baseline panels were produced with a large rectangular (2:1 aspect ratio) mold. Flow was induced in the recycled panels by stacking cut sections of conventionally produced baseline panels in the center of the mold cavity, representing 25% initial coverage. High flow compression molded panels were found to exhibit significantly higher than baseline tensile strength (+50%) and modulus (+31%) when tested in the direction parallel to flow. When tested in the direction perpendicular to flow, the opposite effect was found, with reductions in tensile strength (−42%) and modulus (−37%). However, when the average results of both directions are compared to baseline, no significant difference was found between the recycled and baseline panels. This severe anisotropic redistribution of mechanical properties suggests chip orientation is affected by flow. Additionally, micrographic analysis revealed that high flow molding induces intra-ply chip shearing and a reduction in resin rich regions within panels. Baseline panels also exhibited in-plane anisotropy, despite initial random distribution of chips and no or near no flow induced during molding. In this case, mechanical properties favored the direction perpendicular to that of the recycled panels.
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Wang, Jun. "On-chip frame memory reduction using a high-compression-ratio codec in the overdrives of liquid-crystal displays." Optical Engineering 49, no. 11 (November 1, 2010): 117005. http://dx.doi.org/10.1117/1.3509370.
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Sun, Shoujin, Milan Brandt, and Matthew S. Dargusch. "Effect of tool wear on chip formation during dry machining of Ti-6Al-4V alloy, part 2: Effect of tool failure modes." Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture 231, no. 9 (September 4, 2015): 1575–86. http://dx.doi.org/10.1177/0954405415600011.
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Variation in the geometric and surface features of segmented chips with an increase in the volume of material removed and tool wear has been investigated at cutting speeds of 150 and 220 m/min at which the cutting tools fail due to gradual flank wear and plastic deformation of the cutting edge, respectively. Among the investigated geometric variables of the segmented chips, slipping angle, undeformed surface length, segment spacing, degree of segmentation and chip width showed the different variation trends with an increase in the volume of material removed or flank wear width, and achieved different values when tool failed at different cutting speeds. However, the chip geometric ratio showed a similar variation trend with an increase in the volume of material removed and flank wear width, and achieved the similar value at the end of tool lives at cutting speeds of both 150 and 220 m/min regardless of the different tool failure modes. Plastic deformation of the tool cutting edge results in severe damage on the machined surface of the chip and significant compression deformation on the undeformed surface of the chip.
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Das, Anshuman, S. K. Patel, B. B. Biswal, and Aniket Santoshwar. "Comparative Study of some Machining Characteristics during Hard Turning of Alloy Steel with Untreated and Cryotreated Cermet Inserts." Materials Science Forum 978 (February 2020): 64–76. http://dx.doi.org/10.4028/www.scientific.net/msf.978.64.
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Enhanced tool life of cutting inserts are most suitable condition for higher productivity of a manufacturing industry. Several methods are found and employed for higher tool life of cutting inserts among which cryogenic treatment is considered as the most significant method but no adequate researches have been found concerning the impact of cryogenic treatment on cermet inserts especially in hard turning operation. Hence, in the current experimental investigation, the comparative assessment of various responses such as flank wear, crater wear, chip morphology, and chip compression ratio were carried out during machining of hardened steel with both untreated and cryo-treated cermet inserts under dry cutting condition. Wear on the rake faces and flank faces were studied using advanced optical microscope, while chip morphology was studied using SEM. The experimental result demonstrated that the uncoated deep cryotreated with tempered cermet insert delivered better results in comparison to other cermet inserts. Deep cryogenically treated with tempered insert was found to be more suitable during machining of hardened steel because of the enhancement of wear resistance, micro hardness and toughness.
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Gorski, Dmitri, Jan Hill, Per Engstrand, and Lars Johansson. "Review: Reduction of energy consumption in TMP refining through mechanical pre-treatment of wood chips." Nordic Pulp & Paper Research Journal 25, no. 2 (May 1, 2010): 156–61. http://dx.doi.org/10.3183/npprj-2010-25-02-p156-161.
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Abstract This review covers the effect of mechanical pre-treatment of wood chips on the energy consumption in refining and the quality of pulp. To understand the mechanisms of mechanical pre-treatment, a short description of relevant refining theory and reported effects of pre-treatment on wood morphology is given. Mechanical pre-treatment offers a chance to utilize the energy needed to defibrate chips in a more efficient way, minimizing the cyclic elastic deformations which are the main defibration mechanism in refining. Studies of fibre morphology indicate that compressive pretreatment mechanically introduces favorable weak points in the S1 and S2 fibre walls where defibration proceeds easier upon subsequent refining. Published results which cover the effect of the pretreatment on energy consumption and pulp properties are reviewed. Energy reduction of between 10% and 30% is reported in the literature. High ratio of volumetric compression is necessary. Pressurized conditions are required to ensure that the fibres are not damaged during the pre-treatment. Other effects of compressive pretreatment include a more uniform chip size and moisture content, better penetration of chemicals and removal of extractives from the chips. A list of equipment used for chip pre-compression is provided together with published results of pilot-scale and mill-scale operation.
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Yuan, Haiying, Jiaping Mei, Xun Sun, K. T. Cheng, and Kun Guo. "A Power Efficient Test Data Compression Method on Count Compatible PRL Coding." Journal of Circuits, Systems and Computers 24, no. 06 (May 26, 2015): 1550084. http://dx.doi.org/10.1142/s021812661550084x.
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A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.
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Elkhouly, Mohamed, Chang-Soon Choi, Srdjan Glisic, Frank Ellinger, and J. Christoph Scheytt. "A 60 GHz eight-element phased-array receiver front-end in 0.25 µm SiGe BiCMOS technology." International Journal of Microwave and Wireless Technologies 4, no. 6 (September 20, 2012): 579–94. http://dx.doi.org/10.1017/s1759078712000591.
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This paper presents the design of an eight-element 60 GHz phased-array receiver chip with interference mitigation capability, fabricated in 0.25 μm SiGe BiCMOS technology. Each receiver element contains a low noise amplifier (LNA) and a vector-modulator that supports high-resolution amplitude and phase control. A fully differential power combining network follows the eight elements. The chip also includes an active power divider, a down conversion mixer, and fully integrated 48 GHz PLL to demonstrate the IF down-conversion. With LNA, a phase shifter and hybrid active and passive power combining network, each receiver path achieves 18 dB of gain, 360° phase shift in steps less than 3°, 20 dB amplitude control, and 4 GHz 3 dB-bandwidth and input referred 1 dB compression point P1 dB of each element is of −22 dBm. Each receiver element dissipates in total 132 mW. The phased-array receiver shows more than 25 dB of signal to interference noise ratio, by means of amplitude and phase control.
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Zhu, Chen, Huang, Wang, and Yu. "A High-Efficiency K-band MMIC Linear Amplifier Using Diode Compensation." Electronics 8, no. 5 (April 30, 2019): 487. http://dx.doi.org/10.3390/electronics8050487.
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This paper describes the design and measured performance of a high-efficiency and linearity-enhanced K-band MMIC amplifier fabricated with a 0.15 μm GaAs pHEMT processing technology. The linearization enhancement method utilizing a parallel nonlinear capacitance compensation diode was analyzed and verified. The three-stage MMIC operating at 20–22 GHz obtained an improved third-order intermodulation ratio (IM3) of 20 dBc at a 27 dBm per carrier output power while demonstrating higher than a 27 dB small signal gain and 1-dB compression point output power of 30 dBm with 33% power added efficiency (PAE). The chip dimension was 2.00 mm × 1.40 mm.
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Choe, Young-Joe, Hyohyun Nam, and Jung-Dong Park. "A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology." Electronics 8, no. 9 (September 17, 2019): 1043. http://dx.doi.org/10.3390/electronics8091043.
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We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.
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Standke, Mark. "RD53B Wafer Testing for the ATLAS ITk Pixel Detector." Journal of Physics: Conference Series 2374, no. 1 (November 1, 2022): 012087. http://dx.doi.org/10.1088/1742-6596/2374/1/012087.
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RD53B/ITkPix-V1 is the most recent hybrid pixel readout chip development for the ATLAS pixel detector at the HL-LHC. It is the first full-scale 65 nm hybrid pixel-readout chip of its kind. ITkPix-V1 consists of more than one billion transistors with a high memory triplication ratio to cope with the high particle density at the heart of ATLAS. Chips will be as close to the interaction point as possible to optimize the resolution of impact parameters. The ITkPix-V1 chip features a 5-Gbit connection, with special data compression to deal with high hit intensities. In addition, a low-power, low-noise analog front-end is used to ensure high readout speeds and low detection thresholds. Failure of chips in ATLAS would be problematic. Therefore, a thorough test is necessary before and during production. For this purpose, the Bonn ATLAS group has developed BDAQ53, a fast and versatile simulation and testing environment that allows small and large-scale testing for ITkPix-V1 and its successor chips. This conference note will give an overview of the testing environment while focusing on large-scale wafer testing to evaluate ITkPix-V1’s suitability for its deployment at the HL-LHC.
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Lakshmi Narayanan, K., G. P. Ramesh, and V. Divya. "Robust and brittle secured video for IOT." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 93. http://dx.doi.org/10.14419/ijet.v7i2.20.11762.
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In this paper the system is mainly designed for the military purpose security since now-a-days securing our military has become a difficult task .our live is mainly dependent on other objects mainly we are computer based living and digital image processing plays a vital role in it. This process has much advantage as well as some disadvantage. A VLSI circuit is built with many millions of IC chip, so it is considered to be indivisible for the construction purpose. The internet-of things (Iot) is a electronic device which is connected to the vehicle and the building item which is used to generate many secured techniques which is connected with the software, electrical, electronics and mechectronics devices and human recourses also. Better Portable Graphics Algorithm with a Context-Adaptive Binary Arithmetic Coding (CABAC) encoding algorithm is used in the existing system this process is affected by the Gaussian noise, low compression ratio and time delay to overcome above issues and enhanced with Secure Better Portable Graphics (SBPG) compression algorithm with HEVC is present .The proposed architecture is suitable for high performance imaging in the Iot and for the high quality compression files and secured transformation of image and video captured in the digital camera. Encryption and watermarking are the two technique used in the process. The watermarking technique is more secure than the previous system. This process produces high quality JPEG, and high PSNR ratio. The scrambling algorithm is used in the encryption process. It is used for providing secured image.
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Fang, Hong-Wen, and Chih-Cheng Lu. "A Real Time and Lossless Encoding Scheme for Patch Electrocardiogram Monitors." Applied Sciences 8, no. 12 (November 24, 2018): 2379. http://dx.doi.org/10.3390/app8122379.
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Cardiovascular diseases are the leading cause of death worldwide. Due to advancements facilitating the integration of electric and adhesive technologies, long-term patch electrocardiogram (ECG) monitors (PEMs) are currently used to conduct daily continuous cardiac function assessments. This paper presents an ECG encoding scheme for joint lossless data compression and heartbeat detection to minimize the circuit footprint size and power consumption of a PEM. The proposed encoding scheme supports two operation modes: fixed-block mode and dynamic-block mode. Both modes compress ECG data losslessly, but only dynamic-block mode supports the heartbeat detection feature. The whole encoding scheme was implemented on a C-platform and tested with ECG data from MIT/BIH arrhythmia databases. A compression ratio of 2.1 could be achieved with a normal heartbeat. Dynamic-block mode provides heartbeat detection accuracy at a rate higher than 98%. Fixed-block mode was also implemented on the field-programmable gate array, and could be used as a chip for using analog-to-digital convertor-ready signals as an operation clock.
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Mehta, Usha, K. S. Dasgupta, and N. M. Devashrayee. "Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method." VLSI Design 2011 (October 5, 2011): 1–8. http://dx.doi.org/10.1155/2011/756561.
Full textAbstract:
Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like “don't care bit filling” and “reordering” which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed “Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)” is a modification to earlier proposed “Hamming Distance based Reordering—Columnwise Bit Filling and Difference vector.” This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow.
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Storchak, Michael, Thomas Stehle, and Hans-Christian Möhring. "Determination of the Shear Angle in the Orthogonal Cutting Process." Journal of Manufacturing and Materials Processing 6, no. 6 (October 28, 2022): 132. http://dx.doi.org/10.3390/jmmp6060132.
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Determination of the shear angle by experimental and analytical methods, as well as by numerical simulation, is presented. Experimental determination of the shear angle was performed by analyzing the chip roots obtained by the method of cutting process quick stop through purposeful fracture of the workpiece in the area surrounding the primary cutting zone. The analytical determination of the shear angle was carried out using the chip compression ratio and was based on the principle of a potential energy minimum. Measurement of the shear angle in the numerical simulation of orthogonal cutting was performed using the strain rate pattern of the machined material at the selected simulation moment. It was analyzed how the parameters of the Johnson–Cook constitutive equation and the friction model affect the shear angle value. The parameters with a predominant effect on the shear angle were determined. Then the generalized values of these parameters were established with a software algorithm based on identifying the intersection of the constitutive equation parameter sets. The use of generalized parameters provided the largest deviation between experimental and simulated shear angle values from 9% to 18% and between simulated and analytically calculated shear angle values from 7% to 12%.
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van Veen, Co, Bart Vandevelde, and Eric Beyne. "Influence Of Solder Joint Shape On The Thermo-Mechanical Reliability Of CSP's." Journal of Microelectronics and Electronic Packaging 1, no. 2 (January 1, 2004): 53–63. http://dx.doi.org/10.4071/1551-4897-1.2.53.
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Not only the stand-off height but also the shape of a solder joint has a strong influence on the joint reliability under temperature cycling. The shape determines the size of the local stress and strain concentrations. It is therefore very important to know well the joint shape after reflow. In a previous paper closed analytical expressions were derived for liquid bump shapes, as a function of pad size and bump height [1]. The bump deformation as a function of the chip weight could be derived from the force constant. In the present paper closed analytical expressions are derived for the force constant for liquid bumps having unequal spherical pad sizes. It turns out that the force constant for compression can be optimized as a function of the ratio of those pad sizes. The shape of the bump and especially the contact angle is of interest for modeling activities where geometrical effects do play a role. Furthermore from the variation in bumps heights on a chip an estimate can be made of the tilt of the chip after assembly. The solder profile estimation by the analytical expressions is validated by experimental results. Also a comparison with the solder profile estimation by the simulation software Surface Evolver is done. Both comparisons showed that the analytical estimation of the standoff height is very good as long as the gravitation energy contributed by the chip weight is less than 10% of the total energy. Finally, an example is shown where the analytical model and Surface Evolver are the geometrical input for a finite element model. The example considers a CSP assembled at both sides of the printed circuit board.
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Tseng, Chwan-Lu, Chun-Chieh Hsiao, I.-Chi Chou, Chia-Jung Hsu, Yi-Ju Chang, and Ren-Guey Lee. "DESIGN AND IMPLEMENTATION OF ECG COMPRESSION ALGORITHM WITH CONTROLLABLE PERCENT ROOT-MEAN-SQUARE DIFFERENCE." Biomedical Engineering: Applications, Basis and Communications 19, no. 04 (August 2007): 259–68. http://dx.doi.org/10.4015/s1016237207000343.
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In this paper, the orthogonality of coefficient matrices of wavelet filters is utilized to derive the energy equation for the relation between time-domain signal and its corresponding wavelet coefficients. Using the energy equation, the relationship between the wavelet coefficient error and the reconstruction error is obtained. The errors considered in this paper include the truncation error and quantization error. This not only helps to control the reconstruction quality but also brings two advantages: (1) It is not necessary to perform inverse transform to obtain the distortion caused by compression using wavelet transform and can thus reduce computation efforts. (2) By using the energy equation, we can search for a threshold value to attain a better compression ratio within the range of a pre-specified percent root-mean-square difference (PRD) value. A compression algorithm with run length encoding is proposed based on the energy equation. In the end, the Matlab software and MIT-BIH database are adopted to perform simulations for verifying the feasibility of our proposed method. The algorithm is also implemented on a DSP chip to examine the practicality and suitability. The required computation time of an ECG segment is less than 0.0786 ,s which is fast enough to process real-time signals. As a result, the proposed algorithm is applicable for implementation on mobile ECG recording devices.
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Pope, Gunnar C., and Ryan J. Halter. "Design and Implementation of an Ultra-Low Resource Electrodermal Activity Sensor for Wearable Applications ‡." Sensors 19, no. 11 (May 29, 2019): 2450. http://dx.doi.org/10.3390/s19112450.
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While modern low-power microcontrollers are a cornerstone of wearable physiological sensors, their limited on-chip storage typically makes peripheral storage devices a requirement for long-term physiological sensing—significantly increasing both size and power consumption. Here, a wearable biosensor system capable of long-term recording of physiological signals using a single, 64 kB microcontroller to minimize sensor size and improve energy performance is described. Electrodermal (EDA) signals were sampled and compressed using a multiresolution wavelet transformation to achieve long-term storage within the limited memory of a 16-bit microcontroller. The distortion of the compressed signal and errors in extracting common EDA features is evaluated across 253 independent EDA signals acquired from human volunteers. At a compression ratio (CR) of 23.3×, the root mean square error (RMSErr) is below 0.016 μ S and the percent root-mean-square difference (PRD) is below 1%. Tonic EDA features are preserved at a CR = 23.3× while phasic EDA features are more prone to reconstruction errors at CRs > 8.8×. This compression method is shown to be competitive with other compressive sensing-based approaches for EDA measurement while enabling on-board access to raw EDA data and efficient signal reconstructions. The system and compression method provided improves the functionality of low-resource microcontrollers by limiting the need for external memory devices and wireless connectivity to advance the miniaturization of wearable biosensors for mobile applications.
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Hidei, Volodymyr, Iurii Sidun, Oleksii Hunyak, Svitlana Stanchak, and Volodymyr Bidos. "Application of wastepaper sludge ash as mineral powder for hot asphalt concrete mix." Theory and Building Practice 2020, no. 2 (November 20, 2020): 42–47. http://dx.doi.org/10.23939/jtbp2020.02.042.
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In this article the potentiality is proven for application of wastepaper sludge ash (WSA) as mineral powder for traditional hot asphalt concrete mix. For the comparative testing in this article the traditional limestone mineral powder is used. The chemical (oxide) composition of the aggregates was studied, while that was determined by means of DRON - 3.0 diffractometer. It was ascertained that CaO is present in wastepaper sludge ash in sufficient quantity, while it provides for utilization of this waste material as an aggregate for asphalt concrete. The limestone mineral powder granulometric composition was determined and the wastepaper sludge ash was grinded by ball grinder till the appropriate granulometric composition was reached. There were studied the main physical and mechanical parameters of bitumen 70/100 to be used for formation of asphalt binder in combination with the studied mineral aggregate. There were formed the following series of traditional hot asphalt concrete mix: on limestone mineral powder, on wastepaper sludge ash, on both limestone mineral powder and wastepaper sludge ash in ratio 50/50, 30/70, 20/80 (% w/w). By means of grading curves of dense-graded continuous mixes there was designed the chip-grain carcass of asphalt concrete mix. The asphalt concrete mix was designed based on the following characteristics: hot fine-grained densegraded asphalt concrete with residual porosity from 2 % to 5 %, with quantity of chip-grains sized more than 5 mm – 35-45 % and the maximum grain-size up to 15 mm. There was determined that WSA can perform as material to be used as mineral powder for asphalt concrete mixes. According to the requirements of Ukrainian standard (DSTU B V.2.7-119:2011), the asphalt concrete with WSA is of standard condition, but the water-saturation index approaches the acceptably allowed value, while in comparison with asphalt concrete with LMP – it is higher by 55%. Such result is due to the difference in oxide composition of the aggregates, namely lower content of products of calcareous rock in WSA. With combined application of limestone mineral powder and WSA in ratio 50/50, 30/70, 20/80 (% w/w) the water-saturation index decreases. As to the compression tensile strength and compression tensile strength after water-saturation, these indices on WSA are lower than on LMP just by 10%. The most efficient usage of WSA, considering the studies done, can be achieved when coupled with LMP in ratio 50/50.
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Mitra, Sanjoy, and Debaprasad Das. "A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes." Indonesian Journal of Electrical Engineering and Computer Science 12, no. 3 (December 1, 2018): 933. http://dx.doi.org/10.11591/ijeecs.v12.i3.pp933-940.
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As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘<em>n’</em> bits. Individual slices are treated as a Hamming codeword consisting of ‘<em>p’</em> parity bits and ‘<em>d’</em> data bits (<em>n = d + p)</em> and validity of each codeword is verified. If a valid slice is encountered<em>’</em> data bits prefixed by ‘<em>1’</em> are written to the compressed file, while for a non-valid slice all ‘<em>n’</em> bits preceded by ‘<em>0’</em> are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.
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Lau, John, Ming Li, Nelson Fan, Eric Kuah, Zhang Li, Kim Hwee Tan, Tony Chen, et al. "Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000576–83. http://dx.doi.org/10.4071/isom-2017-tha35_056.
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Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).
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Muhammad, Riaz. "A Fuzzy Logic Model for the Analysis of Ultrasonic Vibration Assisted Turning and Conventional Turning of Ti-Based Alloy." Materials 14, no. 21 (November 1, 2021): 6572. http://dx.doi.org/10.3390/ma14216572.
Full textAbstract:
Titanium and its alloys are largely used in various applications due its prominent mechanical properties. However, the machining of titanium alloys is associated with assured challenges, including high-strength, low thermal conductivity, and long chips produced in conventional machining processes, which result in its poor machinability. Advanced and new machining techniques have been used to improve the machinability of these alloys. Ultrasonic vibration assisted turning (UVAT) is one of these progressive machining techniques, where vibrations are imposed on the cutting insert, and this process has shown considerable improvement in terms of the machinability of hard-to-cut alloys. Therefore, selecting the right cutting parameters for conventional and assisted machining processes is critical for obtaining the anticipated dimensional accuracy and improved surface roughness of Ti-alloys. Hence, fuzzy-based algorithms were developed for the ultrasonic vibration assisted turning (UVAT) and conventional turning (CT) of the Ti-6Al7Zr3Nb4Mo0.9Nd alloy to predict the maximum process zone temperature, cutting forces, surface roughness, shear angle, and chip compression ratio for the selected range of input parameters (speed and depth-of-cut). The fuzzy-measured values were found to be in good agreement with the experimental values, indicating that the created models can be utilized to accurately predict the studied machining output parameters in CT and UVAT processes. The studied alloy resulted in discontinued chips in both the CT and UVAT processes. The achieved results also demonstrated a significant decline in the cutting forces and improvements in the surface quality in the UVAT process. Furthermore, the chip discontinuity is enhanced by the UVAT process due to the higher process zone temperature and the micro-impact imposed by the cutting tool on the workpiece.
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Lau, John, Ming Li, Nelson Fan, Eric Kuah, Zhang Li, Kim Hwee Tan, Tony Chen, et al. "Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)." Journal of Microelectronics and Electronic Packaging 14, no. 4 (October 1, 2017): 123–31. http://dx.doi.org/10.4071/imaps.522798.
Full textAbstract:
This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).
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Liu, Qiang, Guo Hua Fu, Xin Ge Lian, and Jun Wang. "Based on ARM Embedded Remote Data Acquisition System." Advanced Materials Research 614-615 (December 2012): 1566–69. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1566.
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Because of the data acquisition system is more and more wide application range, involved the signal source and the type of more and more of the requirement of measurement, more and more is also high, the domestic now has quite a few data collection system and measurement, but many systems are simple function, and acquisition channel, the sampling rate is low, less complex operation, and higher requirements for test environment. People need a wide application range, high performance/price ratio of data acquisition system. In this paper, the main content is the use of ARM9 processor C2440A primarily controller series 3, design an embedded data acquisition system. Using ARM9 chip do microprocessor design remote data acquisition system, through the embedded Linux system video data collection USB cameras, the JPEG compression coding, ARM9 chip control data acquisition by most industrial environmental restrictions for collection system that has a large capacity of the storage and wireless forwarding function. This paper to S3C2440A as the core, with A piece of FPGA and A piece of Ethernet CS8900A controller for auxiliary to realize the digital parts of the system hardware, analog part two way by the A/D acquisition, variable gain amplifier and basic amplifying circuit component. The system also realize the SD card memory function and various interface such as serial ports and JTAG mouth. In the software of realized in development platform on Linux system of transplantation, separately from the Bootloader transplantation, Linux kernel transplantation and root file system, the establishment of the three are expounded. And completion of the A/D converter, SD card and CS8900A in the drive design under Linux, and finally the data acquisition, storage design and forwarding program.
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Rahimzadeh, Jason, Fanjie Meng, Fredrick Sachs, Jianbin Wang, Deepika Verma, and Susan Z. Hua. "Real-time observation of flow-induced cytoskeletal stress in living cells." American Journal of Physiology-Cell Physiology 301, no. 3 (September 2011): C646—C652. http://dx.doi.org/10.1152/ajpcell.00099.2011.
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The mechanical stress due to shear flow has profound effects on cell proliferation, transport, gene expression, and apoptosis. The mechanisms for flow sensing and transduction are unclear, but it is postulated that fluid flow pulls upon the apical surface, and the resulting stress is eventually transmitted through the cytoskeleton to adhesion plaques on the basal surface. Here we report a direct observation of this flow-induced stress in the cytoskeleton in living cells using a parallel plate microfluidic chip with a fluorescence resonance energy transfer (FRET)-based mechanical stress sensor in actinin. The sensing cassette was genetically inserted into the cytoskeletal host protein and transfected into Madin-Darby canine kidney cells. A shear stress of 10 dyn/cm2 resulted in a rapid increase in the FRET ratio indicating a decrease in stress across actinin with flow. The effect was reversible, and cells were able to respond to repeated stimulation and showed adaptive changes in the cytoskeleton. Flow-induced Ca2+ elevation did not affect the response, suggesting that flow-induced changes in actinin stress are insensitive to intracellular Ca2+ level. The reduction in FRET ratio suggests actin filaments are under normal compression in the presence of flow shear stress due to changes in cell shape, and/or actinin is not in series with actin. Treatment with cytochalasin-D that disrupts F-actin reduced prestress and the response to flow. The FRET/flow method is capable of resolving changes of stress in multiple proteins with optical spatial resolution and time resolution >1 Hz. This promises to provide insight into the force distribution and transduction in all cells.
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Sa’don, Norazzlina M., Abdul Razak Abdul Karim, and Siti Noor Linda Taib. "Comparative Strength of Fibre Reinforced Peat and Clayey-Silt by Using Shredded Scrap-Tire." Materials Science Forum 1030 (May 2021): 124–37. http://dx.doi.org/10.4028/www.scientific.net/msf.1030.124.
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The strength comparison of fibre reinforced peat and clayey-silt for the compacted sub-grade by using the fibre reinforcement technique from the scrap tire is presented. The scrap tires are extracted and shredded into a standard size, i.e., rubber-chip, rubber-crumb, rubber-powder and fibre-polyester for the consistency and homogeneity of the design mix. In this study, two types of fibres are used, which are fibre polyester and rubber crumb. The fibres at various designated percentage are mixed with the clayey-silt and peat with the addition of a minimum 5% cement content as a binder to achieve the targeted strength. The specimens were prepared by compacting at the optimum moisture content and maximum dry density. The compacted treated specimens were prepared and air cured for 7 and 28 days in room temperature (23C to 26C). In evaluating the strength and durability effect of fibres between the untreated (no fibres) and treated specimens (with fibres and cement), the Unconfined Compression Strength (UCS) and California Bearing Ratio (CBR) tests are executed. The findings indicate that the shear strength increases with the curing period. The addition of fibre-polyester and shredded rubber-crumb exhibits an increment in the contact area and bonding between the fibre reinforced materials and soil particles, which then significantly improved the compressive strength of the design mix.
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Saponara, Sergio, Filippo Giannetti, and Bruno Neri. "Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G." Journal of Circuits, Systems and Computers 26, no. 04 (December 6, 2016): 1750069. http://dx.doi.org/10.1142/s0218126617500694.
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This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to derive transceiver design specifications. Being 5G still in pre-standardization phase, a few currently used standards (ECMA-387, IEEE 802.15.3c, and LTE-A) are taken into account as the reference for the signal format. Following a top-down flow, this work presents the design in 65[Formula: see text]nm CMOS SOI and bulk technologies of the key blocks of a fully integrated transceiver: low noise amplifier (LNA), power amplifier (PA) and on-chip antenna. Different circuit topologies are presented and compared allowing for different trade-offs between gain, power consumption, noise figure, output power, linearity, integration cost and link performance. The best configuration of antenna and LNA co-design results in a peak gain higher than 27[Formula: see text]dB, a noise figure below 5[Formula: see text]dB and a power consumption of 35[Formula: see text]mW. A linear PA design is presented to face the high Peak to Average Power Ratio (PAPR) of multi-carrier transmissions envisaged for 5G, featuring a 1[Formula: see text]dB compression point output power (OP1dB) of 8.2[Formula: see text]dBm. The delivered output power in the linear region can be increased up to 13.2[Formula: see text]dBm by combining four basic PA blocks through a Wilkinson power combiner/divider circuit. The proposed circuits are shown to enable future 5G connections, operating in a mm-wave spectrum range (spanning 9[Formula: see text]GHz, from 57[Formula: see text]GHz to 66[Formula: see text]GHz), with a data-rate of several Gb/s in a short-range scenario, spanning from few centimeters to tens of meters.
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Hu, Zheng Fei, Ying Mei Chen, and Min Di Huang. "A 5GHz Analog Laser Diode Driver for Radio-over-Fiber Transmission Applications." Applied Mechanics and Materials 635-637 (September 2014): 1063–66. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.1063.
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The design of an analog laser diode (LD) driver for 5GHz radio-over-fiber (ROF) transmission systems is presented in this paper. The proposed linear LD driver adopted a single-ended two-stage amplifier structure with the operating voltages of 1.8V and 3.3V respectively. The technique of self-biased cascade amplifier is employed to increase the gain and alleviate the danger of gate oxide breakdown. The simulation results show that the analog amplifier achieves the power gain of 35dB and the output 1dB compression point of 18dBm at 5GHz. The corresponding output modulation current is up to 50mA at the 1dB compression point. The total chip area is only 710μm×580μm with the all on chip input and output matching network, and the power consumption is 130mW.
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Oppermann, Hermann, Lothar Dietrich, Matthias Klein, Bernhard Wunderle, and Herbert Reichl. "Nano-Porous Gold Interconnect." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 002249–90. http://dx.doi.org/10.4071/2010dpc-tha31.
Full textAbstract:
Pure metal contacts offer some advantage as high thermal and electrical conductivity, ductile deformation behavior and reduction of mechanical peak stresses. They are used in flip chip assemblies as gold bumps, in die attach as sintered silver powder or as gold layer on very smooth surfaces for wafer bonding. Analyzing the demands in most suitable material properties we were looking for a compressible metal contact, which could compensate for all implanarities, with a highly reactive surface to reduce bonding temperature. It should be a noble metal, but with good adhesion to polymers. We have developed a nanoporous metal layer processed by electroplating a silver-gold alloy with 20 to 30% gold. High plating rates could be achieved exceeding those of standard gold electrolytes. Subsequent de-alloying by etching off the silver provides a nano-porous gold layer as an open-porous sponge with 70 to 80% porosity. Pore and ligament size were measured from different samples between 20 to 100 nm. Aging experiments showed the coarsening of pore size. We have successfully plated nano-sponge layer of 10 μm height on top of gold bumps on wafer level. But we don't see a limitation yet to further increase the thickness of gold nano-sponge. Chips were bonded by thermocompression resulting in a reduction of bump height without changing the bump diameter. At lower bond force and lower bond temperature the collapse of the porous structure occurred in the bond interface mainly, leaving the porosity in most of the bump volume unchanged. This leads to a new interconnect structure of high porosity. For very high porosity stiffness should be reduced with the square of the volume ratio. We therefore expect improved reliability due to the reduction in stiffness. Due to the compressible deformation behavior of the nano-sponge it could improve the yield during wafer-to-wafer bonding and stacking as the particle will be absorbed into the sponge. This allows bonding of wafers without the need of planarization the dielectric layer, e.g. due to steps over conductor lines. Therefore we will use the nano-sponge in stacking and 3D integration. Beside compression bonding and sintering we use the nano-sponge also as a thermal interface for adhesives. Filler particles are pressed into the sponge structure leading to a larger contact area between particle and substrate surface, thereby the adhesive matrix can penetrate into the open porous film. The locking interface should also provide very high adhesion strength.
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Zheng, Yi Lin, Ying Mei Chen, Jian Wei Gong, and Jian Guo Yao. "A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS." Applied Mechanics and Materials 433-435 (October 2013): 1463–69. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1463.
Full textAbstract:
The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.
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Sun, Ke Mei. "Wireless Image Transmission System." Applied Mechanics and Materials 336-338 (July 2013): 1661–64. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1661.
Full textAbstract:
A wireless image transmission system is proposed, which in order to offset the disadvantages of wire video monitor laying points hard, and disadvantages of wire video monitor implementing hard in bad circumstance. The core of the system is TI series of C5000 high speed DSP processor and radio frequency wireless communication chip. Through DSP transplantation of JPEG compression algorithm, complete image collection and image compression through DSP, use wireless receiving and sending module to complete wireless images data transmission. Use wireless receiving and sending module instead of emitter and network as image data transmission device, low cost, not required network fee, system can real-time complete terminal images collection and show. It can apply community guard and video monitor of deploying points urgently in the electric power system, factory, bank and other important department, which dont require higher performance.
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Jiang, Shuang, Shibin Liu, Chenguang Guo, Xu Fan, Teng Ma, and Prayag Tiwari. "Implementation of ARINC 659 Bus Controller for Space-Borne Computers." Electronics 8, no. 4 (April 16, 2019): 435. http://dx.doi.org/10.3390/electronics8040435.
Full textAbstract:
As one of the key technologies of Honeywell, the aeronautical radio incorporated (ARINC) 659 bus is popular in current space-borne computers. However, Honeywell does not design ARINC 659 bus controller separately, and there are only a few papers about FPGA-based ARINC 659 bus controllers. Accordingly, to promote the extremely high performance needs of space-borne computers, this paper designs an ARINC 659 bus controller chip which integrates two independent bus interface units (BIUs), one 8-bit MCU, and several peripheral interfaces (i.e., UART, SPI, and I2C). Because the two BIUs are identical and mutually checked, the symmetry problem is emphatically dealt with in the design of this bus controller, and effective timing convergence is realized, which makes the bus controller work reliably and stably. In addition, due to the circuit’s large scale, design for testability (DFT) is also considered. Accordingly, on-chip clock (OCC) and scanning compression test technique are used to realize the at-speed test and shorten the test time, respectively.
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Jang, Seojin, Wei Liu, and Yongbeom Cho. "Convolutional Neural Network Model Compression Method for Software—Hardware Co-Design." Information 13, no. 10 (September 26, 2022): 451. http://dx.doi.org/10.3390/info13100451.
Full textAbstract:
Owing to their high accuracy, deep convolutional neural networks (CNNs) are extensively used. However, they are characterized by high complexity. Real-time performance and acceleration are required in current CNN systems. A graphics processing unit (GPU) is one possible solution to improve real-time performance; however, its power consumption ratio is poor owing to high power consumption. By contrast, field-programmable gate arrays (FPGAs) have lower power consumption and flexible architecture, making them more suitable for CNN implementation. In this study, we propose a method that offers both the speed of CNNs and the power and parallelism of FPGAs. This solution relies on two primary acceleration techniques—parallel processing of layer resources and pipelining within specific layers. Moreover, a new method is introduced for exchanging domain requirements for speed and design time by implementing an automatic parallel hardware–software co-design CNN using the software-defined system-on-chip tool. We evaluated the proposed method using five networks—MobileNetV1, ShuffleNetV2, SqueezeNet, ResNet-50, and VGG-16—and FPGA processors—ZCU102. We experimentally demonstrated that our design has a higher speed-up than the conventional implementation method. The proposed method achieves 2.47×, 1.93×, and 2.16× speed-up on the ZCU102 for MobileNetV1, ShuffleNetV2, and SqueezeNet, respectively.