Relevant bibliographies by topics / Chip-compression ratio

Academic literature on the topic 'Chip-compression ratio'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Chip-compression ratio"

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Zhou, Jun, and Rong Di Han. "Experimental Investigation of Turning with Magnetized Cutting Emulsion." Key Engineering Materials 426-427 (January 2010): 225–29. http://dx.doi.org/10.4028/www.scientific.net/kem.426-427.225.

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The purpose of this study is to clarify the possibility of the turning process with the magnetized cutting emulsion. In particular, the effect of the magnetized cutting emulsion in turning process were examined through observation and measurement of the shape of the generated chips, machined surface integrity, cutting force and chip thickness compression ratio in a series of turning experiments. As a result, compared with dry turning and turning with cutting emulsion, the application of the magnetized cutting emulsion can decrease cutting force and chip thickness compression ratio, increases machined surface integrity.
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Deng, Wen Jun, Ping Lin, Zi Chun Xie, and Qing Li. "Analysis of Large-Strain Extrusion Machining with Different Chip Compression Ratios." Journal of Nanomaterials 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/851753.

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Large-Strain Extrusion Machining (LSEM) is a novel-introduced process for deforming materials to very high plastic strains to produce ultra-fine nanostructured materials. Before the technique can be exploited, it is important to understand the deformation behavior of the workpiece and its relationship to the machining parameters and friction conditions. This paper reports finite-element method (FEM) analysis of the LSEM process to understand the evolution of temperature field, effective strain, and strain rate under different chip compression ratios. The cutting and thrust forces are also analyzed with respect to time. The results show that LSEM can produce very high strains by changing in the value of chip compression ratio, thereby enabling the production of nanostructured materials. The shape of the chip produced by LSEM can also be geometrically well constrained.
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Li, Guo Ning, Yan Yan Liu, Shuang Li Han, and Long Xu Jin. "Design of the JPEG2000 Compression System Based on ADV212." Applied Mechanics and Materials 602-605 (August 2014): 2761–64. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2761.

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This article in detail on the basis of the algorithm of JPEG2000 standard upon, is put forward based on the FPGA embedded processor MicroBlaze and ADV212 compression chip with the combination of high speed, real time image compression scheme. Experiments show that the scheme can realize the data rate of 520 Mbps largest real-time compression of image data, when the image compression ratio is 53:1, reconstruction image PSNR value can reach 36 dB.
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Pawade, Raju, Avinash Khadtare, Dhanashree Dhumal, and Vishal Wankhede. "Machinability Assessment in High Speed Turning of High Strength Temperature Resistant Superalloys." Journal of Advanced Manufacturing Systems 18, no. 04 (November 19, 2019): 595–623. http://dx.doi.org/10.1142/s021968671950032x.

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The paper discusses the effect of cutting parameters and cutting tool material on chip compression ratio, cutting forces and surface roughness in turning of high strength temperature resistant superalloys (HSTR). The experiments were performed in dry cutting environment on precision CNC lathe with fixed depth of cut of 0.5[Formula: see text]mm. Analytical model is developed to determine chip segmentation frequency, shear angle and shear strain and it is correlated with the machining parameters. The machinability of the selected superalloys is assessed in terms of cutting force, chip compression ratio and surface roughness. It is found from the experimental analysis cutting force magnitude is less at higher cutting speed for all the superalloys. Chip compression ratio is found maximum in case of Inconel 718 due to precipitation hardening of alloy and followed by Inconel 600 and Inconel 800. The chip segmentation frequency is high at lower cutting speed for Inconel 600 due significant strain hardening. Serrated chips are produced during machining of three selected superalloys and it is found that serrated tooth spacing decreases with cutting speed. Shear plane angle increases on cutting speed increases which effect tool workpiece contact length during machining resulted thin, short and snarled chips was produced. From analytical modeling it shows that shear strain decreases with cutting speed which indicate that at higher cutting speed material deformed elastically than plastically. The effect of cutting tool material is observed on the surface roughness. The better surface finish is obtained with coated carbide inserts as compared to ceramic inserts for all the selected superalloys. However, Inconel 800 shows higher surface roughness due to combination of (Ni–Cr–Fe) alloying element which is responsible for carburization of surface layer during machining.
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Pervaiz, Salman, Sathish Kannan, Saqib Anwar, and Dehong Huo. "Machinability analysis of dry and liquid nitrogen–based cryogenic cutting of Inconel 718: experimental and FE analysis." International Journal of Advanced Manufacturing Technology 118, no. 11-12 (October 18, 2021): 3801–18. http://dx.doi.org/10.1007/s00170-021-08173-1.

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Abstract Inconel 718 is famous for its applications in the aerospace industry due to its inherent properties of corrosion resistance, wear resistance, high creep strength, and high hot hardness. Despite the favorable properties, it has poor machinability due to low thermal conductivity and high hot hardness. To limit the influence of high cutting temperature in the cutting zone, application of cutting flood is recommended during the cutting operation. Cryogenic cooling is the recommended method when machining Inconel 718. However, there is very limited literature available when it comes to the numerical finite element modeling of the process. This current study is focused on the machinability analysis of Inconel 718 using numerical approach with experimental validations. Dry and cryogenic cooling methods were compared in terms of associated parameters such as chip compression ratio, shear angle, contact length, cutting forces, and energy consumption for the primary and secondary deformation zones. In addition, parameters related to chip morphology were also investigated under both lubrication methods. Chip formation in cryogenic machining was well captured by the finite element assisted model and found in good agreement with the experimental chip morphology. Both experimental and numerical observations revealed comparatively less chip compression ratio in the cryogenic cooling with larger value of shear plane angle. This results in the smaller tool–chip contact length and better comparative lubrication.
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Bhuvaneshwari, P., and T. R. Jaya Chandra Lekha. "Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 4 (April 1, 2020): 1852–56. http://dx.doi.org/10.1166/jctn.2020.8453.

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This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.
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Wu, Xian, Yu Zhou, Congfu Fang, Laifa Zhu, Feng Jiang, Ke Sun, Yuan Li, and Yiyang Lin. "Experimental Investigation on the Machinability Improvement in Magnetic-Field-Assisted Turning of Single-Crystal Copper." Micromachines 13, no. 12 (December 4, 2022): 2147. http://dx.doi.org/10.3390/mi13122147.

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The single-point diamond-turning operation is a commonly used method for ultra-precision machining of various non-ferrous materials. In this paper, a magnetic field was introduced into a single-point diamond-turning system, and magnetic-field-assisted turning experiments were carried out. The results revealed that the magnetic field affects the metal-cutting process in the form of the cutting force, chip morphology, and surface quality. Compared with traditional turning, magnetic-field assisted turning increases the cutting force by 1.6 times, because of the additional induced Lorentz force, and reduces the cutting-force ratio and friction coefficient on the rake surface by 16%, with the improved tribological property of the tool/chip contact-interface. The chip morphology in the magnetic-field-assisted turning shows the smaller chip-compression ratio and the continuous side-morphology. With the magnetoplasticity effect of the metal material and the friction reduction, magnetic-field-assisted turning is helpful for improving metal machinability and achieving better surface-quality.
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Liu, Yan Yan, Yin Han Gao, Guo Ning Li, Wen Hua Wang, Ran Feng Zhang, and Long Xu Jin. "Design of High Speed and Parallel Compression System Used in the Big Area CCD of High Frame Frequency." Advanced Materials Research 411 (November 2011): 488–96. http://dx.doi.org/10.4028/www.scientific.net/amr.411.488.

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According to the area CCD camera of characteristics, such as high resolution capacity and high frame frequency, this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly, according to the work principle of the area CCD, FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly, with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip, real time image compression and the high speed area CCD are realized. Finally, by detecting the analog signal of the area CCD output, the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15, the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated, which reduces the data transmission between them and improves systematic integration degree.
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Jackson, Mark J., Jameson K. Nelson, Michael D. Whitfield, Jonathan S. Morrell, Rodney G. Handy, and Peter L. Schmidt. "Chip formation and similarity in the plano-grinding of explosive surrogates." Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture 232, no. 12 (January 6, 2017): 2071–82. http://dx.doi.org/10.1177/0954405416683972.

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The processing of polymer-bonded explosives is not widely reported in the literature, especially the machining of explosive surrogates in the combined planing and grinding operation known as plano-grinding. The process of machining long pieces of an inert substitute using a wax binder to hold sugar particles together and then subjecting the surrogate material to a linear cutting motion to generate chip fragments is described. The aim and purpose of this work is to analyze the machining of explosive surrogates in terms of chip formation models (oscillating and stress ratio models) and similarity models (chip compression ratio, Poletica, and Peclet numbers). The analysis of machining is compared to standard engineering materials so that the explosives engineer can benchmark machining performance of explosive surrogates to standard materials. The article concludes with statements on how to improve the understanding of machining of explosive surrogates with specifically engineered abrasive cutting tools.
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Huang, Guilin, Zhengjin Zhang, Honghai Wang, Jiabao Jiang, and Qilin Wu. "Encoding Test Pattern of System-on-Chip (SOC) Using Annular Scan Chain." Security and Communication Networks 2022 (September 2, 2022): 1–7. http://dx.doi.org/10.1155/2022/6974101.

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With the improvement of System-on-Chip integration, the chip requires an increasingly large amount of test data. To solve the contradiction between the storage capacity and bandwidth of automatic test equipment (ATE), a new method of test data compression/decompression is proposed based on an annular scan chain. Corresponding fault bits of different test patterns are incompatible, moving test patterns in an annular scan chain, makes all of the new corresponding bits of different test patterns be compatible or backward-compatible, so different adjacent test patterns form a new relation that are indirectly compatible or indirectly backward-compatible, achieves the purpose of test data compression by encoding these indirectly compatible test patterns or indirectly backward-compatible test patterns. According to experimental results, the average compression ratio increases by %6.94 to % 15.1 compared with the other schemes, relative decompression architecture is simple. In the annular scan chain, the test pattern moves clockwise with the minimal bits, generating subsequent test patterns quickly, it is advantageous to reduce the test application time of a single IP core.
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Book chapters on the topic "Chip-compression ratio"

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Gonciari, Paul Theo, Bashir M. Al-Hashimi, and Nicola Nicolici. "Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-Chip Test Data Compression/Decompression." In Design, Automation, and Test in Europe, 479–95. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-6488-3_35.

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"Appendix B Experimental determination of the chip Compression ratio (CCR)." In Tribology of Metal Cutting, 414–17. Elsevier, 2006. http://dx.doi.org/10.1016/s0167-8922(06)80010-6.

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Conference papers on the topic "Chip-compression ratio"

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Heppner, Joshua D., David C. Walther, and Albert P. Pisano. "ARCTIC: A Rotary Compressor Thermally Insulated µCooler." In ASME 2005 International Mechanical Engineering Congress and Exposition. ASMEDC, 2005. http://dx.doi.org/10.1115/imece2005-82142.

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Microscale cooling to date relies largely on passive on-chip cooling in order to move heat from hot spots to alternate sites. Such passive cooling devices include capillary pump loops (CPL), heat pipes, and thermosiphons. Recent developments for active cooling systems include thermal electric coolers (TECs) for heat removal. This paper focuses on the design of an active microscale closed loop cooling system that uses a Rankine vapor compression cycle cooling system. In this design, a rotary compressor will generate the high pressure required for efficient cooling and will circulate the working fluid to move heat away from chip level hot spots to the ambient. The rotary compressor will leverage technology gained from the Rotary Engine Power System (REPS) program at the UC Berkeley, most specifically the 367 mm3 displacement platform. The advantage of a Wankel (Maillard) compressor is that it provides six compression strokes per revolution rather than a single compression stroke common to other popular compressors such as the rolling piston. The current Wankel compressor design will achieve a theoretical compression ratio of 8:1. The ARCTIC (A Rotary Compressor Thermally Insulated μCooler) system will be a microscale hybrid system consisting of some microfabricated (or MEMS) components including microchannels, in plane MEMS valves, and potentially MEMS temperature, pressure and flow sensors integrated with mesoscale, traditionally machined steel components, including the compressor itself. The system is designed to remove between 25-35 W of heat at 1000 rpm using R-134a but the system is easily scaleable through a speed increase or decrease of the compressor. Further, the current compressor design has a theoretical coefficient of performance (C.O.P.) of approximately 2, a significant improvement over comparable TECs with C.O.P.s of approximately .05-.1. Finally, a thermal circuit analysis determines that the time constant to achieve refrigeration temperature in 12 seconds is possible.
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Cox, C., W. F. Schmidt, M. H. Gordon, W. Marsh, G. Bates, and M. Lucas. "Mechanical Considerations of Shin-Etsu Elastomer As a Z-Axis Interconnect." In ASME 2001 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2001. http://dx.doi.org/10.1115/imece2001/epp-24736.

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Abstract This research effort addresses the integration of a dense z-axis interconnect technology, Shin-Etsu, into a 3D thermo-mechanical multi-chip module with two to eight stack layers. Shin-Etsu is a matrix of vertical beryllium-copper wires embedded in silicone. Since it is a composite material, accurately determining Shin-Etsu’s mechanical properties is extremely important for estimating long-term reliability of the electronic package. Five percent compression of the Shin-Etsu elastomer was specified to maintain proper electrical contact between substrates. To determine the corresponding force, Tinius-Olsen compression tests up to 15% were conducted on both single and double layer samples of Shin-Etsu. In addition, these data were used to infer Shin-Etsu’s Young’s modulus. Both series of test were also conducted with and without alumina (A12O3) to simulate the contact surface boundary condition between Shin-Etsu and the LTCC substrate (2 pieces were used for the single Shin-Etsu case, and 3 pieces were used for the 2 layer Shin-Etsu case). All compression tests follow the same trends, though the sample to sample scatter is relatively large (+/−75%). Because Shin-Etsu’s Poisson’s ratio is near 0.5 (volume is conserved), the frictional forces between the contact surfaces is important. By carefully accounting for these frictional forces, we infer a Young’s modulus for Shin-Etsu of 3.25 MPa. Using this value with the appropriate contact model (we found that a simpler model with infinite friction is suitable in our case), we are able to successfully design a two-board test vehicle which incorporates Shin-Etsu.
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Liew, Li-Anne, Ching-Yi Lin, Alexander Yersak, Ryan Lewis, Collin Coolidge, and Y. C. Lee. "Atomic Layer Deposited TiO2 as Sacrificial Layers and Internal Coatings for Nanoscale Gaps." In ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/ipack2015-48814.

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A key component of the MEMS cryogenic cooling systems we are developing is a MEMS compressor. Its function is to compress the refrigerants used in the cooling cycle. Layers of polyimide are stacked and patterned on a silicon wafer to create micro check-valves and a compression chamber over which a diaphragm is suspended. To achieve the high (4:1) pressure ratio needed for the refrigeration cycle, the polyimide diaphragm needs to be fabricated with minimal dead volume beneath it, hence the need for a sacrificial layer with thickness of 100–300 nm. The topography created by the check-valves and valve-seats makes atomic layer deposition (ALD) ideal due to its conformality. Furthermore, following sacrificial layer release, the inside of the compression chamber will also need to be coated with a hermetic moisture barrier layer to enable the device to operate at 4 atmospheres without leaking. ALD is therefore also ideal for the final internal coating because it does not require line-of-sight. Towards this end, we demonstrate here the concept of using ALD TiO2 as a sacrificial layer to create a 5 mm × 5 mm × 20 m-thick polyimide membrane, suspended by ∼ 100–350 nm above a silicon wafer, followed by a second thinner ALD coating of the interior surfaces bounded by wafer and membrane. The air gap under the membrane, defined by the released sacrificial layer, was measured at about 130–370 nm using two independent methods: reflectometry, and FIB cross sectioning followed by SEM imaging of the air gap’s cross section. The membrane was removed from one chip and the thickness of the internal coating on the underlying silicon was measured with the reflectometer to be about 40 nm. We thus demonstrate the use of ALD TiO2 as both a sacrificial layer for fabricating nanoscale gaps, as well as for coating nanoscale internal cavities and channels.
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Airoldi, Roberto, Piia Saastamoinen, and Jari Nurmi. "Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression." In 2012 International Symposium on System-on-Chip - SOC. IEEE, 2012. http://dx.doi.org/10.1109/issoc.2012.6376371.

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