Relevant bibliographies by topics / Charge storage memory

Academic literature on the topic 'Charge storage memory'

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Published: 25 May 2024

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Journal articles on the topic "Charge storage memory"

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Mabrook, M. F., Youngjun Yun, C. Pearson, D. A. Zeze, and M. C. Petty. "Charge Storage in Pentacene/Polymethylmethacrylate Memory Devices." IEEE Electron Device Letters 30, no. 6 (June 2009): 632–34. http://dx.doi.org/10.1109/led.2009.2018128.

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Spassov, Dencho, and Albena Paskaleva. "Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks." Nanomaterials 13, no. 17 (August 30, 2023): 2456. http://dx.doi.org/10.3390/nano13172456.

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The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.
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Tsoukalas, Dimitris, S. Kolliopoulou, P. Dimitrakis, P. Normand, and M. C. Petty. "Nanoparticles for Charge Storage Using Hybrid Organic Inorganic Devices." Advances in Science and Technology 54 (September 2008): 451–57. http://dx.doi.org/10.4028/www.scientific.net/ast.54.451.

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We present a concept for integration of low temperature fabricated memory devices in a 3-D architecture using a hybrid silicon-organic technology. The realization of electrically erasable read-only memory (EEPROM) like device is based on the fabrication of a V-groove SiGe MOSFET, the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir-Blodgett (LB) technique. Such structures were processed at a temperature lower than 400°C following a process based on wafer bonding. The electrical characteristics of the final hybrid MISFET memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented.
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Gong, Changjie, Xin Ou, Bo Xu, Xuexin Lan, Yan Lei, Jianxin Lu, Yan Chen, et al. "Enhanced charge storage performance in AlTi4Ox/Al2O3multilayer charge trapping memory devices." Japanese Journal of Applied Physics 53, no. 8S3 (July 7, 2014): 08NG02. http://dx.doi.org/10.7567/jjap.53.08ng02.

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Tang, Zhen-Jie, Rong Li, and Jiang Yin. "The charge storage characteristics of ZrO2nanocrystallite-based charge trap nonvolatile memory." Chinese Physics B 22, no. 6 (June 2013): 067702. http://dx.doi.org/10.1088/1674-1056/22/6/067702.

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Tsoukalas, Dimitris, and Emanuele Verrelli. "Inorganic Nanoparticles for either Charge Storage or Memristance Modulation." Advances in Science and Technology 77 (September 2012): 196–204. http://dx.doi.org/10.4028/www.scientific.net/ast.77.196.

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We present prototype memory devices using metallic and metal oxide nanoparticles obtained by a physical deposition technique. The two memory device examples demonstrated concern the use of platinum nanoparticles for flash-type memories and the use of titanium oxide nanoparticles for resistive memories. Both approaches give interesting device memory properties with resistive memories being still in an early exploratory phase.
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Bandić, Zvonimir Z., Dmitri Litvinov, and M. Rooks. "Nanostructured Materials in Information Storage." MRS Bulletin 33, no. 9 (September 2008): 831–37. http://dx.doi.org/10.1557/mrs2008.178.

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AbstractThe ever-increasing demand for information storage has pushed research and development of nonvolatile memories, particularly magnetic disk drives and silicon-based memories, to areal densities where bit sizes are approaching nanometer dimensions. At this level, material and device phenomena make further scaling increasingly difficult. The difficulties are illustrated in the examples of magnetic media and flash memory, such as thermal instability of sub-100-nm bits in magnetic memory and charge retention in flash memory, and solutions are discussed in the form of patterned media and crosspoint memories. The materials-based difficulties are replaced by nanofabrication challenges, requiring the introduction of new techniques such as nanoimprinting lithography for cost-effective manufacturing and self-assembly for fabrication on the sub-25-nm scale. Articles in this issue describe block-copolymer lithographic fabrication of patterned media, materials studies on the scaling limits of phase-change-based crosspoint memories, nanoscale fabrication using imprint lithography, and biologically inspired protein-based memory.
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Lee, Meng Chuan, and Hin Yong Wong. "Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM." Journal of Nanomaterials 2013 (2013): 1–17. http://dx.doi.org/10.1155/2013/195325.

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Charge storage nonvolatile memory (NVM) is one of the main driving forces in the evolution of IT handheld devices. Technology scaling of charge storage NVM has always been the strategy to achieve higher density NVM with lower cost per bit in order to meet the persistent consumer demand for larger storage space. However, conventional technology scaling of charge storage NVM has run into many critical reliability challenges related to fundamental device characteristics. Therefore, further technology scaling has to be supplemented with novel approaches in order to surmount these reliability issues to achieve desired reliability performance. This paper is focused on reviewing critical research findings on major reliability challenges and technical solutions to mitigate technology scaling challenges of charge storage NVM. Most of these technical solutions are still in research phase while a few of them are more mature and ready for production phase. Three of the mature technical solutions will be reviewed in detail, that is, tunnel oxide top/bottom nitridation, nanocrystal, and phase change memory (PCM). Key advantages and reported reliability challenges of these approaches are thoroughly reviewed in this paper. This paper will serve as a good reference to understand the future trend of innovative technical solutions to overcome the reliability challenges of charge storage NVM due to technology scaling.
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Wang, Shuai, Jing Pu, Daniel S. H. Chan, Byung Jin Cho, and Kian Ping Loh. "Wide memory window in graphene oxide charge storage nodes." Applied Physics Letters 96, no. 14 (April 5, 2010): 143109. http://dx.doi.org/10.1063/1.3383234.

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Lee, Gae-Hun, Jung-Min Lee, Yun Heub Song, Ji Chel Bea, Tetsu Tanaka, and Mitsumasa Koyanagi. "Multilevel Charge Storage in a Multiple Alloy Nanodot Memory." Japanese Journal of Applied Physics 50, no. 9R (September 1, 2011): 095001. http://dx.doi.org/10.7567/jjap.50.095001.

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Dissertations / Theses on the topic "Charge storage memory"

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Lee, Yung-Huei. "Dual-carrier charge transport and damage formation of LPCVD nitride for nonvolatile memory devices /." The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487322984316841.

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Hetherington, Dale Laird. "III-V compound semiconductor integrated charge storage structures for dynamic and non-volatile memory elements." Diss., The University of Arizona, 1992. http://hdl.handle.net/10150/186112.

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This thesis presents an investigation into a novel group of GaAs charge storage devices. These devices, which are an integration of bipolar and junction field effect transistor structures were conceived, designed, fabricated, and tested within this study. The purpose was to analyse new types of charge storage devices, which are suitable for fabrication and lead to the development of dynamic and nonvolatile memories in III-V compound semiconductors. Currently, III-V semiconductor storage devices consist only of capacitors, where data is destroyed during reading and electrical erasure is difficult. In this work, four devices types were demonstrated that exhibit nondestructive reading, and three of the prototypes can be electrically erased. All types use the junction field effect transistor (JFET) for charge sensing, with each having different bipolar or epitaxial layer structure controlling the junction gate. The bottom epitaxial layer in each case served as the JFET channel. Two of the device types have three alternately doped layers, while the remaining two have four alternately doped layers. In all cases, removal of majority carriers from the middle layers constitutes stored charge. The missing carriers deplete the current carrying a region of the JFET channel. Drain current of the JFET becomes an indicator of stored charge. The basic function of each JFET memory element type is independent of interchanging n- and p- type doping within the structure type. Some performance advantage can be realized, however, by sensing with an n-type channel as compared to p- type due to increased carrier mobility. All device types exhibit storage time characteristics of order ten seconds. Devices are constructed in epitaxial layers grown by molecular beam epitaxy (MBE) reactors. The design of the epitaxial layers is an intrinsic part, together with the electrical design, of the storage device concept. These concepts are implemented first with photolithography masks which are used in device fabrication. The fabrication methods employ wet chemical etching and ohmic metal liftoff techniques. Electrical dc and charge retention time characteristics along with functionality read/write operations for the memory element group are measured using commercial electronic test equipment.
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Mazoyer, Pascale. "Analyse et caractérisation des mécanismes de perte de charge relatifs aux diélectriques multicouches du point mémoire EPROM." Université Joseph Fourier (Grenoble), 1994. http://www.theses.fr/1994GRE10009.

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L'evolution des memoires a semiconducteurs et en particulier de la famille eprom (erasable read only memory) est liee a l'identification des phenomenes determinants du processus de perte de la charge electronique stockee. Les cellules etudiees ici sont toutes proches des points de fonctionnement de filieres industrialisees ou en cours de developpement (de 4 a 256 megabits). On distingue deux mecanismes de perte de charge. Le premier est une fonction de la nature des dielectriques presents dans la structure et des lois qui regissent la conduction qui leur est associee. Le second est lie a la migration des ions alcalins dans la cellule. Partant de l'analyse des proprietes de la tricouche ono (oxyde nitrure oxyde) et en emettant l'hypothese de l'injection d'electrons en fin d'ecriture, un modele de perte de charge est propose. Il est base sur l'emission electronique assistee en temperature et la migration des electrons a travers l'ono. Les mesures de perte de charge montrent qu'il ne faut pas descendre, dans la realisation de l'ono, en deca de l'epaisseur tunnel de chaque couche et que l'obtention de couche d'epaisseur homogene et stchiometrique ameliore la fiabilite du dispositif. Cette analyse conduit, de meme, a la proposition d'un dielectrique adapte aux applications tres avancees. Forme par l'association de nitrure et d'oxyde, le no apparait comme un candidat interessant les generations eprom et flash eprom 256 mb. L'etude des contaminants ioniques a mis en uvre la methode tvs, qui s'avere un outil puissant, permettant l'evaluation rapide et precise de la densite d'ions mobile dans les dielectriques epais. Une solution economiquement viable a ete mise au point pour prevenir les effets d'une eventuelle contamination sur le plan memoire. Il s'agit de la juxtaposition judicieuse d'un verre au phosphore et d'un verre au bore et au phosphore
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Habhab, Radouane. "Optimisation d'architectures mémoires non-volatiles à piégeage de charges pour les applications microcontrôleur et mémoire autonome." Electronic Thesis or Diss., Université Côte d'Azur, 2023. http://www.theses.fr/2023COAZ4102.

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L'objectif de ces travaux de thèse est d'évaluer les performances en programmation/cyclage/rétention d'une cellule mémoire SONOS basée sur une architecture split gate très innovante développée par STMicroelectronics, l'eSTM (embedded Select in Trench Memory). Dans un premier temps, nous expliquons la réalisation de cette mémoire SONOS qui est basée sur une modification de la mémoire eSTM à grille flottante, cette modification se faisant sans coût supplémentaire. Dans un second temps, nous étudions les mécanismes de programmation et d'effacement les plus performants pour cette mémoire ce qui nous amène aussi à proposer une nouvelle architecture de mémoire SONOS. Dans un troisième temps, nous caractérisons électriquement les phases de programmation de la cellule SONOS eSTM pour les deux architectures disponibles : dual gate et overlap. Pour la mémoire dual gate, les deux cellules mémoires de part et d'autre du transistor de sélection ont chacune leur propre empilement de grille « ONO/grille de contrôle ». Pour la mémoire overlap, la couche ONO est commune aux deux cellules mémoires. Même si cette couche est partagée, la mémorisation de l'information dans l'ONO est localisée uniquement sous la grille de contrôle concernée grâce à la nature discrète du piégeage des charges. Le mécanisme mis en œuvre pour les opérations d'écriture et d'effacement est d'injection de porteurs chauds et nous détaillons l'optimisation des polarisations (différentes pour les deux architectures disponibles) de drain et de grille de sélection qui permettent de définir les tensions de seuil écrite et effacée. Nous effectuons alors des tests d'endurance jusqu'à un million de cycles pour les deux architectures. Finalement, nous menons une étude en rétention et en de pompage de charge pour connaitre la qualité d'oxyde à l'interface de nos cellules. Dans un quatrième temps, nous cherchons à mieux comprendre le fonctionnement du transistor mémoire et la variabilité de l'eSTM à l'aide simulations TCAD et de mesures électriques sur des structures de géométries variées
The aim of this thesis work is to evaluate the performance in programming/cycling/retention of a SONOS memory cell based on a highly innovative split-gate architecture developed by STMicroelectronics, the eSTM™ (embedded Select in Trench Memory). Firstly, we explain the realization of this SONOS memory, which is based on a process step modification of the floating gate eSTM™ memory, with this modification carried out without additional cost.Secondly, we investigate the most efficient program and erase mechanisms for this memory, which also leads us to propose a new SONOS memory architecture. Thirdly, we electrically characterize the P/E activations of the SONOS eSTM™ cell for the two available architectures: dual gate and overlap. For dual gate memory, both memory cells on either side of the selection transistor have their own "ONO/control gate" stack. For overlap memory, the ONO layer is common to both memory cells. Even though this layer is shared, the information storage in ONO is localized only under the relevant control gate due to the discrete nature of charge trapping. The mechanism implemented for write and erase operations is carrier hot injection, and we detail the optimization of biases (different for the two available architectures) of the drain and select gate, which define the written and erased threshold voltages. We then perform endurance tests up to one million cycles for both architectures. Finally, we conduct a study on retention and charge pumping to assess the oxide quality at the interface of our cells. In a fourth phase, we seek to better understand the operation of the memory transistor and the variability of eSTM™ using TCAD simulations and electrical measurements on structures with various geometries
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Srowik, Rico. "Modellierung von Transistoren mit lokaler Ladungsspeicherung für den Entwurf von Flash-Speichern." Doctoral thesis, Technische Universität Dresden, 2007. https://tud.qucosa.de/id/qucosa%3A24067.

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In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert.
In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.
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Srowik, Rico. "Modellierung von Transistoren mit lokaler Ladungsspeicherung für den Entwurf von Flash-Speichern." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1206006642261-96038.

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In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert
In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples
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7

Seong, Nak Hee. "A reliable, secure phase-change memory as a main memory." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50123.

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The main objective of this research is to provide an efficient and reliable method for using multi-level cell (MLC) phase-change memory (PCM) as a main memory. As DRAM scaling approaches the physical limit, alternative memory technologies are being explored for future computing systems. Among them, PCM is the most mature with announced commercial products for NOR flash replacement. Its fast access latency and scalability have led researchers to investigate PCM as a feasible candidate for DRAM replacement. Moreover, the multi-level potential of PCM cells can enhance the scalability by increasing the number of bits stored in a cell. However, the two major challenges for adopting MLC PCM are the limited write endurance cycle and the resistance drift issue. To alleviate the negative impact of the limited write endurance cycle, this thesis first introduces a secure wear-leveling scheme called Security Refresh. In the study, this thesis argues that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. Security Refresh can avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. In addition to the secure wear-leveling scheme, this thesis also proposes SAFER, a hardware-efficient multi-bit stuck-at-fault error recovery scheme which can function in conjunction with existing wear-leveling techniques. The limited write endurance leads to wear-out related permanent failures, and furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data; thereby reducing the hardware overhead for error recovery. Another approach that this thesis proposes to address the lower write endurance is a hybrid phase-change memory architecture that can dynamically classify, detect, and isolate frequent writes from accessing the phase-change memory. This proposed architecture employs a small SRAM-based Isolation Cache with a detection mechanism based on a multi-dimensional Bloom filter and a binary classifier. The techniques are orthogonal to and can be combined with other wear-out management schemes to obtain a synergistic result. Lastly, this thesis quantitatively studies the current art for MLC PCM in dealing with the resistance drift problem and shows that the previous techniques such as scrubbing or error correction schemes are incapable of providing sufficient level of reliability. Then, this thesis proposes tri-level-cell (3LC) PCM and demonstrates that 3LC PCM can be a viable solution to achieve the soft error rate of DRAM and the performance of single-level-cell PCM.
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Barclay, Martin Jared. "Electrical switching properties of ternary and layered chalcogenide phase-change memory devices." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/67/.

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Gao, Shen. "Transaction logging and recovery on phase-change memory." HKBU Institutional Repository, 2013. http://repository.hkbu.edu.hk/etd_ra/1549.

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Balasubramanian, Mahesh. "Phase change memory : array development and sensing circuits using delta-sigma modulation /." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/44/.

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Books on the topic "Charge storage memory"

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1976-, Chen Yiran, ed. Nonvolatile memory design: Magnetic, resistive, and phase change. Boca Raton, FL: Taylor & Francis, 2012.

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1969-, Luminet Olivier, and Curci Antonietta 1969-, eds. Flashbulb memories: New issues and new perspectives. Hove (UK): Psychology Press, 2009.

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Chen, Yiran, and Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.

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Li, Hai. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2011.

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Chen, Yiran, and Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.

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Chen, Yiran, and Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.

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Chen, Yiran, and Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.

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Chen, Yiran, and Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.

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Luminet, Olivier, and Antonietta Curci. Flashbulb Memories: New Challenges and Future Perspectives. Taylor & Francis Group, 2017.

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Luminet, Olivier, and Antonietta Curci. Flashbulb Memories: New Challenges and Future Perspectives. Taylor & Francis Group, 2017.

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Book chapters on the topic "Charge storage memory"

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Shi, Luping, Rong Zhao, and Tow C. Chong. "Phase Change Random Access Memory." In Developments in Data Storage, 277–96. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118096833.ch13.

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Shen, Xiang, Yimin Chen, Guoxiang Wang, and Yegang Lv. "Phase-Change Memory and Optical Data Storage." In Springer Handbook of Glass, 1495–520. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-93728-1_44.

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Ricci, Saverio, Piergiulio Mannocci, Matteo Farronato, Alessandro Milozzi, and Daniele Ielmini. "Development of Crosspoint Memory Arrays for Neuromorphic Computing." In Special Topics in Information Technology, 65–74. Cham: Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-51500-2_6.

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AbstractMemristor-based hardware accelerators play a crucial role in achieving energy-efficient big data processing and artificial intelligence, overcoming the limitations of traditional von Neumann architectures. Resistive-switching memories (RRAMs) combine a simple two-terminal structure with the possibility of tuning the device conductance. This Chapter revolves around the topic of emerging memristor-related technologies, starting from their fabrication, through the characterization of single devices up to the development of proof-of-concept experiments in the field of in-memory computing, hardware accelerators, and brain-inspired architecture. Non-volatile devices are optimized for large-size crossbars where the devices’ conductance encodes mathematical coefficients of matrices. By exploiting Kirchhoff’s and Ohm’s law the matrix–vector-multiplication between the conductance matrix and a voltage vector is computed in one step. Eigenvalues/eigenvectors are experimentally calculated according to the power-iteration algorithm, with a fast convergence within about 10 iterations to the correct solution and Principal Component Analysis of the Wine and Iris datasets, showing up to 98% accuracy comparable to a floating-point implementation. Volatile memories instead present a spontaneous change of device conductance with a unique similarity to biological neuron behavior. This characteristic is exploited to demonstrate a simple fully-memristive architecture of five volatile RRAMs able to learn, store, and distinguish up to 10 different items with a memory capability of a few seconds. The architecture is thus tested in terms of robustness under many experimental conditions and it is compared with the real brain, disclosing interesting mechanisms which resemble the biological brain.
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Polzer, Miriam, and Sergey Goncharov. "Local Local Reasoning: A BI-Hyperdoctrine for Full Ground Store." In Lecture Notes in Computer Science, 542–61. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-45231-5_28.

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AbstractModelling and reasoning about dynamic memory allocation is one of the well-established strands of theoretical computer science, which is particularly well-known as a source of notorious challenges in semantics, reasoning, and proof theory. We capitalize on recent progress on categorical semantics of full ground store, in terms of a full ground store monad, to build a corresponding semantics of a higher order logic over the corresponding programs. Our main result is a construction of an (intuitionistic) BI-hyperdoctrine, which is arguably the semantic core of higher order logic over local store. Although we have made an extensive use of the existing generic tools, certain principled changes had to be made to enable the desired construction: while the original monad works over total heaps (to disable dangling pointers), our version involves partial heaps (heaplets) to enable compositional reasoning using separating conjunction. Another remarkable feature of our construction is that, in contrast to the existing generic approaches, our BI-algebra does not directly stem from an internal categorical partial commutative monoid.
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Cappelletti, Paolo, and Jon Slaughter. "Embedded memory solutions: Charge storage based, resistive and magnetic." In Semiconductor Memories and Systems, 159–215. Elsevier, 2022. http://dx.doi.org/10.1016/b978-0-12-820758-1.00007-8.

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Molas, G., L. Masoero, V. Della Marca, G. Gay, and B. De Salvo. "Improving embedded Flash memory technology: silicon and metal nanocrystals, engineered charge-trapping layers and split-gate memory architectures." In Advances in Non-volatile Memory and Storage Technology, 120–57. Elsevier, 2014. http://dx.doi.org/10.1533/9780857098092.1.120.

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Roy, Sourav. "Resistive Memory with Functional Duality-Non Volatile Emerging Memory & Nano Biosensors." In Memristors - the Fourth Fundamental Circuit Element - Theory, Device, and Applications [Working Title]. IntechOpen, 2023. http://dx.doi.org/10.5772/intechopen.1002783.

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Resistive Memory in recent year has emerged as a potential candidate in the field of Non Volatile Memory to solve the existing problems with FLASH. The operation novelty of ReRAM helps to evolve it from storage device to an effective ultra sensitive biomarker with a very simple structure and fabrication process steps. Basically as ReRAM is MIM capacitor like structure so for store data in terms of charge like DRAM is feasible effectively and at the same time capacitor as we know can be excellent for bioanalyte detection. So with same structure two purpose can be solved. Also we can see in this chapter that the biosensors with ReRAM will detect on Current -Voltage sampling method which is more efficient to detect with low sample volume. This chapter will give the readers a brief idea about the work done and ongoing research on Resistive memory as Non Volatile Memory as well as its potentiality as Biosensor.
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Chand Verma, Kuldeep. "Synthesis and Characterization of Multiferroic BiFeO3 for Data Storage." In Bismuth - Fundamentals and Optoelectronic Applications. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.94049.

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Multiferroic BiFeO3 deals with spintronic devices involved spin-charge processes and applicable in new non-volatile memory devices to store information for computing performance and the magnetic random access memories storage. Since multiferroic leads to the new generation memory devices for which the data can be written electrically and read magnetically. The main advantage of present study of multiferroic BiFeO3 is that to observe magnetoelectric effects at room temperature. The nanostructural growth (for both size and shape) of BiFeO3 may depend on the selection of appropriate synthesis route, reaction conditions and heating processes. In pure BiFeO3, the ferroelectricity is induced by 6s2 lone-pair electrons of Bi3+ ions and the G-type antiferromagnetic ordering resulting from Fe3+ spins order of cycloidal (62-64 nm wavelength) occurred below Neel temperature, TN = 640 K. The multiferroicity of BiFeO3 is disappeared due to factors such as impurity phases, leakage current and low value of magnetization. Therefore, to overcome such factors to get multiferroic enhancement in BiFeO3, there are different possible ways like changes dopant ions and their concentrations, BiFeO3 composites as well as thin films especially multilayers.
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Wang, Dingchen, Shuhui Shi, Yi Zhang, Dashan Shang, Qing Wang, Hongyu Yu, and Zhongrui Wang. "Stochastic Emerging Resistive Memories for Unconventional Computing." In Advanced Memory Technology, 240–69. Royal Society of Chemistry, 2023. http://dx.doi.org/10.1039/bk9781839169946-00240.

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Stochasticity plays a critical role in biological neural systems, which also inspires various statistical learning approaches. However, conventional digital electronics on silicon-based transistors practice deterministic Boolean logic, making it less favorable for solving problems involving stochasticity. This is further intensified by the von Neumann bottleneck of digital systems and the slowdowns of Moore’s law. Emerging resistive memory, such as those based on redox reactions and phase transitions, features intrinsic stochasticity due to their underlying physical mechanisms. In addition, such devices integrate storage and computing functions, like that of the brain. They are also endowed with superior scalability and stack-ability due to their simple and low-cost structures. In this chapter, we will survey the broad spectrum of unconventional computing applications of stochastic emerging resistive memories (RMs) from their physics origin to system-level applications. Firstly, we review the mainstream resistive memories and the origin of stochasticity in both programming and charge transport. Secondly, we explore how the stochasticity of RMs benefits bio-inspired computing, including artificial neural networks, spiking neural networks, and reservoir computing. Thirdly, we discuss how stochasticity benefits energy-based networks, such as Hopfield networks, in solving optimization problems. Fourthly, we survey the applications to cybersecurity, including how the cycle-to-cycle (C2C) variation is leveraged for random number generation and how the device-to-device (D2D) variation contributes to hardware identities. Last but not least, we introduce RM-based probability bit generation and bit stream decorrelation for probabilistic computing, with applications to Bayesian neural networks and Markov chain Monte Carlo algorithms.
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"Phase-Change Random Access Memory." In Data Storage at the Nanoscale, 485–612. Jenny Stanford Publishing, 2015. http://dx.doi.org/10.1201/b18094-13.

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Conference papers on the topic "Charge storage memory"

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Shinn, Charles E. "Charge Constrained (1,7) Code For Magneto Optic Recording." In Optical Data Storage. Washington, D.C.: Optica Publishing Group, 1987. http://dx.doi.org/10.1364/ods.1987.thb4.

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Modulation codes are used in disc memory applications to limit the distance between transitions, control the spectral distribution of the data stream, and to maximize the data capacity. Because of their high density ratios the class of codes known as Run Length Limited (RLL) codes have become dominant in the magnetic disc recording industry.
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Lee, Sung-Tae, Suhwan Lim, Nagyong Choi, Jong-Ho Bae, Chul-Heung Kim, Soochang Lee, Dong Hwan Lee, et al. "Neuromorphic Technology Based on Charge Storage Memory Devices." In 2018 IEEE Symposium on VLSI Technology. IEEE, 2018. http://dx.doi.org/10.1109/vlsit.2018.8510667.

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Hussein Ali Alabdulqader and Samah Abdulkarim. "MIOS memory devices and their charge storage properties." In 2010 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2010. http://dx.doi.org/10.1109/icedsa.2010.5503056.

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Molas, G., J. P. Colonna, R. Kies, D. Belhachemi, M. Bocquet, M. Gely, V. Vidal, et al. "Investigation of charge-trap memories with AlN based band engineered storage layers." In 2010 IEEE International Memory Workshop. IEEE, 2010. http://dx.doi.org/10.1109/imw.2010.5488309.

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Lee, C. H., C. W. Wu, S. W. Lin, T. H. Yeh, S. H. Gu, K. F. Chen, Y. J. Chen, et al. "Numerical Simulation of Programming Transient Behavior in Charge Trapping Storage Memory." In 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design. IEEE, 2008. http://dx.doi.org/10.1109/nvsmw.2008.38.

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Misra, Abhishek, Hemen Kalita, Mayur Waikar, Amit Gour, Meenakshi Bhaisare, Manali Khare, Mohhamad Aslam, and Anil Kottantharayil. "Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory." In 2012 4th IEEE International Memory Workshop (IMW). IEEE, 2012. http://dx.doi.org/10.1109/imw.2012.6213626.

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Xiaoxiao Zhu, Qiliang Li, Dimitris E. Ioannou, William A. Kimes, John S. Suehle, James E. Maslar, Hao D. Xiong, Shuo Yang, and Curt A. Richter. "Silicon nanowire memory application using hafnium oxide charge storage layer." In 2007 International Semiconductor Device Research Symposium. IEEE, 2007. http://dx.doi.org/10.1109/isdrs.2007.4422492.

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Kaur, Ramneek, and S. K. Tripathi. "Charge storage effects in doped polymer nanocomposite for memory device application." In ADVANCED MATERIALS AND RADIATION PHYSICS (AMRP-2015): 4th National Conference on Advanced Materials and Radiation Physics. AIP Publishing LLC, 2015. http://dx.doi.org/10.1063/1.4929191.

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Yang, Shao-Ming, Jiun-Jia Huang, Chao-Hsin Chien, Pei-Jer Taeng, Lurng-Shehng Lee, Ming-Jinn Tsai, and Tan-Fu Lei. "High Charge Storage Characteristics of CeO2 Nanocrystals for Novolatile Memory Applications." In 2008 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA). IEEE, 2008. http://dx.doi.org/10.1109/vtsa.2008.4530792.

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Liu, S. H., W. L. Yang, C. W. Chiu, and T. S. Chao. "High Efficiency Charge Storage Layer for MLC NAND Non-Volatile Memory." In 2010 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2010. http://dx.doi.org/10.7567/ssdm.2010.p-4-8.

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