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Journal articles on the topic 'Charge pump current mismatch'

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Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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1

Hwang, M. S., J. Kim, and D. K. Jeong. "Reduction of pump current mismatch in charge-pump PLL." Electronics Letters 45, no. 3 (2009): 135. http://dx.doi.org/10.1049/el:20092727.

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2

Liu, Lianxi, Shaopu Gao, Junchao Mu, and Zhangming Zhu. "A Low Power and Low Current-Mismatch Charge Pump with Dynamic Current Compensation." Journal of Circuits, Systems and Computers 28, no. 12 (November 2019): 1920007. http://dx.doi.org/10.1142/s021812661920007x.

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A novel low power charge pump (CP) that minimizes the mismatch between the charging and the discharging currents is proposed in this paper. The switching circuit with dynamic current compensation is used to reduce the power consumption of the proposed CP. In addition, precise current replication which makes use of the resistors and the low offset operational amplifiers (OTA) can enable a reduction in current mismatch caused by process mismatch. Meanwhile, the high output impedance can reduce the current mismatch caused by the channel length modulation effect. Based on the 0.18[Formula: see text][Formula: see text]m deep-Nwell CMOS process, the proposed CP can reduce the overall power consumption by 56% compared with the CP without current compensation, reduce the current mismatch caused by process mismatch to less than 0.9% and reduce the current mismatch caused by the channel length modulation effect to less than 0.01% over the output voltage ranging from 0.3 to 1.5[Formula: see text]V with 1.8[Formula: see text]V supply.
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3

Joram, N., R. Wolf, and F. Ellinger. "High swing PLL charge pump with current mismatch reduction." Electronics Letters 50, no. 9 (April 2014): 661–63. http://dx.doi.org/10.1049/el.2014.0804.

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4

D S, Rajeshwari, P. V Rao, and Ramesh Karmungi. "10Ghz Charge Pump PLL for Low Jitter Applica-tions." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 348. http://dx.doi.org/10.14419/ijet.v7i2.12.11349.

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This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files
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5

Zhang, G. "Linearised charge pump independent of current mismatch through timing rearrangement." Electronics Letters 46, no. 1 (2010): 33. http://dx.doi.org/10.1049/el.2010.2555.

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6

Guo, Rui, Zhenghao Lu, Shaogang Hu, Qi Yu, Limei Rong, and Yang Liu. "Design and Verification of a Charge Pump in Local Oscillator for 5G Applications." Electronics 10, no. 9 (April 23, 2021): 1009. http://dx.doi.org/10.3390/electronics10091009.

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A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design.
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7

Byun, Sangjin, and Jae Hoon Shim. "Charge Pump circuit with wide range digital leakage current mismatch compensator." IEICE Electronics Express 7, no. 23 (2010): 1709–13. http://dx.doi.org/10.1587/elex.7.1709.

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8

Zulkalnain, Mohd Khairi, and Yan Chiew Wong. "Current mismatch reduction in charge pumps using regulated current stealing-injecting transistors for PLLs." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 1 (October 1, 2021): 61. http://dx.doi.org/10.11591/ijeecs.v24.i1.pp61-69.

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A charge pump for phase locked loops (PLL) with a novel current mismatch compensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The proposed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.
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9

Yu, Cao, Min Su Kim, Hyung Chul Kim, and Youn Goo Yang. "A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application." Advanced Materials Research 457-458 (January 2012): 1178–82. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1178.

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A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.
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10

Zhai, Yannan, Ling Gao, Jingquan Li, and Qangli Qiu. "A Design of fast-setting on-chip Charge Pump Circuit." Journal of Physics: Conference Series 2195, no. 1 (February 1, 2022): 012034. http://dx.doi.org/10.1088/1742-6596/2195/1/012034.

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Abstract A circuit of fast-setting charge pump on-chip is designed based on the Dickson circuit. The charge pump circuit, which is improved, increases the initial node voltage. With the consideration of the current mismatch, the accurate clock of the duty circle below 50% is proposed. The HSPICE simulation result indicates that the setting time from 0V to 20V only needs 51.650μs for the charge pump, and it is faster than the traditional Dickson charge pump 26.03μs. In summary, the settling time of the output voltage of the charge pump is prominently decreased and the performance of the charge pump is obviously improved.
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11

Chen, Yating, Yan Han, and Sihui Wang. "A high swing charge pump with current mismatch reduction for PLL applications." IEICE Electronics Express 18, no. 4 (February 25, 2021): 20200434. http://dx.doi.org/10.1587/elex.18.20200434.

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12

Biswas, Debdut, and Tarun Kanti Bhattacharyya. "Charge pump with reduced current mismatch for reference spur minimization in PLLs." Analog Integrated Circuits and Signal Processing 95, no. 2 (March 17, 2018): 209–21. http://dx.doi.org/10.1007/s10470-018-1163-z.

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13

YOSHIOKA, Masahiro, and Nobuo FUJII. "Reduction of Charge Injection and Current-Mismatch Errors of Charge Pump for Phase-Locked Loop." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 2 (2009): 381–88. http://dx.doi.org/10.1587/transfun.e92.a.381.

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14

D S, Rajeshwari, and P. V. Rao. "Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- DPLL." International Journal of Engineering Research and Applications 07, no. 05 (May 2017): 13–17. http://dx.doi.org/10.9790/9622-0705041317.

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15

Manikandan, R. R., and Bharadwaj Amrutur. "A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs." Microelectronics Journal 46, no. 6 (June 2015): 422–30. http://dx.doi.org/10.1016/j.mejo.2015.03.004.

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16

Lozada, Oscar, and Guillermo Espinosa. "A charge pump with a 0.32 % of current mismatch for a high speed PLL." Analog Integrated Circuits and Signal Processing 86, no. 2 (December 29, 2015): 321–26. http://dx.doi.org/10.1007/s10470-015-0676-y.

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17

Wei, Xueming, Renchuan Yin, Lingli Hou, Weilin Xu, and Baolin Wei. "Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch." Electronics 11, no. 14 (July 7, 2022): 2133. http://dx.doi.org/10.3390/electronics11142133.

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A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occupies 1.3% of the whole PLL area.
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18

B. Mane, Pradeep, and Shobha N. Pawar. "An Ultra Low Current Mismatch Charge Pump and Loop Filter in 0.18um CMOS Process for Low Spur PLL Applications." International Journal of Engineering Trends and Technology 69, no. 6 (June 25, 2021): 14–24. http://dx.doi.org/10.14445/22315381/ijett-v69i6p203.

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19

Kang, Li, Juncai Lv, and Xu Cheng. "A 5.42~6.28 GHz Type-II PLL with Dead-Zone Programmability and Charge Pump Mismatch Trimming." Electronics 11, no. 24 (December 13, 2022): 4153. http://dx.doi.org/10.3390/electronics11244153.

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This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoMT is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature.
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20

Wang, Weiyin, Xiangjie Chen, and Hei Wong. "A system-on-chip 1.5 GHz phase locked loop realized using 40 nm CMOS technology." Facta universitatis - series: Electronics and Energetics 31, no. 1 (2018): 101–13. http://dx.doi.org/10.2298/fuee1801101w.

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This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifier-feedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.
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21

Zhao, C., D. Guo, Q. Chen, Z. Guo, R. Arteche, C. Ceballos, N. Fang, et al. "A low noise 5.12 GHz PLL ASIC in 55 nm for NICA multi purpose detector project." Journal of Instrumentation 17, no. 09 (September 1, 2022): C09003. http://dx.doi.org/10.1088/1748-0221/17/09/c09003.

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Abstract This paper presents the design and the test results of a low noise PLL ASIC for the optical data transmission system in NICA MPD project. In the proposed PLL, a novel charge pump circuit uses two feedback operational amplifiers to obtain low leakage current and reduce dynamic mismatch. A LC-VCO circuit combines the two-step capacitor tuning structure and the novel capacitor array unit to obtain a reasonable frequency range and an optimized Q factor performance. The PLL ASIC has been fabricated in a 55 nm CMOS process. The test results show that the PLL ASIC outputs the 5.12 GHz clock with a phase noise of −108 dBc/Hz at 1 MHz offset and a rms jitter of 880 fs. The PLL core consumes 22.2 mW from a 1.2 V power supply.
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22

Azadbakht, Mostafa, Ali Sahafi, and Esmaeil Najafi Aghdam. "A Dual Band Fractional-N Frequency Synthesizer with a Self-Calibrated Charge Pump for WLAN Standards." Journal of Circuits, Systems and Computers 27, no. 08 (April 12, 2018): 1850131. http://dx.doi.org/10.1142/s0218126618501311.

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This work presents a fully integrated fractional-[Formula: see text] frequency synthesizer that covers the entire frequency bands specified in the IEEE 802.11 a/b/g/n. In this paper, the effects of charge pump (CP) gain mismatch on spectral purity of local oscillator signal is studied theoretically and a new high precision self-calibrated CP is presented for alleviating the nonidealities. The idea is implemented in a 0.18-[Formula: see text]m standard CMOS technology. According to post layout simulation, the proposed calibration circuit demonstrates an excellent matching in the CP currents in a wide voltage range. By using this technique, the average of close-in phase noise of the designed frequency synthesizer is suppressed by more than 12[Formula: see text]dBc. The active whole chip die area is 0.475[Formula: see text]mm2 and the power dissipation from a 1.8-V DC supply is 17.3–20.6[Formula: see text]mW.
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23

Kazeminia, Sarang, Sobhan Sofi Mowloodi, and Khayrollah Hadidi. "A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump." Journal of Circuits, Systems and Computers 24, no. 01 (November 10, 2014): 1550001. http://dx.doi.org/10.1142/s0218126615500012.

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In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm2 active area in a 0.18 μm CMOS technology.
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24

Hati, A., and B. C. Sarkar. "Pump current modulated charge pump PLL." Electronics Letters 35, no. 18 (1999): 1498. http://dx.doi.org/10.1049/el:19990997.

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25

Gwak, Ki-Uk, Sang-Gug Lee, and Seung-Tak Ryu. "Improved Charge Pump with Reduced Reverse Current." JSTS:Journal of Semiconductor Technology and Science 12, no. 3 (September 30, 2012): 353–59. http://dx.doi.org/10.5573/jsts.2012.12.3.353.

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26

Lad Kirankumar, H., S. Rekha, and Tonse Laxminidhi. "Low mismatch high-speed charge pump for high bandwidth phase locked loops." Microelectronics Journal 114 (August 2021): 105156. http://dx.doi.org/10.1016/j.mejo.2021.105156.

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27

Pin-En Su and Sudhakar Pamarti. "Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-$N$ PLLs." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 6 (June 2010): 1221–30. http://dx.doi.org/10.1109/tcsi.2009.2031746.

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28

CHANG, ROBERT C., LUNG-CHIH KUO, and HOU-MING CHEN. "A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 14, no. 05 (October 2005): 997–1006. http://dx.doi.org/10.1142/s0218126605002738.

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A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.
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29

Mao, Xiaojian, Huazhong Yang, and Hui Wang. "An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer." Analog Integrated Circuits and Signal Processing 48, no. 3 (June 12, 2006): 223–29. http://dx.doi.org/10.1007/s10470-006-7832-3.

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30

Jinrong Qian, F. C. Y. Lee, and T. Yamauchi. "Current-source charge-pump power-factor-correction electronic ballast." IEEE Transactions on Power Electronics 13, no. 3 (May 1998): 564–72. http://dx.doi.org/10.1109/63.668121.

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31

Lin, Hesheng, Zhirong Chen, Wing Chun Chan, Wai Kwong Lee, and Min Zhang. "Leakage Current Improvement for a Voltage Doubler Charge Pump." Journal of Low Power Electronics 12, no. 3 (September 1, 2016): 227–33. http://dx.doi.org/10.1166/jolpe.2016.1442.

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32

Kamal, N., S. F. Al‐Sarawi, and D. Abbott. "Reference spur suppression technique using ratioed current charge pump." Electronics Letters 49, no. 12 (June 2013): 746–47. http://dx.doi.org/10.1049/el.2013.1010.

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33

Jeong, Chan‐Hui, Kyu‐Young Kim, Chan‐Keun Kwon, Hoonki Kim, and Soo‐Won Kim. "Digital calibration technique using a signed counter for charge pump mismatch in phase‐locked loops." IET Circuits, Devices & Systems 7, no. 6 (November 2013): 313–18. http://dx.doi.org/10.1049/iet-cds.2013.0011.

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34

Li, Jiayang. "Applications of Wireless Communication in a New Dual Branch CTS Charge Pump Based on Employing Clock Matched Technology." Wireless Communications and Mobile Computing 2021 (August 14, 2021): 1–9. http://dx.doi.org/10.1155/2021/4014795.

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With the increase in communication requirements, new communication technologies and implementation methods have developed rapidly. The rise of emerging markets such as the Internet of Things, smart homes, smart cities, and wearables has promoted the development of wireless communication integrated circuits in the direction of monolithic, low energy consumption, and high energy efficiency. This paper proposes a new dual branch charge pump based on CTS charge pump with enhanced current drive capability and undesired charge transfer completely eliminated. Clock matched technology is proposed to completely eliminate undesired charge transfer caused by delay turn on and off of the auxiliary transistors in the traditional CTS charge pump. The current drive capability is enhanced by employing NMOS transistors with 2Vdd gate drive voltage, while traditional dual branch CTS charge pumps are based on PMOS with 1Vdd gate drive voltage. The output voltage ripple is also reduced resulting from a dual branch structure. Simulation results of output voltage gain and power efficiency for the proposed charge pump and other traditional charge pumps are provided. Comparisons are made to show the improvement of the proposed charge pump compared with other traditional charge pumps.
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35

Ouremchi, Mounir, Karim El Khadiri, Ahmed Tahiri, and Hassan Qjidaa. "Design of a Novel Current Mode Charge Pump for Very-Low-Voltage Applications in 130 nm SOI-BCD Technology." International Journal of Circuits, Systems and Signal Processing 15 (May 18, 2021): 461–69. http://dx.doi.org/10.46300/9106.2021.15.50.

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A novel charge pump with current mode control suitable to work under a very-low-voltage supply is proposed in this paper. The proposed charge pump consists of two sections. The first section is a power switches stage which consists of seven cascaded DEPMOS power switches. The second section is a low voltage stage which consists of a Low Voltage Level Shifter, Current Mode control, Follower Amplifier, Error Amplifier, Soft Start Comparator, and Skip mode & Over Voltage Comparator. The charge pump has been designed, simulated, and layout in Cadence using TSMC 130 nm SOI technology with LDMOS transistors, which have very low on-resistance. The input range of the charge pump is 2.7– 4.4 V, and it can supply up to 100 mA load current. The maximum efficiency is 90%, and the chip area is only 0.597 mm².
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36

Lin, Chih-Lung, Fu-Chieh Chang, Po-Chun Lai, Po-Syun Chen, and Wen-Yen Chang. "A Charge-Pump-Based Current Feedback Method for AMOLED Displays." Journal of Display Technology 9, no. 10 (October 2013): 783–86. http://dx.doi.org/10.1109/jdt.2013.2279885.

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37

Xianrui, Li, Lai Xinquan, Li Yushan, and Ye Qiang. "Research and design of a novel current mode charge pump." Journal of Semiconductors 30, no. 10 (October 2009): 105012. http://dx.doi.org/10.1088/1674-4926/30/10/105012.

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38

Park, Sung Sik, Ju Sang Lee, and Sang Dae Yu. "Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4120. http://dx.doi.org/10.11591/ijece.v8i6.pp4120-4132.

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In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.
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39

Yao, Fang Fang, Xiao Jing Zhang, Zhi Qiang Gao, and Xiao Wei Liu. "Design of Charge Pump for Inertial Sensor Drive Circuit." Key Engineering Materials 609-610 (April 2014): 942–51. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.942.

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A transistor-level circuit design of charge pump is introduced to drive the inertial device. The design is made of several big modules, including main charge pump module, band gap reference module, comparator module, oscillating module, control module, temperature protection module. A three-stage charge pump is applied to achieve 5 V to 18 V DC/DC conversion, and each stage uses the cross coupled charge pump circuit, taking body effect, threshold voltage drop and efficiency into account. Considering efficiency and power consumption, the band gap reference module adopts a self-biased op amp. To make the comparator transient response fast, the op amp cascades two inverters. The temperature protection module sets a maximum temperature to protect the charge pump. The control module is composed of a data selector, a two-phase non-overlap clock circuit and a frequency divider to optimize clock signal. Then simulations are given and the charge pump is analyzed, finally the efficiency of charge pump is calculated. Designed in CSMC 0.5um process, the charge pump has an efficiency of 87.63 percent, a 19.85V output voltage, a 100 mA output current, and 6.05mV ripple.
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40

Yoshimura, Tsutomu, Shuhei Iwade, Hiroshi Makino, and Yoshio Matsuda. "Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 4 (April 2013): 896–907. http://dx.doi.org/10.1109/tcsi.2012.2215393.

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41

Gudkov, S. I., A. V. Solnyshkin, D. A. Kiselev, and A. N. Belov. "Electrical conductivity of lithium tantalate thin film." Cerâmica 66, no. 379 (September 2020): 291–96. http://dx.doi.org/10.1590/0366-69132020663792885.

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Abstract The electrical conductivity of lithium tantalate thin film on the silicon substrate was studied. The film structure was prepared by RF magnetron sputtering. In general, the current-voltage characteristics were asymmetric and similar to that of a diode. The current-voltage characteristics had several sections associated with various transport mechanisms of current carriers. The main conductivity mechanism was related to the space-charge-limited current. The current-voltage characteristics showed that there was a mismatch between the forward and backward runs. One of the reasons for such behavior is a space charge accumulation due to charge carriers which were injected from the electrode and did not relax.
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42

Jinrong Qian, F. C. Lee, and T. Yamauchi. "New continuous-input current charge pump power-factor-correction electronic ballast." IEEE Transactions on Industry Applications 35, no. 2 (1999): 433–41. http://dx.doi.org/10.1109/28.753639.

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43

Lin, Hesheng, Wing Chun Chan, Wai Kwong Lee, Zhirong Chen, Mansun Chan, and Min Zhang. "High-Current Drivability Fibonacci Charge Pump With Connect–Point–Shift Enhancement." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 7 (July 2017): 2164–73. http://dx.doi.org/10.1109/tvlsi.2017.2676822.

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44

Lin, Hesheng, Hongtao Cao, Zhirong Chen, Wing Chun Chan, Wai Kwong Lee, and Min Zhang. "Leakage current elimination for Dickson charge pump with a linear regulator." Microelectronics Journal 64 (June 2017): 29–34. http://dx.doi.org/10.1016/j.mejo.2017.03.010.

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45

St. Pierre, R. "Low-power BiCMOS op-amp with integrated current-mode charge pump." IEEE Journal of Solid-State Circuits 35, no. 7 (July 2000): 1046–50. http://dx.doi.org/10.1109/4.848215.

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46

Tao, Zhang, Zou Xuecheng, Zhao Guangzhou, and Shen Xubang. "Design of a CMOS adaptive charge pump with dynamic current matching." Wuhan University Journal of Natural Sciences 11, no. 2 (February 2006): 405–8. http://dx.doi.org/10.1007/bf02832132.

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47

Choi, Y. S., and D. H. Han. "Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 10 (October 2006): 1022–25. http://dx.doi.org/10.1109/tcsii.2006.882122.

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48

Chi-Hao Wu and Chern-Lin Chen. "High-Efficiency Current-Regulated Charge Pump for a White LED Driver." IEEE Transactions on Circuits and Systems II: Express Briefs 56, no. 10 (October 2009): 763–67. http://dx.doi.org/10.1109/tcsii.2009.2027955.

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49

Shen, Junhua, and Peter R. Kinget. "Current-Charge-Pump Residue Amplification for Ultra-Low-Power Pipelined ADCs." IEEE Transactions on Circuits and Systems II: Express Briefs 58, no. 7 (July 2011): 412–16. http://dx.doi.org/10.1109/tcsii.2011.2158259.

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50

Lee, Jae-Shin, Min-Sun Keel, Shin-Il Lim, and Suki Kim. "Charge pump with perfect current matching characteristics in phase-locked loops." Electronics Letters 36, no. 23 (2000): 1907. http://dx.doi.org/10.1049/el:20001358.

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