Dissertations / Theses on the topic 'Charge pump current mismatch'
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Chan, Chit Sang. "Bi-directional integrated charge pump with switching low dropout regulator /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20CHANC.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.Includes bibliographical references (leaves 62-64). Also available in electronic version. Access restricted to campus users.
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Lopes, Bruno Miguel. "Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system." Master's thesis, Faculdade de Ciências e Tecnologia, 2010. http://hdl.handle.net/10362/4101.
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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e ComputadoresThe objective of this thesis is to study and design a digitally programmable delay locked loop for a UWB radar sensor in 0.13 m CMOS technology.. Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. In certain cases it is necessary to have rising (or falling) edges at precise time instants, different from the ones in the main clock. To create those new timing edges at the appropriate time it is necessary to use delay circuits or delay lines. In the case of the radar system its necessary to generate a clock signal with a variable delay. This delay is relative to the transmit clock signal and is used to determine the target distance. Traditionally, delay lines are realized using a cascade of delay elements and are typically inserted into a delay-locked-loop (DLL) to guaranty that the delay is not affected by process and temperature variations. A DLL works in a similar way to a Phase Locked Loop (PLL). In order to facilitate the operation of the radar system, it is important that the delay value should be digitally programmable. To achieve a digitally programmable delay with a large linearity (independent from matching errors), the architecture of the system is constituted by a digital modulator that controls a 1-bit digital to time converter, whose output will be filtered by the DLL, thus producing the delayed clock signal. The electronic sub-blocks necessary to build this circuit are describe in detail as the proposed architectures. These circuits are implemented using differential clock signals in order to reduce the noise level in the radar system. Design and simulation results of the digitally programmable DLL shows a high output jitter noise for large delays. In order to improve this results a new architecture is proposed. Conventional DLL’s have a predefined charge pump current. The new architecture will make the charge pump current variable. Simulations results will show a improved jitter noise and delay error.
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Chang, Tai-Shun. "Charge Pump Mismatch Current Calibration Techniques for Phase-Locked Loop." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2412200713100200.
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Kamal, Noorfazila. "Reference spurs in an integer-N phase-locked loop : analysis, modelling and design." Thesis, 2013. http://hdl.handle.net/2440/80592.
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The Phase-Locked Loop (PLL) is commonly used for frequency synthesis in RF transceivers. It can be implemented in two architectures, namely, fractional-N and integer- N. In this thesis, the integer-N architecture is chosen due to its suitability for frequency planning. Here, a PLL with a low noise output is important to ensure signal purity. There are two dominant noise sources in a PLL, namely, phase noise and periodic noise. In the integer-N PLL, periodic noise is also referred to as a reference spur, where the noise gives rise to multiple reference frequency offsets at the PLL output. Of these two noise sources, this thesis is focused on the analysis and suppression of reference spurs. It is because less work has been carried in the literature regarding spurs, and phase noise is better studied. The main factors underlying reference spurs are discussed. These factors are mainly from the charge pump and phase/frequency detector (PFD) circuit non-idealities, namely, PFD delay, charge pump current leakage, charge pump current mismatch, and rise and fall times characteristic of the charge pump current. Reference spur magnitude can be predicted via a transient analysis. The simulation is time consuming, as the reference spur magnitude can only be captured after the PLL in its locked state. Therefore, the simulation period has to be set long enough to ensure enough data can be obtained to read that state. In this thesis, a reference spur mathematical analysis is presented to accurately estimate the reference spur magnitude. In the analysis, all the circuit non-idealities that contribute to the reference spur are considered. Circuit parameters required in the mathematical analysis can be obtained from transistor level simulation for each circuit. As the simulation for each circuit can be carried out separately, a large amount of simulation time can be saved. The proposed mathematical analysis also can be used to determine the major contributing factor to the problem of reference spurs. The reference spur also can be estimated via behavioural modelling simulation. Behavioural modelling of the PLL using Simulink is presented in this thesis. Each PLL component is modelled separately, and circuit non-idealities contributing to the reference spur are included in the behavioural model. In addition to reference spur estimation, the PLL behavioural model also can be used to visualise the dynamic behaviour of the system. Results from the spur analysis show that a slight mismatch current in the charge pump helps to improve the reference spur performance. This thesis presents an analysis to determine an optimum charge pump current ratio for reference spur suppression, which is caused by the charge pump current mismatch and the switching delay. Further, a ratioed current charge pump circuit is proposed to replace the conventional charge pump circuit for a reference spur performance improvement. This spur suppression technique is implemented using a 180 nm SiGe BiCMOS technology for performance evaluation.Thesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 2013
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Ke, Yu-Zhou, and 柯昱州. "High Performance Charge Pump Circuit Design with Minimized Leakage Current." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/37546640753519650730.
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碩士國立交通大學
電機學院IC設計產業專班
96
Charge pump has developed for thirty years from 1976 till now. However, different kinds of charge pump have their advantages and disadvantages. The biggest problem among these charge pump circuits is that most of these charge pumps would cause voltage gain and efficiency lower than the ideal values due to the undesired loss. In this thesis, the disadvantage that charge pump circuits are alleviated and a new cross-coupled charge pump circuit is presented to enhance the performance of energy loss. Till now, most charge pumps all have the same problems such as, threshold voltage drop, body effect, gate-oxide reliability, reversion loss, conduction loss and redistribution loss. These problems may cause the layer of gate-oxide broken and the system failure. Besides, the breakdown not only makes damage to MOS transistors but also decreases voltage gain and, thereby diminishing conversion efficiency of charge pump. Therefore, the most important things that the designers need to do are to minimize the effects of these disadvantages. The cross coupled charge pump mentioned in this thesis will improve or alleviate the above problems and thus increase the efficiency of charge pump circuits. The proposed technique can effectively avoid the energy loss in the operation of charge pump circuits. The test chip was designed by TSMC 0.35um technology. Simulation results can demonstrate the correctness and performance of the proposed techniques.
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Tingfang, Zheng, and 鄭廷芳. "Design Of Current Mode Charge Pump For White LED Circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/77194298825018286545.
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碩士亞洲大學
光電與通訊學系碩士班
100
Power efficiency is an important issue for portable electronic devices. The major part of power consumption of portable device is LED backlight module. Therefore, deign of high efficiency backlight module is required to extend the operation time. Nowadays white light-emitting diodes (WLEDs) have replaced cold cathode fluorescent lamps (CCFL) as backlight modules in portable electronics in terms of power efficiency and size. This paper presents a current mode DC-DC converter for WLED and OLED that are all popular light source for portable devices.
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Yang, Yu-Chun, and 楊毓群. "Charge Pump with Zero Reverse Current , Constant Switch On-Resistance and Frequency Control." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/70827749537230448442.
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Wu, Geng-yi, and 吳耿毅. "A Self-Regulated Charge Pump with High Drive Current and Small Output Ripple Voltage." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/71309610072403955378.
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碩士國立雲林科技大學
電子與資訊工程研究所
95
A self-regulated charge pump circuit is proposed. The charge pump exploits an automatic pumping control scheme to provide small output ripple voltage. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an improved automatic pumping frequency control scheme. We utilized a Range-programmable Voltage-controlled Oscillator which has four different frequency band outputs depended on load current value. The output frequency of the VCO varies from 400KHz to 10MHz. The improved automatic pumping frequency control scheme generates high pumping frequency when the system provides the great load current, and also reduce the output ripple voltage. The improved charge pump is designed in a TSMC 0.18 CMOS process. The fabricated circuit occupies an area of 734.54um*794.805um, operating at 1.8V power supply with a flying capacitor of 330nF. For the variable load resistor and the load capacitor of 2μF. The circuit offers load current from 1mA to 30mA. The improved charge pump delivers 2.05-V output voltage, and the output ripple voltage is less than 1mV, and the power efficiency is 51.5%, while providing 30mA of load current.
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Lu, Wan-Ying, and 呂婉熒. "Low Supply Noise High Output Current Voltage Charge Pump for Embedded Non-Volatile Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/58504327885945151254.
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碩士國立清華大學
產業研發碩士積體電路設計專班
98
Charge pump circuits (CPCs) are commonly used for pumping charge upward to produce higher than the regular supply voltage or downward to negative voltage on a chip, and have been widely used in non-volatile memories (NVMs) for many years since the NVMs require a high voltage to program floating-gate devices. Power integrity has become more important as scaling down the supply voltage in SOC designs, the largest power noise and ground bounce occur in high voltage generator as CPC for embedded NVMs such as Flash memory, OTP and EEPROM since periodical switching clock s cause serious power peak current and suffer inductive effect on package bond wire. Suppressing power peak current (PPC) is the most key point for a low noise design. This study proposes new 4-phase with distributed local control scheme that each charge pump module operates not at the same time, therefore the peak current would be degraded and switching power noise due to dI/dt is greatly reduced The Low Noise Charge Pump (LNCP) is fabricated in 90nm CMOS technology. The measurement results demonstrate that the power noise can be reduced more than 60% from 10MHz to 16.7MHz and better power efficiency about 7% comparing to conventional 4-phase CP with less than 3% area penalty. Moreover, LNCP can be achieved to high speed with new 4-phase clock control in the future.
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Hsu, Te-Hsien, and 許德賢. "A Low Spurious Tones of 5-GHz CMOS Frequency Synthesizer with New Current-Match Charge Pump." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/57937910858614456477.
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碩士國立交通大學
電機資訊學院碩士在職專班
93
The thesis use TSMC 0.18um CMOS process to implement a 5-GHz frequency synthesizer that has perfect characteristic of low spurious tones. In this synthesizer which includes two perfect current-match of charge pump and they reduce spurious tones validly. The spurious sidebands at the center of adjacent channels are less than -69.52dBc. The frequency synthesizer collocate a small layout area of divide-by-2 divider, which structure of layout area and cost are smaller than other structure which like inductances loading type divider. The quadrature phase output of synthesizer can support IEEE 802.11a transceiver. The chip working frequency reach 5.62 GHz, and the loop settling time was small than 13.5uS. The frequency phase noise is restrained at -107dBc@1MHz. The chip total power is 18.8mW based on 1.4V power supply for program counter and swallow counter and 1.8V power supply for other block.
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Weng, Hsiu-Hua, and 翁秀樺. "Study on the Improvement of Current-Matching Property of the Charge Pump for Phase-Locked Loops." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/09419936034183700236.
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碩士逢甲大學
電子工程所
98
The goal of this research is to use a standard CMOS process to implement a modified charge pump (CP) with better current-matching property for phase-locked loop (PLL) system. This technique uses differential amplifiers to improve current mismatch for charge pump circuit. This thesis is divided into five parts. Chapter 1 is introducing the background information and applications of phase-locked loops and motivation. The second part is chapter 2, in which the operation mechanisms and related analysis of the phase-locked loops (PLLs) are presented. The current-matching property of charge pump is the most important performance-assessment. Both the dead zone of phase frequency detector (PFD) and the glitch problems make clock- synchronization mistakes in phase-locked loop system and also affect current-matching in charge pump. In addition, the low-pass filter converts current from charge pump output to a proportioned control-voltage for the voltage-controlled oscillator (VCO). Thus, the preceding part of chapter 3 will discuss phase frequency detector (PFD), glitch, and low-pass filter (LPF). And then we review references and introduce several charge pump circuits. The chapter 4, first of all is to analyze and to design the charge pumps discussed in chapter 3 and then we propose a method to modify the current mismatch. After all, the verification of this circuit by simulation, its physical chip layout and the results of measurement are presented in chapter 5. Finally, the conclusion is given in chapter 6. The chip of proposed circuit is implemented with the TSMC 0.18-μm CMOS process and a 2.4GHz frequency synthesizer is used to evaluate the proposed technique. The experimental results show that techniques we used reduce the static phase error and charge sharing significantly. The effect of mismatch is reduced to 1% that is about 8-times better than that of previous works within a range from 0.4V to 1.4 V even if without using negative feedback. Index terms: phase-locked loop (PLL)、charge pump(CP)、 Current mismatch、frequency synthesizer
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Yen, Tzu-Yang, and 顏子揚. "Hysteresis-Controlled DC-DC Buck/Boost Current Converter and The Low-voltage Low-power Voltage Regulated Charge Pump." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96sxzg.
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碩士國立臺北科技大學
電腦與通訊研究所
95
In this thesis, we design switching mode DC-DC current converter based on hysteresis-controlled technique. This structure is a novel and original circuit. There is not relative circuit presented in the paper, and this technology get better driving to apply to current mode loading like Motor or OLED etc. DC-DC current converter can decrease the noise due to stray inductance effect which is generated by conducting wire. As a result, we use current converter to current mode loading will reduce the interference of noise, and increase stability and accuracy of power supply. In the proposed DC-DC current converter is consist of power switch transistors, a comparator, a hysteresis circuit, a non-overlapping circuit and a driver circuit. The concept of hysreresis circuit is used the voltage of capacitor to be a control signal, and compare with up and down limited-voltage that be generated by hysteresis circuit, and control of power switch transistors to get output current that we expected. The control driving circuit provides non-overlapping signals that are used to switch power switch transistors in order to avoid the short-current between power switch transistors. Hysteresis-controlled buck/boost current converter are implemented with TSMC 0.35μm 2P4M CMOS processes. The experimental results show that the buck/ buck-boost converter operation range of input current is 100mA~800mA, and the output current is 100mA~800mA. The current converter maximum efficiency could reach to 88%. The other chip, we design novel boost circuit, and one characteristic is through closed-loop design to get expected output voltage. The other characteristic can detect the state of output current, when there is no output current, it will shut down control circuit to saving power consumption. In this work, because each pumping capacitor of charge pump is designed to 4pF that can design on-chip, so that can save circuit size. These characteristics are suitable to apply to portable electronic products. It consists of a charge pump, a load sensing circuit, a comparator, a non-overlapped circuit and a driver circuit. The charge transfer switches in this charge pump can be completely turn on and turn off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices do not exceed the normal operating power supply voltage. A load sensing circuit can detect the state of output current, and shut down control circuit to saving power consumption. In the proposed regulated charge pump is implemented with TSMC 0.35μm 2P4M CMOS processes. Under 1.5V power supply, the results of simulation show that operation range of output voltage is 1.5V~5.5V. The power consumption of circuit under no output current is 16uW .
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Chen, Jyun Ting, and 陳俊廷. "Using sequential switching asymmetric stimulating waveforms to implement a current-mode neuron stimulator with residual charge mismatch percentage less than 0.1%." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/50544431688217336764.
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碩士國立清華大學
電機工程學系
103
Bio-medical field has drawn more and more attention in recent years. Functional electrical stimulation (FES) has been researched and applied to treat neuron disease, repair the physiological function of patients suffering from neuron damage. The stimulator is very close to neuron in all implantable devices, so safety is the critical point. Usually, residual charge on electrode/neuron interface after once stimulation is estimated as safety standard. We wish the residual charge can be reduced as low as possible. Because lower residual charge means the electrode electrolysis probability is smaller. Besides, some researches have proven that the stimulator with asymmetric stimulation output waveform can reduce neuron stimulation threshold charge effectively. However, stimulator with asymmetric output waveform is hard to reduce residual charge because of its difficult calibration through circuit. According to above design hard point, we use an improved current source control signal called sequential switching signal (S.S signal) to achieve lower residual charge when transferring asymmetric waveform. The stimulator has been fabricated using TSMC 0.18μm technology. Simulation result shows that stimulation current is up to 400μA and its residual charge mismatch percentage is less than 0.1%.
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Lin, Yuming, and 林育民. "Study of Charge Pump Circuits for UHF RFID Tag and 10 bits 250MS/s Current-Steering Digital-to-Analog Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/94670037659013069801.
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碩士國立暨南國際大學
電機工程學系
99
In this thesis achieve circuit is applied to UHF 915MHz RFID Tags , transfering small radio waves into stable DC voltage for the use of next stage circuit. Because RF signal losses quickly in air, much smaller than -15dBm, the issue of using a charge pump to supply sufficient and stable DC voltage is important. And this technology can be further applied in wireless charging technology, not only in wireless sensor system but also in various technology products such as mobile phones, MP3, wireless communications, and camera…In this thesis, I implement the charge pump circuits by TSMC 18µm 1P6M process. In order to achieve a stable supply meet the specifications of the DC voltage, the circuit layout includes a matching network, voltage multiplier, voltage limiting circuit, reference voltage circuit, and Regulator. The simulation and layout of the thesis is to achieve a 250MHz 10bits current steering DAC, and is expected to complete tape out by 35um 2p4m process provided by Taiwan Semiconductor Manufacturing Company provided . The circuit layout design has two parts - digital and analog. To reduce the glitch and differential nonlinearity (DNL), integral nonlinearity (INL) and to maintain the transfer curve monotonic the circuit is designed to be segmented structure, in which the highest 6bits MSB is the thermometer decoder and the lowest 4bits LSB is weighted binary code. The circuit is composed of 4 main parts: (1) digital circuit (2) clock drive, buffer (3) Deglitch Latch (4) current units. And current steering DAC output current do not need to output buffer can Directly drive the load resistance, so better than other architecture has speed advantages.
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Huang, Shih-Yun, and 黃詩芸. "The Design of 180-nm CMOS 256-Pixel Sensing and Biphasic Current Stimulation Chips with Bidirectional-Sharing Electrodes and Charge Pump for Subretinal Prosthesis." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/eq66hv.
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Liao, Jung-Hsing, and 廖容興. "THE DESIGN OF 180-NM CMOS 480-PIXEL SENSING AND BIPHASIC CURRENT STIMULATION CHIPS WITH FOUR DIRECTIONAL SHARING ELECTRODES AND CHARGE PUMP FOR SUBRETINAL PROSTHESIS." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/9u4376.
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碩士國立交通大學
電子研究所
106
A photovoltaic-cell-powered CMOS 480-pixel implantable chip is proposed for subretinal prostheses. In the proposed chip, the divisional power supply scheme (DPSS) and the active pixel sensor (APS) are adopted to improve the efficiency of output stimulation currents and the image sensitivity. The proposed chip consists of totally 480 photodiode array with 32 DPSS divisions, control signal generator circuits, and photovoltaic cells. It is designed and fabricated in 180-nm CMOS image sensor (CIS) technology. The chip size is 3.1mm x 3.1mm. At first, the chip have not any output function. After FIB, this chip measured frequency of 32-phase control signals is 30 Hz under signal light intensity of 505.4 lux and background IR intensity of 94 mW/cm2. The measured output stimulation current is 9.0 μA under 10-kΩ load. Under the equivalent electrode impedance load, the measured frequency of 32-phase control signals is 38 Hz. The measured peak output stimulation current is 9.0 μA and the amount of injected charges per pixel is 9.8 nC. The measurement results have verified the correct function of the proposed subretinal implant chip after FIB.
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"Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications." Doctoral diss., 2018. http://hdl.handle.net/2286/R.I.50579.
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abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator.
Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2018