Relevant bibliographies by topics / Charge pump current mismatch

Academic literature on the topic 'Charge pump current mismatch'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Charge pump current mismatch"

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Hwang, M. S., J. Kim, and D. K. Jeong. "Reduction of pump current mismatch in charge-pump PLL." Electronics Letters 45, no. 3 (2009): 135. http://dx.doi.org/10.1049/el:20092727.

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Liu, Lianxi, Shaopu Gao, Junchao Mu, and Zhangming Zhu. "A Low Power and Low Current-Mismatch Charge Pump with Dynamic Current Compensation." Journal of Circuits, Systems and Computers 28, no. 12 (November 2019): 1920007. http://dx.doi.org/10.1142/s021812661920007x.

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A novel low power charge pump (CP) that minimizes the mismatch between the charging and the discharging currents is proposed in this paper. The switching circuit with dynamic current compensation is used to reduce the power consumption of the proposed CP. In addition, precise current replication which makes use of the resistors and the low offset operational amplifiers (OTA) can enable a reduction in current mismatch caused by process mismatch. Meanwhile, the high output impedance can reduce the current mismatch caused by the channel length modulation effect. Based on the 0.18[Formula: see text][Formula: see text]m deep-Nwell CMOS process, the proposed CP can reduce the overall power consumption by 56% compared with the CP without current compensation, reduce the current mismatch caused by process mismatch to less than 0.9% and reduce the current mismatch caused by the channel length modulation effect to less than 0.01% over the output voltage ranging from 0.3 to 1.5[Formula: see text]V with 1.8[Formula: see text]V supply.
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Joram, N., R. Wolf, and F. Ellinger. "High swing PLL charge pump with current mismatch reduction." Electronics Letters 50, no. 9 (April 2014): 661–63. http://dx.doi.org/10.1049/el.2014.0804.

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D S, Rajeshwari, P. V Rao, and Ramesh Karmungi. "10Ghz Charge Pump PLL for Low Jitter Applica-tions." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 348. http://dx.doi.org/10.14419/ijet.v7i2.12.11349.

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This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files
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Zhang, G. "Linearised charge pump independent of current mismatch through timing rearrangement." Electronics Letters 46, no. 1 (2010): 33. http://dx.doi.org/10.1049/el.2010.2555.

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Guo, Rui, Zhenghao Lu, Shaogang Hu, Qi Yu, Limei Rong, and Yang Liu. "Design and Verification of a Charge Pump in Local Oscillator for 5G Applications." Electronics 10, no. 9 (April 23, 2021): 1009. http://dx.doi.org/10.3390/electronics10091009.

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A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design.
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Byun, Sangjin, and Jae Hoon Shim. "Charge Pump circuit with wide range digital leakage current mismatch compensator." IEICE Electronics Express 7, no. 23 (2010): 1709–13. http://dx.doi.org/10.1587/elex.7.1709.

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Zulkalnain, Mohd Khairi, and Yan Chiew Wong. "Current mismatch reduction in charge pumps using regulated current stealing-injecting transistors for PLLs." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 1 (October 1, 2021): 61. http://dx.doi.org/10.11591/ijeecs.v24.i1.pp61-69.

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A charge pump for phase locked loops (PLL) with a novel current mismatch compensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The proposed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.
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Yu, Cao, Min Su Kim, Hyung Chul Kim, and Youn Goo Yang. "A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application." Advanced Materials Research 457-458 (January 2012): 1178–82. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1178.

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A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.
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Zhai, Yannan, Ling Gao, Jingquan Li, and Qangli Qiu. "A Design of fast-setting on-chip Charge Pump Circuit." Journal of Physics: Conference Series 2195, no. 1 (February 1, 2022): 012034. http://dx.doi.org/10.1088/1742-6596/2195/1/012034.

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Abstract A circuit of fast-setting charge pump on-chip is designed based on the Dickson circuit. The charge pump circuit, which is improved, increases the initial node voltage. With the consideration of the current mismatch, the accurate clock of the duty circle below 50% is proposed. The HSPICE simulation result indicates that the setting time from 0V to 20V only needs 51.650μs for the charge pump, and it is faster than the traditional Dickson charge pump 26.03μs. In summary, the settling time of the output voltage of the charge pump is prominently decreased and the performance of the charge pump is obviously improved.
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Dissertations / Theses on the topic "Charge pump current mismatch"

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Chan, Chit Sang. "Bi-directional integrated charge pump with switching low dropout regulator /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20CHANC.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.
Includes bibliographical references (leaves 62-64). Also available in electronic version. Access restricted to campus users.
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Lopes, Bruno Miguel. "Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system." Master's thesis, Faculdade de Ciências e Tecnologia, 2010. http://hdl.handle.net/10362/4101.

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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores
The objective of this thesis is to study and design a digitally programmable delay locked loop for a UWB radar sensor in 0.13 m CMOS technology.. Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. In certain cases it is necessary to have rising (or falling) edges at precise time instants, different from the ones in the main clock. To create those new timing edges at the appropriate time it is necessary to use delay circuits or delay lines. In the case of the radar system its necessary to generate a clock signal with a variable delay. This delay is relative to the transmit clock signal and is used to determine the target distance. Traditionally, delay lines are realized using a cascade of delay elements and are typically inserted into a delay-locked-loop (DLL) to guaranty that the delay is not affected by process and temperature variations. A DLL works in a similar way to a Phase Locked Loop (PLL). In order to facilitate the operation of the radar system, it is important that the delay value should be digitally programmable. To achieve a digitally programmable delay with a large linearity (independent from matching errors), the architecture of the system is constituted by a digital modulator that controls a 1-bit digital to time converter, whose output will be filtered by the DLL, thus producing the delayed clock signal. The electronic sub-blocks necessary to build this circuit are describe in detail as the proposed architectures. These circuits are implemented using differential clock signals in order to reduce the noise level in the radar system. Design and simulation results of the digitally programmable DLL shows a high output jitter noise for large delays. In order to improve this results a new architecture is proposed. Conventional DLL’s have a predefined charge pump current. The new architecture will make the charge pump current variable. Simulations results will show a improved jitter noise and delay error.
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Chang, Tai-Shun. "Charge Pump Mismatch Current Calibration Techniques for Phase-Locked Loop." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2412200713100200.

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Kamal, Noorfazila. "Reference spurs in an integer-N phase-locked loop : analysis, modelling and design." Thesis, 2013. http://hdl.handle.net/2440/80592.

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The Phase-Locked Loop (PLL) is commonly used for frequency synthesis in RF transceivers. It can be implemented in two architectures, namely, fractional-N and integer- N. In this thesis, the integer-N architecture is chosen due to its suitability for frequency planning. Here, a PLL with a low noise output is important to ensure signal purity. There are two dominant noise sources in a PLL, namely, phase noise and periodic noise. In the integer-N PLL, periodic noise is also referred to as a reference spur, where the noise gives rise to multiple reference frequency offsets at the PLL output. Of these two noise sources, this thesis is focused on the analysis and suppression of reference spurs. It is because less work has been carried in the literature regarding spurs, and phase noise is better studied. The main factors underlying reference spurs are discussed. These factors are mainly from the charge pump and phase/frequency detector (PFD) circuit non-idealities, namely, PFD delay, charge pump current leakage, charge pump current mismatch, and rise and fall times characteristic of the charge pump current. Reference spur magnitude can be predicted via a transient analysis. The simulation is time consuming, as the reference spur magnitude can only be captured after the PLL in its locked state. Therefore, the simulation period has to be set long enough to ensure enough data can be obtained to read that state. In this thesis, a reference spur mathematical analysis is presented to accurately estimate the reference spur magnitude. In the analysis, all the circuit non-idealities that contribute to the reference spur are considered. Circuit parameters required in the mathematical analysis can be obtained from transistor level simulation for each circuit. As the simulation for each circuit can be carried out separately, a large amount of simulation time can be saved. The proposed mathematical analysis also can be used to determine the major contributing factor to the problem of reference spurs. The reference spur also can be estimated via behavioural modelling simulation. Behavioural modelling of the PLL using Simulink is presented in this thesis. Each PLL component is modelled separately, and circuit non-idealities contributing to the reference spur are included in the behavioural model. In addition to reference spur estimation, the PLL behavioural model also can be used to visualise the dynamic behaviour of the system. Results from the spur analysis show that a slight mismatch current in the charge pump helps to improve the reference spur performance. This thesis presents an analysis to determine an optimum charge pump current ratio for reference spur suppression, which is caused by the charge pump current mismatch and the switching delay. Further, a ratioed current charge pump circuit is proposed to replace the conventional charge pump circuit for a reference spur performance improvement. This spur suppression technique is implemented using a 180 nm SiGe BiCMOS technology for performance evaluation.
Thesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 2013
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Ke, Yu-Zhou, and 柯昱州. "High Performance Charge Pump Circuit Design with Minimized Leakage Current." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/37546640753519650730.

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碩士
國立交通大學
電機學院IC設計產業專班
96
Charge pump has developed for thirty years from 1976 till now. However, different kinds of charge pump have their advantages and disadvantages. The biggest problem among these charge pump circuits is that most of these charge pumps would cause voltage gain and efficiency lower than the ideal values due to the undesired loss. In this thesis, the disadvantage that charge pump circuits are alleviated and a new cross-coupled charge pump circuit is presented to enhance the performance of energy loss. Till now, most charge pumps all have the same problems such as, threshold voltage drop, body effect, gate-oxide reliability, reversion loss, conduction loss and redistribution loss. These problems may cause the layer of gate-oxide broken and the system failure. Besides, the breakdown not only makes damage to MOS transistors but also decreases voltage gain and, thereby diminishing conversion efficiency of charge pump. Therefore, the most important things that the designers need to do are to minimize the effects of these disadvantages. The cross coupled charge pump mentioned in this thesis will improve or alleviate the above problems and thus increase the efficiency of charge pump circuits. The proposed technique can effectively avoid the energy loss in the operation of charge pump circuits. The test chip was designed by TSMC 0.35um technology. Simulation results can demonstrate the correctness and performance of the proposed techniques.
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Tingfang, Zheng, and 鄭廷芳. "Design Of Current Mode Charge Pump For White LED Circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/77194298825018286545.

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碩士
亞洲大學
光電與通訊學系碩士班
100
Power efficiency is an important issue for portable electronic devices. The major part of power consumption of portable device is LED backlight module. Therefore, deign of high efficiency backlight module is required to extend the operation time. Nowadays white light-emitting diodes (WLEDs) have replaced cold cathode fluorescent lamps (CCFL) as backlight modules in portable electronics in terms of power efficiency and size. This paper presents a current mode DC-DC converter for WLED and OLED that are all popular light source for portable devices.
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Yang, Yu-Chun, and 楊毓群. "Charge Pump with Zero Reverse Current , Constant Switch On-Resistance and Frequency Control." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/70827749537230448442.

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Wu, Geng-yi, and 吳耿毅. "A Self-Regulated Charge Pump with High Drive Current and Small Output Ripple Voltage." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/71309610072403955378.

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碩士
國立雲林科技大學
電子與資訊工程研究所
95
A self-regulated charge pump circuit is proposed. The charge pump exploits an automatic pumping control scheme to provide small output ripple voltage. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an improved automatic pumping frequency control scheme. We utilized a Range-programmable Voltage-controlled Oscillator which has four different frequency band outputs depended on load current value. The output frequency of the VCO varies from 400KHz to 10MHz. The improved automatic pumping frequency control scheme generates high pumping frequency when the system provides the great load current, and also reduce the output ripple voltage. The improved charge pump is designed in a TSMC 0.18 CMOS process. The fabricated circuit occupies an area of 734.54um*794.805um, operating at 1.8V power supply with a flying capacitor of 330nF. For the variable load resistor and the load capacitor of 2μF. The circuit offers load current from 1mA to 30mA. The improved charge pump delivers 2.05-V output voltage, and the output ripple voltage is less than 1mV, and the power efficiency is 51.5%, while providing 30mA of load current.
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Lu, Wan-Ying, and 呂婉熒. "Low Supply Noise High Output Current Voltage Charge Pump for Embedded Non-Volatile Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/58504327885945151254.

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碩士
國立清華大學
產業研發碩士積體電路設計專班
98
Charge pump circuits (CPCs) are commonly used for pumping charge upward to produce higher than the regular supply voltage or downward to negative voltage on a chip, and have been widely used in non-volatile memories (NVMs) for many years since the NVMs require a high voltage to program floating-gate devices. Power integrity has become more important as scaling down the supply voltage in SOC designs, the largest power noise and ground bounce occur in high voltage generator as CPC for embedded NVMs such as Flash memory, OTP and EEPROM since periodical switching clock s cause serious power peak current and suffer inductive effect on package bond wire. Suppressing power peak current (PPC) is the most key point for a low noise design. This study proposes new 4-phase with distributed local control scheme that each charge pump module operates not at the same time, therefore the peak current would be degraded and switching power noise due to dI/dt is greatly reduced The Low Noise Charge Pump (LNCP) is fabricated in 90nm CMOS technology. The measurement results demonstrate that the power noise can be reduced more than 60% from 10MHz to 16.7MHz and better power efficiency about 7% comparing to conventional 4-phase CP with less than 3% area penalty. Moreover, LNCP can be achieved to high speed with new 4-phase clock control in the future.
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Hsu, Te-Hsien, and 許德賢. "A Low Spurious Tones of 5-GHz CMOS Frequency Synthesizer with New Current-Match Charge Pump." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/57937910858614456477.

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碩士
國立交通大學
電機資訊學院碩士在職專班
93
The thesis use TSMC 0.18um CMOS process to implement a 5-GHz frequency synthesizer that has perfect characteristic of low spurious tones. In this synthesizer which includes two perfect current-match of charge pump and they reduce spurious tones validly. The spurious sidebands at the center of adjacent channels are less than -69.52dBc. The frequency synthesizer collocate a small layout area of divide-by-2 divider, which structure of layout area and cost are smaller than other structure which like inductances loading type divider. The quadrature phase output of synthesizer can support IEEE 802.11a transceiver. The chip working frequency reach 5.62 GHz, and the loop settling time was small than 13.5uS. The frequency phase noise is restrained at -107dBc@1MHz. The chip total power is 18.8mW based on 1.4V power supply for program counter and swallow counter and 1.8V power supply for other block.
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Books on the topic "Charge pump current mismatch"

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Charge Pump IC Design. McGraw-Hill Professional Publishing, 2015.

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Book chapters on the topic "Charge pump current mismatch"

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Roy, Subham, Kirankumar H. Lad, S. Rekha, and T. Laxminidhi. "A Low Mismatch Current Steering Charge Pump for High-Speed PLL." In Proceedings of Second International Conference on Computational Electronics for Wireless Communications, 447–56. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_40.

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Huang, Qixiang, Xinnan Lin, and Jin He. "A Low Current Mismatch and Deviation Charge Pump with Symmetrical Complementary Half-Current Circuits." In Recent Advances in Computer Science and Information Engineering, 735–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-25769-8_103.

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Saldanha, Alan, Vijil Gupta, and Vinod Kumar Joshi. "Comparison of Low Current Mismatch CMOS Charge Pumps for Analog PLLs Using 180 nm Technology." In Advances in Intelligent Systems and Computing, 683–92. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3600-3_65.

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Rajeshwari, D. S., P. V. Rao, and V. Rajesh. "Charge Pump with Improved High-Swing Cascode Current Source for Accurate Current Matching in DPLL." In Advances in Intelligent Systems and Computing, 39–47. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2656-7_4.

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Huang, Jhin-Fang, Jia-Lun Yang, and Kuo-Lung Chen. "A 5.8-GHz Frequency Synthesizer with Dynamic Current-Matching Charge Pump Linearization Technique and an Average Varactor Circuit." In Lecture Notes in Electrical Engineering, 1045–53. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01766-2_119.

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"High Performance PLL base on Nonlinear Phase Frequency Detector and Optimized Charge Pump." In Current Trends in Computer Science and Mechanical Automation Vol.1, 492–99. De Gruyter Open Poland, 2017. http://dx.doi.org/10.1515/9783110584974-052.

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Apell, H. J., R. Borlinghaus, and P. Läuger. "Chapter 12 Electrogenic Properties of the Na/K Pump: Voltage Dependence and Kinetics of Charge Translocation." In Current Topics in Membranes and Transport, 229–52. Elsevier, 1989. http://dx.doi.org/10.1016/s0070-2161(08)60016-7.

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Conference papers on the topic "Charge pump current mismatch"

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Fazeel, H. Md Shuaeb, Leneesh Raghavan, Chandrasekaran Srinivasaraman, and Manish Jain. "Reduction of Current Mismatch in PLL Charge Pump." In 2009 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2009. http://dx.doi.org/10.1109/isvlsi.2009.45.

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Chen, Chun-Chieh, and Nan-Ku Lu. "CMOS Charge Pump with Ultra-Low Current Mismatch." In 2022 IEEE 5th International Conference on Knowledge Innovation and Invention (ICKII ). IEEE, 2022. http://dx.doi.org/10.1109/ickii55100.2022.9983569.

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Biswas, Debdut. "Charge Pump with Low Current Mismatch for PLL Applications." In 2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2021. http://dx.doi.org/10.1109/conecct52877.2021.9622662.

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Liang, Shengyu, Youze Xin, Chenglong Liang, Bin Zhang, Yanlong Zhang, Xiaoli Wang, and Li Geng. "A 0.025% DC Current Mismatch Charge Pump for PLL Applications." In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2021. http://dx.doi.org/10.1109/mwscas47672.2021.9531880.

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Shiau, Miin-Shyue, Ching-Hwa Cheng, Heng-Shou Hsu, Hong-Chong Wu, Hsiu-Hua Weng, Jing-Jhong Hou, Ruei-Cheng Sun, Kai-Che Liu, Guang-Bao Lu, and Don-Gey Liu. "Design for low current mismatch in the CMOS charge pump." In 2013 International Soc Design Conference (ISOCC). IEEE, 2013. http://dx.doi.org/10.1109/isocc.2013.6864035.

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Amer, Aya G., Sameh A. Ibrahim, and Hani F. Ragai. "A novel current steering charge pump with low current mismatch and variation." In 2016 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2016. http://dx.doi.org/10.1109/iscas.2016.7538887.

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Kim, Sung-Geun, Jinsoo Rhim, Dae-Hyun Kwon, Min-Hyeong Kim, and Woo-Young Choi. "A low-voltage PLL with a current mismatch compensated charge pump." In 2015 International SoC Design Conference (ISOCC). IEEE, 2015. http://dx.doi.org/10.1109/isocc.2015.7401629.

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Koithyar, Aravinda, and T. K. Ramesh. "Integer-N charge pump phase locked loop with reduced current mismatch." In 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). IEEE, 2017. http://dx.doi.org/10.1109/wispnet.2017.8299840.

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Ji, Shujiang, Yuxiao Zhao, Wenjie Xu, Na Yan, and Hao Min. "A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL." In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. http://dx.doi.org/10.1109/iscas45731.2020.9180830.

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Vaishali and R. K. Sharma. "An Improved Dynamic Range Charge Pump with Reduced Current Mismatch for PLL Applications." In 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS). IEEE, 2018. http://dx.doi.org/10.1109/iccons.2018.8663212.

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