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Dissertations / Theses on the topic 'CARRIER RELIABILITY'

Author: Grafiati

Published: 11 September 2023

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1

Tsarouchas, Ioannis. "Through life reliability of a bulk carrier." Thesis, University of Glasgow, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.368736.

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2

Jiang, Wenjie 1963. "Hot-carrier reliability assessment in CMOS digital integrated circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47514.

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3

Chan, Vei-Han. "Hot-carrier reliability evaluation for CMOS devices and circuits." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36532.

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4

Wang, Lei. "Reliability control of GNSS carrier-phase integer ambiguity resolution." Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/86976/1/Lei_Wang_Thesis.pdf.

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This research investigates how to obtain accurate and reliable positioning results with global navigation satellite systems (GNSS). The work provides a theoretical framework for reliability control in GNSS carrier phase ambiguity resolution, which is the key technique for precise GNSS positioning in centimetre levels. The proposed approach includes identification and exclusion procedures of unreliable solutions and hypothesis tests, allowing the reliability of solutions to be controlled in the aspects of mathematical models, integer estimation and ambiguity acceptance tests. Extensive experime

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5

Le, Huy X. P. "Characterization of hot-carrier reliability in analog sub-circuit design." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41379.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.<br>Includes bibliographical references (leaves 52-54).<br>by Huy X.P. Le.<br>M.Eng.

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6

Kim, SeokWon Abraham 1970. "Hot-carrier reliability of MOSFETs at room and cryogenic temperature." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/28215.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Vita.<br>Includes bibliographical references.<br>Hot-carrier reliability is an increasingly important issue as the geometry scaling of MOSFET continues down to the sub-quarter micron regime. The power-supply voltage does not scale at the same rate as the device dimensions, and thus, the peak lateral E-field in the channel increases. Hot-carriers, generated by this high lateral E-field, gain more kinetic energy and cause damage to the device as the geometry dimension of MOSFETs

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7

Jiang, Liangjun. "HOT CARRIER EFFECT ON LDMOS TRANSISTORS." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3230.

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One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by pr

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8

Le, Huy X. P. "On the methodology of assessing hot-carrier reliability of analog circuits." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/84212.

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9

Das, A. G. Man Mohan. "Effect of wearout processes on the critical timing parameters and reliability of CMOS bistable circuits." Thesis, Durham University, 1997. http://etheses.dur.ac.uk/4701/.

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The objective of the research presented in this thesis was to investigate the effects of wearout processes on the performance and reliability of CMOS bistable circuits. The main wearout process affecting reliability of submicron MOS devices was identified as hot-carrier stress (and the resulting degradation in circuit performance). The effect of hot-carrier degradation on the resolving time leading to metastability of the bistable circuits also have been investigated. Hot-carrier degradation was identified as a major reliability concern for CMOS bistable circuits designed using submicron techn

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10

Koeppel, Gaudenz Alesch. "Reliability considerations of future energy systems : multi-carrier systems and the effect of energy storage /." Zürich : ETH, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=17058.

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11

Liu, Yi. "STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3550.

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As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide

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12

Steighner, Jason. "Investigation and trade study on hot carrier reliability of the PHEMT for DC and RF performance." Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5048.

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A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstr

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13

Raghunathan, Uppili Srinivasan. "TCAD modeling of mixed-mode degradation in SiGe HBTs." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54315.

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14

Zhu, Chendong. "The mixed-mode reliability stress of Silicon-Germanium heterojunction bipolar transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14647.

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The objective of the dissertation is to combine the recent Mixed-Mode reliability stress studies into a single text. The thesis starts with a review of silicon-germanium heterojunction bipolar transistor fundamentals, development trends, and the conventional reliability stress paths used in industry, after which the new stress path, Mixed-Mode stress, is introduced. Chapter 2 is devoted to an in-depth discussion of damage mechanisms that includes the impact ionization effct and the selfheating effect. Chapter 3 goes onto the impact ionization effect using two-dimensional calibrated MEDICI simu

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15

Huang, Wei-Jie, and Wei-Jie Huang. "Towards Increased Photovoltaic Energy Generation Efficiency and Reliability: Quantum-Scale Spectral Sensitizers in Thin-Film Hybrid Devices and Microcracking in Monocrystalline Si." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/623175.

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The present work focuses on two strategies contributing to the development of high efficiency, cost-effective photovoltaic (PV) technology for renewable energy generation: the design of new materials offering enhanced opto-electronic performance and the investigation of material degradation processes and their role in predicting the long-term reliability of PV modules in the field. The first portion of the present work investigates the integration of a novel CdTe-ZnO nanocomposite material as a spectral sensitizer component within a thin-film, hybrid heterojunction (HJ) PV device structure. Q

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16

CUI, ZHI. "MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2163.

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Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and cha

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17

Chen, Chang-Chih. "System-level modeling and reliability analysis of microprocessor systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53033.

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Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking int

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18

Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.

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The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to

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19

Tran, Thi-Phuong-Yen. "CMOS 180 nm Compact Modeling Including Ageing Laws for Harsh Environment." Thesis, Bordeaux, 2022. http://www.theses.fr/2022BORD0185.

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Au cours des dernières décennies, la demande de fonctionnalités complexes et d'intégration haute densité pour les Circuits Intégrés (CI) a mené à une réduction de la taille des dispositifs métal-oxyde-silicium (MOS). Dans ce scénario, les problèmes de fiabilité sont les préoccupations considérables par suite de la miniaturisation de l'appareil, telles que Hot Carrier Injection (HCI) et Bias Temperature Instability (BTI) qui ont un impact sérieux sur les performances de l'appareil. Dans certains domaines d'application où le coût des pannes est extrêmement élevé, comme l'espace, les champs pétro

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20

Mamy, Randriamihaja Yoann. "Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4781/document.

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L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord

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21

Arfaoui, Wafa. "Fiabilité Porteurs Chauds (HCI) des transistors FDSOI 28nm High-K grille métal." Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4335.

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Au sein de la course industrielle à la miniaturisation et avec l’augmentation des exigences technologiques visant à obtenir plus de performances sur moins de surface, la fiabilité des transistors MOSFET est devenue un sujet d’étude de plus en plus complexe. Afin de maintenir un rythme de miniaturisation continu, des nouvelles architectures de transistors MOS en été introduite, les technologies conventionnelles sont remplacées par des technologies innovantes qui permettent d'améliorer l'intégrité électrostatique telle que la technologie FDSOI avec des diélectriques à haute constante et grille m

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22

Ndiaye, Cheikh. "Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI." Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182/document.

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L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des trans

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23

Guichard, Éric. "Contribution à l'étude de la sensibilité au vieillissement des technologies SOI durcies." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0102.

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Devant le developpement des technologies soi dans le domaine militaire et spatial et aujourd'hui civil, il s'agissait d'essayer de mieux comprendre les mecanismes physiques de degradation, par porteurs chauds, intervenant dans les transistors et les circuits. La specificite des transistors soi par rapport aux transistors bulk est la presence de l'oxyde enterre. Ce dernier, bien qu'apportant de nombreux avantages au fonctionnement des dispositifs, est considere, aujourd'hui encore, comme le talon d'achille des transistors soi vis a vis du vieillissement. Cependant, nous avons montre que pour le

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24

Vincent, Emmanuel. "Étude des propriétés de dégradation du système SI/SIO#2 : application a la fiabilité des filières CMOS submicroniques." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0126.

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Compte tenu de la reduction spectaculaire des dimensions critiques des dispositifs elementaires utilises dans la fabrication des circuits integres, les questions de fiabilite des dielectriques minces des technologies cmos submicroniques sont au cur des preoccupations de l'industrie des semiconducteurs. Dans ce contexte, l'objet de ce memoire est l'etude des phenomenes physiques responsables de la degradation des isolants intervenant dans les dispositifs mos. Apres des rappels generaux sur le systeme si-sio#2 et sur les methodes de caracterisation utilisees, nous presentons dans le deuxieme cha

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25

Shams, Kollol 3085942. "Understanding the Value of Travel Time Reliability for Freight Transportation to Support Freight Planning." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2828.

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Today’s logistics practices are moving from inventory-based push supply chains to replenishment-based pull supply chains, leading to a lower and less centralized inventory, smaller shipment sizes, and more just-in-time deliveries. As a result, industries are now demanding greater reliability in freight transportation. Delays and uncertainty in freight transportation translate directly into additional inventory, higher manufacturing costs, less economic competitiveness for businesses, and higher costs of goods that are being passed on to the consumers. Given the growing demand in freight transp

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26

Moras, Albero Miquel. "Caracterización de la variabilidad dependiente del tiempo de MOSFETs ultraescalados para su modelado compacto." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/457581.

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El transistor MOSFET es uno de los dispositivos más utilizados en multitud de aplicaciones electrónicas gracias a sus excelentes características de funcionamiento, su bajo consumo y su gran capacidad de miniaturización. El constante progreso de la tecnología microelectrónica ha permitido una reducción de las dimensiones de este dispositivo, lo que ha conllevado mejoras en las prestaciones de los circuitos integrados (CI). Sin embargo, cuando estas dimensiones alcanzan el rango nanométrico, aparecen diferentes fenómenos físicos de distinta naturaleza como efectos de canal corto, procesos cuánti

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27

Jacquet, Thomas. "Reliability of SiGe, C HBTs operating at 500 GHz : characterization and modeling." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0354/document.

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Le sujet de cette thèse est l’analyse de la fiabilité des transistors bipolaires à hétérojonction SiGe:C et descircuits intégrés associés. Dans ce but, un modèle compact prenant en compte l’évolution des caractéristiquesdes transistors SiGe:C a été développé. Ce modèle intègre les lois de vieillissement des mécanismes dedéfaillance des transistors identifiés lors des tests de vieillissement. Grâce aux simulations physiques TCADcomplétées par une analyse du bruit basses fréquences, deux mécanismes de dégradations ont été localisés. Eneffet, selon les conditions de polarisation, des porteurs cha

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28

Laurent, Antoine. "Etude des mécanismes physiques de fiabilité sur transistors Trigate/Nanowire." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT024/document.

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En continuant à suivre la loi de Moore, les transistors ont atteint des dimensions de plus en plus réduites. Cependant pour les largeurs inférieures à 100nm, des effets parasites dits de canaux courts sont apparus. Il a ainsi fallu développer de nouvelles architectures, à savoir les transistors 3D, aussi appelés trigates, finfets ou encore nanofils. Le remplacement des transistors planaires utilisés depuis les années 60 par ces dispositifs tridimensionnels constitue une réelle rupture technologique et pose de sérieuses questions quant à la fiabilité de ces nouveaux composants électroniques. Pa

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29

Bonner, J. K. "Kirk", and Silveira Carl de. "Thermal Cycling Fatigue Investigation of Surface Mounted Components with Eutectic Tin-Lead Solder Joints." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611418.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>Eutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is importa

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30

Candelier, Philippe. "Contribution à l'amélioration de la fiabilité des mémoires non volatiles de type flash EEPROM." Université Joseph Fourier (Grenoble ; 1971-2015), 1997. http://www.theses.fr/1997GRE10245.

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L'augmentation continue de la densite d'integration des memoires non-volatiles de type flash eeprom passe par la comprehension des mecanismes de degradation intervenant dans le cadre du fonctionnement de ces memoires. Nous avons pu correler les degradations observees sur des dispositifs elementaires (transistors et capacites) aux derives des caracteristiques de la cellule flash. Cette etude demontre que de nouveaux modes de fonctionnement devront etre envisages. Le mode d'effacement par la source, habituellement utilise, pose des problemes d'optimisation technologique pour les cellules de faib

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31

Couret, Marine. "Failure mechanisms implementation into SiGe HBT compact model operating close to safe operating area edges." Thesis, Bordeaux, 2020. http://www.theses.fr/2020BORD0265.

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Afin de répondre au marché florissant des applications térahertz, les filières BiCMOS atteignent désormais des fréquences de coupure supérieures à 0,5 THz. Ces performances dynamiques sont obtenues grâce aux améliorations technologiques apportées aux transistors bipolaires à hétérojonction (TBH) SiGe. Toutefois, cette montée en fréquence à entraîner un décalage du point de polarisation des transistors au plus proche, voir au-delà, de l’aire de sécurité de fonctionnement (SOA). En conséquence, de nombreux effets physiques « parasites » sont présents tel que l’ionisation par impact ou bien l’aut

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32

Faynot, Olivier. "Caractérisation et modélisation du fonctionnement des transistors MOS ultra-submicroniques fabriqués sur films SIMOX très minces." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0121.

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Ce memoire est consacre a la caracterisation et a la modelisation des transistors mos fabriques sur des films simox tres minces. Dans le premier chapitre, outre l'orientation de la microelectronique, nous detaillons l'interet potentiel que peut susciter la technologie soi pour les applications basse-tension. Ensuite, nous analysons les phenomenes de couplage d'interfaces apparaissant dans deux types de conduction de transistors totalement desertes: la conduction par canal d'inversion et la conduction par canal d'accumulation. Puis, les effets de canaux courts sont etudies dans l'objectif d'opt

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33

Bestory, Corinne. "Développement de stratégies de conception en vue de la fiabilité pour la simulation et la prévision des durées de vie de circuits intégrés dès la phase de conception." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13627/document.

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La conception en vue de la fiabilité (DFR, Design for Reliability) consiste à simuler le vieillissement électrique des composants élémentaires pour évaluer la dégradation d'un circuit complet. C'est dans ce contexte de fiabilité et de simulation de cette dernière, qu'une stratégie de conception en vue de la fiabilité a été développée au cours de ses travaux. Cette stratégie, intégrant une approche « système » de la simulation, s'appuie sur l'ajout de deux étapes intermédiaires dans la phase de conception. La première étape est une étape de construction de modèles comportementaux compacts à l'a

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Tsao, Chih-Pin, and 曹志彬. "Hot-Carrier reliability in deep submicron CMOS device." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/16925700898041641574.

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碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>90<br>In this study, the effects of hot-carrier induced drain current degradation and gate leakage current induced by ultra-thin gate oxide on 0.18μm and 0.15μm CMOS devices will be investigated. In the first chapter, the background of hot-carrier effects will be discussed. Results show that in deep submicron device, the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than 0.1V which was well known as the worst case condition in long channel device. The worst case of characterized Vd was found to lager at high

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Lee, Jia-Rui, and 李佳叡. "Studies on Hot-Carrier Reliability in High-Voltage MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/46789891396748452586.

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博士<br>國立成功大學<br>微電子工程研究所碩博士班<br>96<br>In this dissertation, the hot-carrier-induced degradation in 0.35 μm n-type self-aligned lateral double-diffused MOSFET (LDMOS) and p-type drain-extended MOSFET (DEMOS) devices are studied. When the nLDMOS device is used in a power switching circuits with an unclamped inductive load, the off-state avalanche breakdown occurs during on-state to off-state transient. The device degrades because of the high electric field and impact ionization located near the drain side poly-gate edge. The main mechanism of device degradation is the interface states and posi

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36

Li, Jian Fang, and 李劍芳. "Reliability analysis for mid-ship structure of bulk carrier." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/49487316057887387484.

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37

Pagey, Manish Prabhakar. "Hot-carrier reliability simulation in aggresively scaled MOS transistors." 2003. http://etd.library.vanderbilt.edu/ETD-db/available/etd-12032003-100902/.

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38

Wu, Tai-Ching, and 吳泰慶. "Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/30479749998144585484.

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碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>97<br>In this thesis, the experiment mainly studies on the hot-carrier reliability of a 0.35 μm p-type lateral double diffusion metal oxide semiconductor field-effect-transistor. Base on the degradation of every parameter, we can analyze the mechanism causing the device degradation. First, the differences between HV device structure and normal LV MOS structure are introduced. The development of LDMOS device is also introduced. As process scaling down, the reliability becomes an important issue to discuss. After hot carrier stress experiment on standard dimension

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Chen, Shiang-Yu, and 陳翔裕. "Hot Carrier Reliability of 12V High Voltage n-LDMOS Transistors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/34503827838537514146.

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碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>94<br><P>In recent years, LDMOS transistors have been widely used in high voltage integrated circuits (HVIC). That’s due to its process flow being compatible with low voltage CMOS devices. In some applications, LMDOS transistors operate under high gate and drain voltage, thus hot carrier reliability becomes a serious concern. In this thesis, hot carrier reliability of LDMOS transistors will be investigated in detail. <P>First of all, LDMOS transistors designed to operate at Vds=12V are studied. Substrate current (Isub) of the devices continually increases as mea

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40

Hsiao, Mei-Yi, and 蕭美宜. "Effect of Oxygen Annealing on Hot-Carrier Reliability of HfO2 nMOSFETs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/c46sx3.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>99<br>In order to avoid the short channel effect in the MOSFET, the thickness of the dielectric has gradually become thinner. However, the serious problems of leakage current and reliability due to the thinning oxide are also unavoidable. Therefore, using high-k materials passes into one of the most significant studies. After many years of researches, the Hafnium-based high-k materials emerge as the most promising candidates to replace SiO2 and SiON gate dielectrics. It has been reported that the oxygen vacancy defects of high-k dielectrics can be passivated by a

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Yang, Hui-Ting, and 楊惠婷. "A Study on the Hot-Carrier Reliability of 200V SOI PLDMOS." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/17003352917403750503.

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碩士<br>亞洲大學<br>資訊工程學系碩士班<br>97<br>The reliability of the high voltage P-LDMOS is examined extensively by moving the impact ionization area and varying the surface electric field in the drift region. Breakdown walkout in high-voltage P-LDMOS devices on a thin SOI layer is demonstrated closely related to gate-metal field plate extension and gate channel length. The two field peaks along the channel can be reduced by varying the impact ionization area properly. N-well ion implantation dose monitoring and gate-metal field plate extensions are also studied to effectively improve the breakdown voltag

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Liu, Xin-chang, and 劉信昌. "Reliability Analysis of a Maintained Bulk Carrier Subjected Corrosion and Fatigue." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19944119167581906619.

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碩士<br>國立成功大學<br>系統及船舶機電工程學系碩博士班<br>97<br>In general the structure of large ships are made of steel, the corrosion and fatigue of the steel may occur due to the waves and harsh environment. The purpose of this study is to assess fatigue translate into structure failure and reliability analysis on the structure of maintained ships after failure under the effect of combined corrosion and fatigue crack. The reliability analysis of fatigue crack is broken down into two failure model, for one is concerning the reliability of the possession of initial crack in fatigue crack growth, the other is regar

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Kuo, Yu-Chen, and 郭育禎. "Characteristics and Hot Carrier Reliability in 40V n-type LDMOS Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22495897312119913693.

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碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>97<br>In this thesis, device characteristics and hot carrier reliability of n-type LDMOS transistors with different device dimension are investigated. The device used in this thesis has four main layout parameters: channel length, accumulation length, length of drift region with gate control and length of drift region without gate control. As for device characteristics, the effect of parameters of channel length and accumulation length are more significant than that of parameters of drift region with gate control and length of drift region without gate control.

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Yih, Cherng-Ming, and 易成名. "Investigation of Hot-Carrier Injection Induced Reliability Issues in Flash Memories." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/73427801549497138777.

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博士<br>國立交通大學<br>電子工程系<br>87<br>Hot carrier induced reliability issues have become increasingly important for miniaturized flash memory design. These reliability issues include hot carrier related issues, such as oxide damage, program/erase cycling endurance, disturbance, and data retention. In this dissertation, the hot-carrier injection induced reliability problems in stacked-gate flash memories is investigated. First, a new model based on the charge-balance theory was proposed to accurately calculate the floating gate voltage. Based on the new model, the method to determine the ca

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Liu, Jun-Lin, and 劉駿霖. "Reliability Analysis of a Double Hull Bulk Carrier with Corrosion Effects." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65529682437162812242.

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碩士<br>國立成功大學<br>系統及船舶機電工程學系碩博士班<br>93<br>Generally, the hull structures usually are made of steel, however the steel will deteriorate under the environment of the high salt and the high humidity. In order to solve the damage of ship due to corrosion, many experts have developed several kinds of linear or non-linear ship corrosion model respectively by way of material experiment、statistics data and various corrosion model. In general, non-linear corrosion model can explain the real corrosion process more than linear corrosion model. Therefore, the non-linear corrosion model is used in present i

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Kuo, Jui-Min, and 郭瑞旻. "Hot-carrier Induced Reliability Degradation in High Voltage P-LDMOS Transistors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/44883155072548759819.

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碩士<br>國立清華大學<br>電子工程研究所<br>100<br>In this thesis, the p-type lateral diffused MOS (LDMOS) transistor used in this work is implemented with a 0.5 μm 2p3m high-voltage process. To investigate the reliability issue, charge pumping method is used to detect the interface states of the device. And to combine TCAD (Technology Computer Aided Design) simulation supports the analysis of the device. First, we have background review, which contains the introduction of the high-voltage device, the mechanism of hot-carrier degradation, and the methodology of charge pumping. Then the measurement set-up a

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Lu, Ying-Hsin, and 盧頴新. "Investigation on the Reliability and Hot Carrier degradation in Advance MOSFET." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/56e373.

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博士<br>國立中山大學<br>物理學系研究所<br>107<br>Since 1960, the world’s the first metal-oxide-semiconductor-field-effect transistors (MOSFETs) were invented by Kahng and Atalla in Bell Lab. The transistor length is 25 μm, and gate oxide thickness is 100nm. Nowadays, MOSFETs have become the dominant devices for ultra-large-scale integration (ULSI) circuits due to its low cost, power consumption and easy to scale down. In 1965, Gordon Moore, one of Intel''s founders, first proposed Moore’s Law: The number of components per integrated circuit will doubling every year. And with the advancement of tech

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Ze-Wei, Jhou. "DC Hot Carrier Reliability at Elevated Temperatures for nMOSFETs Using 0.13Mum Technology." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0006-2007200517293700.

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Wu, Kuo-Ming, and 吳國銘. "Development and Hot-Carrier Reliability Study of Integrated High-Voltage MOSFET Transistors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/16242266300247122086.

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博士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>In this dissertation, the integrated high-voltage MOSFET with three different kinds of application, structure and operation voltage are studied and analyzed on hot-carrier reliability and process conditions correlations. Comparing the hot-carrier reliability of 0.5um 40V N-type drain extended MOSFET (DEMOS) transistors to the conventional low-voltage CMOS transistors; there are there kinds of obviously phenomena – Kick effect accelerated the device degradation, the degradation is proportional to the gate bias and degradation recovery. The hot-carrier reliabi

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Yeh, Chang Hua, and 葉昌樺. "Investigation of Hot Carrier Reliability Issues in STI and Strained-Silicon MOSFET's." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/52610615356862911344.

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碩士<br>長庚大學<br>電子工程研究所<br>92<br>This thesis addresses the issues related to hot carrier reliabilities in CMOS devices. At first, results on the width dependent hot-carrier (HC) degradation for shallow-trench-isolated (STI) CMOS devices are presented. This is a very crucial issue for the present and future CMOS ULSI using STI technologies. Both thick gate oxide and thin gate oxide exhibit different effects for STI CMOS devices. And then, the analysis of interface reliability in the most advanced strained-silicon devices will be studied. It is important to evaluate the electric property of the ne

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