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Journal articles on the topic 'Cache codée'

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Published: 25 May 2024

Last updated: 31 July 2025

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1

Ding, Wei, Yuanrui Zhang, Mahmut Kandemir, and Seung Woo Son. "Compiler-Directed File Layout Optimization for Hierarchical Storage Systems." Scientific Programming 21, no. 3-4 (2013): 65–78. http://dx.doi.org/10.1155/2013/167581.

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File layout of array data is a critical factor that effects the behavior of storage caches, and has so far taken not much attention in the context of hierarchical storage systems. The main contribution of this paper is a compiler-driven file layout optimization scheme for hierarchical storage caches. This approach, fully automated within an optimizing compiler, analyzes a multi-threaded application code and determines a file layout for each disk-resident array referenced by the code, such that the performance of the target storage cache hierarchy is maximized. We tested our approach using 16 I

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Calciu, Irina, M. Talha Imran, Ivan Puddu, et al. "Using Local Cache Coherence for Disaggregated Memory Systems." ACM SIGOPS Operating Systems Review 57, no. 1 (2023): 21–28. http://dx.doi.org/10.1145/3606557.3606561.

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Disaggregated memory provides many cost savings and resource provisioning benefits for current datacenters, but software systems enabling disaggregated memory access result in high performance penalties. These systems require intrusive code changes to port applications for disaggregated memory or employ slow virtual memory mechanisms to avoid code changes. Such mechanisms result in high overhead page faults to access remote data and high dirty data amplification when tracking changes to cached data at page-granularity. In this paper, we propose a fundamentally new approach for disaggregated me

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Pan, Qinglin, Ji Qi, Jiatai He, Heng Zhang, Jiageng Yu, and Yanjun Wu. "Beaver: A High-Performance and Crash-Consistent File System Cache via PM-DRAM Collaborative Memory Tiering." Proceedings of the ACM on Measurement and Analysis of Computing Systems 8, no. 3 (2024): 1–24. https://doi.org/10.1145/3700414.

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The in-memory cache layer is crucial in building a file system. Crash-consistency is highly desirable for applications running on the file system, ensuring that data is written in an all-or-none fashion during unexpected system failures or crashes. However, existing works fail to achieve both high read and write performance in constructing a crash-consistent cache layer. In this paper, we propose Beaver, a new in-memory file system cache that achieves both crash-consistency and high read/write performance. Beaver exploits a read/write distinguishable memory hierarchy involving both PM and DRAM

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Pan, Qinglin, Ji Qi, Jiatai He, Heng Zhang, Jiageng Yu, and Yanjun Wu. "Beaver: A High-Performance and Crash-Consistent File System Cache via PM-DRAM Collaborative Memory Tiering." ACM SIGMETRICS Performance Evaluation Review 53, no. 1 (2025): 70–72. https://doi.org/10.1145/3744970.3727273.

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The in-memory cache layer is crucial in building a file system. Crash-consistency is highly desirable for applications running on the file system, ensuring that data is written in an all-or-none fashion during unexpected system failures or crashes. However, existing works fail to achieve both high read and write performance in constructing a crash-consistent cache layer. In this paper, we propose Beaver, a new in-memory file system cache that achieves both crash-consistency and high read/write performance. Beaver exploits a read/write distinguishable memory hierarchy involving both PM and DRAM

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Charrier, Dominic E., Benjamin Hazelwood, Ekaterina Tutlyaeva, et al. "Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver." International Journal of High Performance Computing Applications 33, no. 5 (2019): 973–86. http://dx.doi.org/10.1177/1094342019842645.

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We study the performance behaviour of a seismic simulation using the ExaHyPE engine with a specific focus on memory characteristics and energy needs. ExaHyPE combines dynamically adaptive mesh refinement (AMR) with ADER-DG. It is parallelized using tasks, and it is cache efficient. AMR plus ADER-DG yields a task graph which is highly dynamic in nature and comprises both arithmetically expensive tasks and tasks which challenge the memory’s latency. The expensive tasks and thus the whole code benefit from AVX vectorization, although we suffer from memory access bursts. A frequency reduction of t

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Moon, S. M. "Increasing cache bandwidth using multiport caches for exploiting ILP in non-numerical code." IEE Proceedings - Computers and Digital Techniques 144, no. 5 (1997): 295. http://dx.doi.org/10.1049/ip-cdt:19971283.

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Mittal, Shaily, and Nitin. "Memory Map: A Multiprocessor Cache Simulator." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.

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Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an opti

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Ma, Ruhui, Haibing Guan, Erzhou Zhu, Yongqiang Gao, and Alei Liang. "Code cache management based on working set in dynamic binary translator." Computer Science and Information Systems 8, no. 3 (2011): 653–71. http://dx.doi.org/10.2298/csis100327022m.

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Software code cache employed to store translated or optimized codes, amortizes the overhead of dynamic binary translation via reusing of stored-altered copies of original program instructions. Though many conventional code cache managements, such as Flush, Least-Recently Used (LRU), have been applied on some classic dynamic binary translators, actually they are so unsophisticated yet unadaptable that it not only brings additional unnecessary overhead, but also wastes much cache space, since there exist several noticeable features in software code cache, unlike pages in memory. Consequently, th

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Das, Abhishek, and Nur A. Touba. "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote." Electronics 9, no. 5 (2020): 709. http://dx.doi.org/10.3390/electronics9050709.

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Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on

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Simecek, Ivan, and Pavel Tvrdík. "A new code transformation technique for nested loops." Computer Science and Information Systems 11, no. 4 (2014): 1381–416. http://dx.doi.org/10.2298/csis131126075s.

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For good performance of every computer program, good cache utilization is crucial. In numerical linear algebra libraries, good cache utilization is achieved by explicit loop restructuring (mainly loop blocking), but it requires a complicated memory pattern behavior analysis. In this paper, we describe a new source code transformation called dynamic loop reversal that can increase temporal and spatial locality. We also describe a formal method for predicting cache behavior and evaluate results of the model accuracy by the measurements on a cache monitor. The comparisons of the numbers of measur

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Guillon, Christophe, Fabrice Rastello, Thierry Bidault, and Florent Bouchez. "Procedure placement using temporal-ordering information: Dealing with code size expansion." Journal of Embedded Computing 1, no. 4 (2005): 437–59. https://doi.org/10.3233/emc-2005-00045.

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In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size share a common and unique cache slot. Instruction cache conflicts can be partially handled at linked time by procedure placement. Pettis and Hansen give in [1] an algorithm that reorders procedures in memory by aggregating them in a greedy fashion. The Gloy and Smith algorithm [2] greatly decreases the number of conflict-misses but increases the code size by allowing gaps between procedures. The latter contains two main stages: the cache-placement phase assigns modulo addresses to min

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Luo, Ya Li. "Research of Adaptive Control Algorithm Based on the Cached Playing of Streaming Media." Applied Mechanics and Materials 539 (July 2014): 502–6. http://dx.doi.org/10.4028/www.scientific.net/amm.539.502.

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Aimed at the quality issues of current network streaming media playing, it manages by introducing a streaming media caching mechanism to help improve the playing effect. But the cached playing also has its own deficiencies, so here combines the adaptive control algorithm with the caching mechanism to solve this problem. It firstly introduces the streaming media service, and analyzes the transmission process of streaming media and adaptive media playing in detail; secondly analyzes the adaptive control algorithm of streaming media caching from the principle and design of reserving cache algorit

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Heirman, Wim, Stijn Eyerman, Kristof Du Bois, and Ibrahim Hur. "Automatic Sublining for Efficient Sparse Memory Accesses." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–23. http://dx.doi.org/10.1145/3452141.

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Sparse memory accesses, which are scattered accesses to single elements of a large data structure, are a challenge for current processor architectures. Their lack of spatial and temporal locality and their irregularity makes caches and traditional stream prefetchers useless. Furthermore, performing standard caching and prefetching on sparse accesses wastes precious memory bandwidth and thrashes caches, deteriorating performance for regular accesses. Bypassing prefetchers and caches for sparse accesses, and fetching only a single element (e.g., 8 B) from main memory (subline access), can solve

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Пуйденко, Вадим Олексійович, та Вячеслав Сергійович Харченко. "МІНІМІЗАЦІЯ ЛОГІЧНОЇ СХЕМИ ДЛЯ РЕАЛІЗАЦІЇ PSEUDO LRU ШЛЯХОМ МІЖТИПОВОГО ПЕРЕХОДУ У ТРИГЕРНИХ СТРУКТУРАХ". RADIOELECTRONIC AND COMPUTER SYSTEMS, № 2 (26 квітня 2020): 33–47. http://dx.doi.org/10.32620/reks.2020.2.03.

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The principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses both page memory organization and segment memory organization. The page memory organization is always mapped to the segment organization. Due to the cached packet cycles of the processor core, copies of the main memory pages are stored in the internal associative cache memory. The associative cache

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Sasongko, Muhammad Aditya, Milind Chabbi, Mandana Bagheri Marzijarani, and Didem Unat. "ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer." ACM Transactions on Architecture and Code Optimization 19, no. 1 (2022): 1–25. http://dx.doi.org/10.1145/3484199.

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One widely used metric that measures data locality is reuse distance —the number of unique memory locations that are accessed between two consecutive accesses to a particular memory location. State-of-the-art techniques that measure reuse distance in parallel applications rely on simulators or binary instrumentation tools that incur large performance and memory overheads. Moreover, the existing sampling-based tools are limited to measuring reuse distances of a single thread and discard interactions among threads in multi-threaded programs. In this work, we propose ReuseTracker —a fast and accu

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Zhang, Kang, Fan Fu Zhou, and Alei Liang. "DCC: A Replacement Strategy for DBT System Based on Working Sets." Applied Mechanics and Materials 251 (December 2012): 114–18. http://dx.doi.org/10.4028/www.scientific.net/amm.251.114.

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Limited memory resource has always been deemed as the major bottleneck of the program performance, not excepting for dynamic binary translation (DBT) [1] system. However, traditional methods seldom enable this issue mentioned to be solved better due to a ﬁx cache size routinely assigned for codes without considering the program behavior on the ﬂy. Though some prediction methods implemented via LRU [2] histograms can achieve better performance in Operating System, unlike pages in memory, blocks in DBT have unﬁxed sizes each other, making the prediction imprecise. In this paper, we present a new

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Gordon-Ross, Ann, Frank Vahid, and Nikil Dutt. "Combining code reordering and cache configuration." ACM Transactions on Embedded Computing Systems 11, no. 4 (2012): 1–20. http://dx.doi.org/10.1145/2362336.2399177.

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Duangthong, Chatuporn, Pornchai Supnithi, and Watid Phakphisut. "Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 16, no. 3 (2022): 237–46. http://dx.doi.org/10.37936/ecti-cit.2022163.246903.

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Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC - DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits ha

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Zhao, Yiqiang, Boning Shi, Qizhi Zhang, Yidong Yuan, and Jiaji He. "Research on Cache Coherence Protocol Verification Method Based on Model Checking." Electronics 12, no. 16 (2023): 3420. http://dx.doi.org/10.3390/electronics12163420.

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This paper analyzes the underlying logic of the processor’s behavior level code. It proposes an automatic model construction and formal verification method for the cache consistency protocol with the aim of ensuring data consistency in the processor and the correctness of the cache function. The main idea of this method is to analyze the register transfer level (RTL) code directly at the module level and variable level, and extract the key modules and key variables according to the code information. Then, based on key variables, conditional behavior statements are retrieved from the code, and

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Ding, Chen, Dong Chen, Fangzhou Liu, Benjamin Reber, and Wesley Smith. "CARL: Compiler Assigned Reference Leasing." ACM Transactions on Architecture and Code Optimization 19, no. 1 (2022): 1–28. http://dx.doi.org/10.1145/3498730.

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Data movement is a common performance bottleneck, and its chief remedy is caching. Traditional cache management is transparent to the workload: data that should be kept in cache are determined by the recency information only, while the program information, i.e., future data reuses, is not communicated to the cache. This has changed in a new cache design named Lease Cache . The program control is passed to the lease cache by a compiler technique called Compiler Assigned Reference Lease (CARL). This technique collects the reuse interval distribution for each reference and uses it to compute and

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Vishnekov, A. V., and E. M. Ivanova. "DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 191 (May 2020): 49–56. http://dx.doi.org/10.14489/vkit.2020.05.pp.049-056.

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The paper investigates the issues of increasing the performance of computing systems by improving the efficiency of cache memory, analyzes the efficiency indicators of replacement algorithms. We show the necessity of creation of automated or automatic means for cache memory tuning in the current conditions of program code execution, namely a dynamic cache replacement algorithms control by replacement of the current replacement algorithm by more effective one in current computation conditions. Methods development for caching policy control based on the program type definition: cyclic, sequentia

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Vishnekov, A. V., and E. M. Ivanova. "DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 191 (May 2020): 49–56. http://dx.doi.org/10.14489/vkit.2020.05.pp.049-056.

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The paper investigates the issues of increasing the performance of computing systems by improving the efficiency of cache memory, analyzes the efficiency indicators of replacement algorithms. We show the necessity of creation of automated or automatic means for cache memory tuning in the current conditions of program code execution, namely a dynamic cache replacement algorithms control by replacement of the current replacement algorithm by more effective one in current computation conditions. Methods development for caching policy control based on the program type definition: cyclic, sequentia

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Ma, Cong, Dinghao Wu, Gang Tan, Mahmut Taylan Kandemir, and Danfeng Zhang. "Quantifying and Mitigating Cache Side Channel Leakage with Differential Set." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 1470–98. http://dx.doi.org/10.1145/3622850.

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Cache side-channel attacks leverage secret-dependent footprints in CPU cache to steal confidential information, such as encryption keys. Due to the lack of a proper abstraction for reasoning about cache side channels, existing static program analysis tools that can quantify or mitigate cache side channels are built on very different kinds of abstractions. As a consequence, it is hard to bridge advances in quantification and mitigation research. Moreover, existing abstractions lead to imprecise results. In this paper, we present a novel abstraction, called differential set, for analyzing cache

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Sahuquillo, Julio, Noel Tomas, Salvador Petit, and Ana Pont. "Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises." IEEE Transactions on Education 50, no. 3 (2007): 244–50. http://dx.doi.org/10.1109/te.2007.900021.

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Liu, Cong, Xinyu Xu, Zhenjiao Chen, and Binghao Wang. "A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller." Electronics 12, no. 18 (2023): 3821. http://dx.doi.org/10.3390/electronics12183821.

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The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatical

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Yash, Kumar, and B. Ramesh K. "Analysis and Optimization of Memory Hierarchy." Recent Trends in Analog Design and Digital Devices 5, no. 1 (2022): 1–5. https://doi.org/10.5281/zenodo.6388324.

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<em>Cache is plays a vital role in overall performance of computer architecture. Because increase in the operating gap between the processor and the main memory, it is essential to fill the void by designing effective memory sequences that can decrease the amount of memory access time. From the recent research on enhancing the performance of the archive is focused on reducing the rate of depletion. Cache loss rate can be minimize by adjusting the data or command cache. Data is too massive to be stored in the archive so data storage upgrades are necessary as it has to be moved between memory an

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Makhkamova, Ozoda, and Doohyun Kim. "A Conversation History-Based Q&A Cache Mechanism for Multi-Layered Chatbot Services." Applied Sciences 11, no. 21 (2021): 9981. http://dx.doi.org/10.3390/app11219981.

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Chatbot technologies have made our lives easier. To create a chatbot with high intelligence, a significant amount of knowledge processing is required. However, this can slow down the reaction time; hence, a mechanism to enable a quick response is needed. This paper proposes a cache mechanism to improve the response time of the chatbot service; while the cache in CPU utilizes the locality of references within binary code executions, our cache mechanism for chatbots uses the frequency and relevance information which potentially exists within the set of Q&A pairs. The proposed idea is to enab

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Lin, Bo, Shangwen Wang, Ming Wen, and Xiaoguang Mao. "Context-Aware Code Change Embedding for Better Patch Correctness Assessment." ACM Transactions on Software Engineering and Methodology 31, no. 3 (2022): 1–29. http://dx.doi.org/10.1145/3505247.

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Despite the capability in successfully fixing more and more real-world bugs, existing Automated Program Repair (APR) techniques are still challenged by the long-standing overfitting problem (i.e., a generated patch that passes all tests is actually incorrect). Plenty of approaches have been proposed for automated patch correctness assessment (APCA ). Nonetheless, dynamic ones (i.e., those that needed to execute tests) are time-consuming while static ones (i.e., those built on top of static code features) are less precise. Therefore, embedding techniques have been proposed recently, which asses

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Cheng, Shing Hing William, Chitchanok Chuengsatiansup, Daniel Genkin, et al. "Evict+Spec+Time: Exploiting Out-of-Order Execution to Improve Cache-Timing Attacks." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 3 (2024): 224–48. http://dx.doi.org/10.46586/tches.v2024.i3.224-248.

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Speculative out-of-order execution is a strategy of masking execution latency by allowing younger instructions to execute before older instructions. While originally considered to be innocuous, speculative out-of-order execution was brought into the spotlight with the 2018 publication of the Spectre and Meltdown attacks. These attacks demonstrated that microarchitectural side channels can leak sensitive data accessed by speculatively executed instructions that are not part of the normal program execution. Since then, a significant effort has been vested in investigating how microarchitectural

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Ansari, Ali, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad. "Code Layout Optimization for Near-Ideal Instruction Cache." IEEE Computer Architecture Letters 18, no. 2 (2019): 124–27. http://dx.doi.org/10.1109/lca.2019.2924429.

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Tomiyama, Hiroyuki, and Hiroto Yasuura. "Code placement techniques for cache miss rate reduction." ACM Transactions on Design Automation of Electronic Systems 2, no. 4 (1997): 410–29. http://dx.doi.org/10.1145/268424.268469.

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Ryoo, Jihyun, Mahmut Taylan Kandemir, and Mustafa Karakoy. "Memory Space Recycling." Proceedings of the ACM on Measurement and Analysis of Computing Systems 6, no. 1 (2022): 1–24. http://dx.doi.org/10.1145/3508034.

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Many program codes from different application domains process very large amounts of data, making their cache memory behavior critical for high performance. Most of the existing work targeting cache memory hierarchies focus on improving data access patterns, e.g., maximizing sequential accesses to program data structures via code and/or data layout restructuring strategies. Prior work has addressed this data locality optimization problem in the context of both single-core and multi-core systems. Another dimension of optimization, which can be as equally important/beneficial as improving data ac

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Błaszyński, Piotr, and Włodzimierz Bielecki. "High-Performance Computation of the Number of Nested RNA Structures with 3D Parallel Tiled Code." Eng 4, no. 1 (2023): 507–25. http://dx.doi.org/10.3390/eng4010030.

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Many current bioinformatics algorithms have been implemented in parallel programming code. Some of them have already reached the limits imposed by Amdahl’s law, but many can still be improved. In our paper, we present an approach allowing us to generate a high-performance code for calculating the number of RNA pairs. The approach allows us to generate parallel tiled code of the maximal dimension of tiles, which for the discussed algorithm is 3D. Experiments carried out by us on two modern multi-core computers, an Intel(R) Xeon(R) Gold 6326 (2.90 GHz, 2 physical units, 32 cores, 64 threads, 24

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Bielecki, Włodzimierz, Piotr Błaszyński, and Marek Pałkowski. "3D Tiled Code Generation for Nussinov’s Algorithm." Applied Sciences 12, no. 12 (2022): 5898. http://dx.doi.org/10.3390/app12125898.

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Current state-of-the-art parallel codes used to calculate the maximum number of pairs for a given RNA sequence by means of Nussinov’s algorithm do not allow for achieving speedup close up to the number of the processors used for execution of those codes on multi-core computers. This is due to the fact that known codes do not make full use of and derive benefit from cache memory of such computers. There is a need to develop new approaches allowing for increasing cache exploitation in multi-core computers. One of such possibilities is increasing the dimension of tiles in generated target tiled c

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Murugan, Dr. "Hybrid LRU Algorithm for Enterprise Data Hub using Serverless Architecture." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 4 (2021): 441–49. http://dx.doi.org/10.17762/turcomat.v12i4.525.

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In hybrid LRU algorithm was built to execute parameterized priority queue using Least Recently Used model. It helped to determine the object in an optimum mode to remove from cache. Experiment results demonstrated ~30% decrease of the execution time to extract data from cache store during object cache extraction process. In the era of modern utility computing theory, Serverless architecture is the cloud platform concept to hide the server usage from the development community and runs the code on-demand basis. This paper provides Hybrid LRU algorithm by leveraging Serverless Architecture benefi

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Steenkiste, P. "The impact of code density on instruction cache performance." ACM SIGARCH Computer Architecture News 17, no. 3 (1989): 252–59. http://dx.doi.org/10.1145/74926.74954.

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Marathe, Jaydeep, and Frank Mueller. "Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks." IEEE Transactions on Parallel and Distributed Systems 18, no. 6 (2007): 818–34. http://dx.doi.org/10.1109/tpds.2007.1058.

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Naik Dessai, Sanket Suresh, and Varuna Eswer. "Embedded Software Testing to Determine BCM5354 Processor Performance." International Journal of Software Engineering and Technologies (IJSET) 1, no. 3 (2016): 121. http://dx.doi.org/10.11591/ijset.v1i3.4577.

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Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation of embedded testing procedure to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating sys

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Oktrifianto, Rahmat, Dani Adhipta, and Warsun Najib. "Page Load Time Speed Increase on Disease Outbreak Investigation Information System Website." IJITEE (International Journal of Information Technology and Electrical Engineering) 2, no. 4 (2019): 114. http://dx.doi.org/10.22146/ijitee.46599.

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Outbreaks or extraordinary events often become an issue that occurs in Indonesia. Therefore, an outbreak investigation information system is required to collect, manage and analyze data quickly and accurately. On the other hand, challenges in data accessing processes in certain locations are still constrained by a slow internet connection. This paper conducted speed increase of a page load or site speed time from disease outbreaks investigation information system website.Page load time speed testing was carried out using Google Chrome Developer Tools and using simulation speeds of 2.5 Mbps. Te

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Wang, Xiang, Zongmin Zhao, Dongdong Xu, et al. "Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor." Electronics 9, no. 7 (2020): 1165. http://dx.doi.org/10.3390/electronics9071165.

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Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, t

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Pitchanathan, Arjun, Kunwar Grover, and Tobias Grosser. "Falcon: A Scalable Analytical Cache Model." Proceedings of the ACM on Programming Languages 8, PLDI (2024): 1854–78. http://dx.doi.org/10.1145/3656452.

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Compilers often use performance models to decide how to optimize code. This is often preferred over using hardware performance measurements, since hardware measurements can be expensive, limited by hardware availability, and makes the output of compilation non-deterministic. Analytical models, on the other hand, serve as efficient and noise-free performance indicators. Since many optimizations focus on improving memory performance, memory cache miss rate estimations can serve as an effective and noise-free performance indicator for superoptimizers, worst-case execution time analyses, manual pr

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Eswer, Varuna, and Sanket Suresh Naik Dessai. "Embedded Software Engineering Approach to Implement BCM5354 Processor Performance." International Journal of Software Engineering and Technologies (IJSET) 1, no. 1 (2016): 41. http://dx.doi.org/10.11591/ijset.v1i1.4568.

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Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS) using software engine

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Steiner, Michael, Thomas Köhler, Lukas Radl, and Markus Steinberger. "Frustum Volume Caching for Accelerated NeRF Rendering." Proceedings of the ACM on Computer Graphics and Interactive Techniques 7, no. 3 (2024): 1–22. http://dx.doi.org/10.1145/3675370.

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Neural Radiance Fields (NeRFs) have revolutionized the field of inverse rendering due to their ability to synthesize high-quality novel views and applicability in practical contexts. NeRFs leverage volume rendering, evaluating view-dependent color at each sample with an expensive network, where a high computational burden is placed on extracting an informative, view-independent latent code. We propose a temporal coherence method to accelerate NeRF rendering by caching the latent codes of all samples in an initial viewpoint and reusing them in consecutive frames. By utilizing a sparse frustum v

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Benini, L., A. Macii, and A. Nannarelli. "Code compression architecture for cache energy minimisation in embedded systems." IEE Proceedings - Computers and Digital Techniques 149, no. 4 (2002): 157. http://dx.doi.org/10.1049/ip-cdt:20020467.

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Chen, W. Y., P. P. Chang, T. M. Conte, and W. W. Hwu. "The effect of code expanding optimizations on instruction cache design." IEEE Transactions on Computers 42, no. 9 (1993): 1045–57. http://dx.doi.org/10.1109/12.241594.

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Wang, Weike, Xiang Wang, Pei Du, et al. "Embedded System Confidentiality Protection by Cryptographic Engine Implemented with Composite Field Arithmetic." MATEC Web of Conferences 210 (2018): 02047. http://dx.doi.org/10.1051/matecconf/201821002047.

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Embedded systems are subjecting to various kinds of security threats. Some malicious attacks exploit valid code gadgets to launch destructive actions or to reveal critical details. Some previous memory encryption strategies aiming at this issue suffer from unacceptable performance overhead and resource consumption. This paper proposes a hardware based confidentiality protection method to secure the code and data stored and transferred in embedded systems. This method takes advantage of the I/D-cache structure to reduce the frequency of the cryptographic encryption and decryption processing. We

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Fahringer, T., and A. Požgaj. "P3T+: A Performance Estimator for Distributed and Parallel Programs." Scientific Programming 8, no. 2 (2000): 73–93. http://dx.doi.org/10.1155/2000/217384.

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Developing distributed and parallel programs on today's multiprocessor architectures is still a challenging task. Particular distressing is the lack of effective performance tools that support the programmer in evaluating changes in code, problem and machine sizes, and target architectures. In this paper we introduceP3T+ which is a performance estimator for mostly regular HPF (High Performance Fortran) programs but partially covers also message passing programs (MPI).P3T+ is unique by modeling programs, compiler code transformations, and parallel and distributed architectures. It computes at c

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Shin, Dong-Jin, and Jeong-Joon Kim. "Cache-Based Matrix Technology for Efficient Write and Recovery in Erasure Coding Distributed File Systems." Symmetry 15, no. 4 (2023): 872. http://dx.doi.org/10.3390/sym15040872.

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With the development of various information and communication technologies, the amount of big data has increased, and distributed file systems have emerged to store them stably. The replication technique divides the original data into blocks and writes them on multiple servers for redundancy and fault tolerance. However, there is a symmetrical space efficiency problem that arises from the need to store blocks larger than the original data. When storing data, the Erasure Coding (EC) technique generates parity blocks through encoding calculations and writes them separately on each server for fau

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Sieck, Florian, Zhiyuan Zhang, Sebastian Berndt, Chitchanok Chuengsatiansup, Thomas Eisenbarth, and Yuval Yarom. "TeeJam: Sub-Cache-Line Leakages Strike Back." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 1 (2023): 457–500. http://dx.doi.org/10.46586/tches.v2024.i1.457-500.

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The microarchitectural behavior of modern CPUs is mostly hidden from developers and users of computer software. Due to a plethora of attacks exploiting microarchitectural behavior, developers of security-critical software must, e.g., ensure their code is constant-time, which is cumbersome and usually results in slower programs. In practice, small leakages which are deemed not exploitable still remain in the codebase. For example, sub-cache-line leakages have previously been investigated in the CacheBleed and MemJam attacks, which are deemed impractical on modern platforms.In this work, we revi

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Cho, Won, and Joonho Kong. "Memory and Cache Contention Denial-of-Service Attack in Mobile Edge Devices." Applied Sciences 11, no. 5 (2021): 2385. http://dx.doi.org/10.3390/app11052385.

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In this paper, we introduce a memory and cache contention denial-of-service attack and its hardware-based countermeasure. Our attack can significantly degrade the performance of the benign programs by hindering the shared resource accesses of the benign programs. It can be achieved by a simple C-based malicious code while degrading the performance of the benign programs by 47.6% on average. As another side-effect, our attack also leads to greater energy consumption of the system by 2.1× on average, which may cause shorter battery life in the mobile edge devices. We also propose detection and m

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