Relevant bibliographies by topics / Cache codée

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Cache codée'

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Published: 25 May 2024

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Journal articles on the topic "Cache codée"

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Ding, Wei, Yuanrui Zhang, Mahmut Kandemir, and Seung Woo Son. "Compiler-Directed File Layout Optimization for Hierarchical Storage Systems." Scientific Programming 21, no. 3-4 (2013): 65–78. http://dx.doi.org/10.1155/2013/167581.

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File layout of array data is a critical factor that effects the behavior of storage caches, and has so far taken not much attention in the context of hierarchical storage systems. The main contribution of this paper is a compiler-driven file layout optimization scheme for hierarchical storage caches. This approach, fully automated within an optimizing compiler, analyzes a multi-threaded application code and determines a file layout for each disk-resident array referenced by the code, such that the performance of the target storage cache hierarchy is maximized. We tested our approach using 16 I/O intensive application programs and compared its performance against two previously proposed approaches under different cache space management schemes. Our experimental results show that the proposed approach improves the execution time of these parallel applications by 23.7% on average.
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Calciu, Irina, M. Talha Imran, Ivan Puddu, Sanidhya Kashyap, Hasan Al Maruf, Onur Mutlu, and Aasheesh Kolli. "Using Local Cache Coherence for Disaggregated Memory Systems." ACM SIGOPS Operating Systems Review 57, no. 1 (June 26, 2023): 21–28. http://dx.doi.org/10.1145/3606557.3606561.

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Disaggregated memory provides many cost savings and resource provisioning benefits for current datacenters, but software systems enabling disaggregated memory access result in high performance penalties. These systems require intrusive code changes to port applications for disaggregated memory or employ slow virtual memory mechanisms to avoid code changes. Such mechanisms result in high overhead page faults to access remote data and high dirty data amplification when tracking changes to cached data at page-granularity. In this paper, we propose a fundamentally new approach for disaggregated memory systems, based on the observation that we can use local cache coherence to track applications' memory accesses transparently, without code changes, at cache-line granularity. This simple idea (1) eliminates page faults from the application critical path when accessing remote data, and (2) decouples the application memory access tracking from the virtual memory page size, enabling cache-line granularity dirty data tracking and eviction. Using this observation, we implemented a new software runtime for disaggregated memory that improves average memory access time and reduces dirty data amplification1.
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Charrier, Dominic E., Benjamin Hazelwood, Ekaterina Tutlyaeva, Michael Bader, Michael Dumbser, Andrey Kudryavtsev, Alexander Moskovsky, and Tobias Weinzierl. "Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver." International Journal of High Performance Computing Applications 33, no. 5 (April 15, 2019): 973–86. http://dx.doi.org/10.1177/1094342019842645.

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We study the performance behaviour of a seismic simulation using the ExaHyPE engine with a specific focus on memory characteristics and energy needs. ExaHyPE combines dynamically adaptive mesh refinement (AMR) with ADER-DG. It is parallelized using tasks, and it is cache efficient. AMR plus ADER-DG yields a task graph which is highly dynamic in nature and comprises both arithmetically expensive tasks and tasks which challenge the memory’s latency. The expensive tasks and thus the whole code benefit from AVX vectorization, although we suffer from memory access bursts. A frequency reduction of the chip improves the code’s energy-to-solution. Yet, it does not mitigate burst effects. The bursts’ latency penalty becomes worse once we add Intel Optane technology, increase the core count significantly or make individual, computationally heavy tasks fall out of close caches. Thread overbooking to hide away these latency penalties becomes contra-productive with noninclusive caches as it destroys the cache and vectorization character. In cases where memory-intense and computationally expensive tasks overlap, ExaHyPE’s cache-oblivious implementation nevertheless can exploit deep, noninclusive, heterogeneous memory effectively, as main memory misses arise infrequently and slow down only few cores. We thus propose that upcoming supercomputing simulation codes with dynamic, inhomogeneous task graphs are actively supported by thread runtimes in intermixing tasks of different compute character, and we propose that future hardware actively allows codes to downclock the cores running particular task types.
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Mittal, Shaily, and Nitin. "Memory Map: A Multiprocessor Cache Simulator." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.

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Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cache miss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java.
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Moon, S. M. "Increasing cache bandwidth using multiport caches for exploiting ILP in non-numerical code." IEE Proceedings - Computers and Digital Techniques 144, no. 5 (1997): 295. http://dx.doi.org/10.1049/ip-cdt:19971283.

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Ma, Ruhui, Haibing Guan, Erzhou Zhu, Yongqiang Gao, and Alei Liang. "Code cache management based on working set in dynamic binary translator." Computer Science and Information Systems 8, no. 3 (2011): 653–71. http://dx.doi.org/10.2298/csis100327022m.

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Software code cache employed to store translated or optimized codes, amortizes the overhead of dynamic binary translation via reusing of stored-altered copies of original program instructions. Though many conventional code cache managements, such as Flush, Least-Recently Used (LRU), have been applied on some classic dynamic binary translators, actually they are so unsophisticated yet unadaptable that it not only brings additional unnecessary overhead, but also wastes much cache space, since there exist several noticeable features in software code cache, unlike pages in memory. Consequently, this paper presents two novel alternative cache schemes-SCC (Static Code Cache) and DCC (Dynamic Code Cache) based on working set. In these new schemes, we utilize translation rate to judge working set. To evaluate these new replacement policies, we implement them on dynamic binary translator-CrossBit with several commonplace code cache managements. Through the experiment results based on benchmark SPECint 2000, we achieve better performance improvement and cache space utilization ratio.
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Das, Abhishek, and Nur A. Touba. "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote." Electronics 9, no. 5 (April 26, 2020): 709. http://dx.doi.org/10.3390/electronics9050709.

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Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.
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Simecek, Ivan, and Pavel Tvrdík. "A new code transformation technique for nested loops." Computer Science and Information Systems 11, no. 4 (2014): 1381–416. http://dx.doi.org/10.2298/csis131126075s.

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For good performance of every computer program, good cache utilization is crucial. In numerical linear algebra libraries, good cache utilization is achieved by explicit loop restructuring (mainly loop blocking), but it requires a complicated memory pattern behavior analysis. In this paper, we describe a new source code transformation called dynamic loop reversal that can increase temporal and spatial locality. We also describe a formal method for predicting cache behavior and evaluate results of the model accuracy by the measurements on a cache monitor. The comparisons of the numbers of measured cache misses and the numbers of cache misses estimated by the model indicate that the model is relatively accurate and can be used in practice.
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Luo, Ya Li. "Research of Adaptive Control Algorithm Based on the Cached Playing of Streaming Media." Applied Mechanics and Materials 539 (July 2014): 502–6. http://dx.doi.org/10.4028/www.scientific.net/amm.539.502.

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Aimed at the quality issues of current network streaming media playing, it manages by introducing a streaming media caching mechanism to help improve the playing effect. But the cached playing also has its own deficiencies, so here combines the adaptive control algorithm with the caching mechanism to solve this problem. It firstly introduces the streaming media service, and analyzes the transmission process of streaming media and adaptive media playing in detail; secondly analyzes the adaptive control algorithm of streaming media caching from the principle and design of reserving cache algorithm and the balance frame dropping algorithm; and finally gives the core code of the algorithm. This paper has a certain reference value to the video website developers and computer system architecture researchers.
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Heirman, Wim, Stijn Eyerman, Kristof Du Bois, and Ibrahim Hur. "Automatic Sublining for Efficient Sparse Memory Accesses." ACM Transactions on Architecture and Code Optimization 18, no. 3 (June 2021): 1–23. http://dx.doi.org/10.1145/3452141.

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Sparse memory accesses, which are scattered accesses to single elements of a large data structure, are a challenge for current processor architectures. Their lack of spatial and temporal locality and their irregularity makes caches and traditional stream prefetchers useless. Furthermore, performing standard caching and prefetching on sparse accesses wastes precious memory bandwidth and thrashes caches, deteriorating performance for regular accesses. Bypassing prefetchers and caches for sparse accesses, and fetching only a single element (e.g., 8 B) from main memory (subline access), can solve these issues. Deciding which accesses to handle as sparse accesses and which as regular cached accesses, is a challenging task, with a large potential impact on performance. Not only is performance reduced by treating sparse accesses as regular accesses, not caching accesses that do have locality also negatively impacts performance by significantly increasing their latency and bandwidth consumption. Furthermore, this decision depends on the dynamic environment, such as input set characteristics and system load, making a static decision by the programmer or compiler suboptimal. We propose the Instruction Spatial Locality Estimator ( ISLE ), a hardware detector that finds instructions that access isolated words in a sea of unused data. These sparse accesses are dynamically converted into uncached subline accesses, while keeping regular accesses cached. ISLE does not require modifying source code or binaries, and adapts automatically to a changing environment (input data, available bandwidth, etc.). We apply ISLE to a graph analytics processor running sparse graph workloads, and show that ISLE outperforms the performance of no subline accesses, manual sublining, and prior work on detecting sparse accesses.
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Dissertations / Theses on the topic "Cache codée"

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Parrinello, Emanuele. "Fundamental Limits of Shared-Cache Networks." Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS491.

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Dans le contexte des réseaux de diffusion de contenu, les avantages puissants de la combinaison du cache et de la multidiffusion codée ont été démontrés pour les réseaux où chaque utilisateur est équipé de son propre cache isolé. Cette thèse vise à fournir les principes fondamentaux des réseaux à cache partagé où la communication avec les utilisateurs est assistée par un petit ensemble de caches, chacun d'entre eux servant un nombre arbitraire d'utilisateurs. Notre modèle de cache partagé, non seulement capture les réseaux cellulaires sans fil hétérogènes où les petites stations de base assistées par cache coexistent avec une macro station de base, mais il peut également représenter un modèle pour les réseaux où les utilisateurs demandent plusieurs fichiers. Nous verrons également comment ce problème des demandes de fichiers multiples se pose dans le contexte de calcul distribué codé, où nous appliquerons les mêmes idées et techniques que celles utilisées pour les réseaux avec cache. De plus, il est bien connu que la limitation du nombre de caches à une valeur beaucoup plus petite que le nombre d'utilisateurs peut être inévitable dans des scénarios pratiques où la taille des fichiers est finie et limitée. C'est pourquoi nous pensons que l'étude des réseaux de caches partagés est d'une importance critique pour le développement des techniques de mise en cache codée
In the context of communication networks, the emergence of predictable content has brought to the fore the use of caching as a fundamental ingredient for handling the exponential growth in data volumes. This thesis aims at providing the fundamental limits of shared-cache networks where the communication to users is aided by a small set of caches. Our shared-cache model, not only captures heterogeneous wireless cellular networks, but it can also represent a model for users requesting multiple files simultaneously, and it can be used as a simple yet effective way to deal with the so-called subpacketization bottleneck of coded caching. Furthermore, we will also see how our techniques developed for caching networks can find application in the context of heterogeneous coded distributed computing
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Zhao, Hui. "High performance cache-aided downlink systems : novel algorithms and analysis." Electronic Thesis or Diss., Sorbonne université, 2022. http://www.theses.fr/2022SORUS366.

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La thèse aborde d'abord le pire goulot d'étranglement de la mise en cache codée sans fil, qui est connue pour diminuer considérablement les gains de multidiffusion assistée par cache. Nous présentons un nouveau schéma, appelé mise en cache codée agrégée, qui peut récupérer entièrement les gains de mise en cache codée en capitalisant sur les informations partagées apportées par la contrainte de taille de fichier effectivement inévitable. La thèse passe ensuite à des scénarios avec des émetteurs avec des réseaux multi-antennes. En particulier, nous considérons maintenant le scénario multi-utilisateurs assisté par cache multi-antennes, où l'émetteur multi-antennes délivre des flux de mise en cache codés, pouvant ainsi servir plusieurs utilisateurs à la fois, avec des chaînes de radio fréquences (RF) réduites. Ce faisant, la mise en cache codée peut aider un simple formateur de faisceau analogique (une seule chaîne RF), entraînant ainsi des économies considérables d'énergie et de matériel. Enfin, après avoir supprimé la limitation de la chaîne RF, la thèse étudie les performances de la technique de mise en cache codée par vecteur et révèle que cette technique peut atteindre, sous plusieurs hypothèses réalistes, une augmentation multiplicative du taux de somme par rapport à la contrepartie optimisée multi-antennes sans cache. En particulier, pour un système MIMO de liaison descendante déjà optimisé pour exploiter à la fois les gains de multiplexage et de formation de faisceaux, notre analyse répond à une question simple: quelle est l'augmentation de débit multiplicative obtenue en introduisant des caches côté récepteur de taille raisonnable ?
The thesis first addresses the worst-user bottleneck of wireless coded caching, which is known to severely diminish cache-aided multicasting gains. We present a novel scheme, called aggregated coded caching, which can fully recover the coded caching gains by capitalizing on the shared side information brought about by the effectively unavoidable file-size constraint. The thesis then transitions to scenarios with transmitters with multi-antenna arrays. In particular, we now consider the multi-antenna cache-aided multi-user scenario, where the multi-antenna transmitter delivers coded caching streams, thus being able to serve multiple users at a time, with a reduced radio frequency (RF) chains. By doing so, coded caching can assist a simple analog beamformer (only a single RF chain), thus incurring considerable power and hardware savings. Finally, after removing the RF-chain limitation, the thesis studies the performance of the vector coded caching technique, and reveals that this technique can achieve, under several realistic assumptions, a multiplicative sum-rate boost over the optimized cacheless multi-antenna counterpart. In particular, for a given downlink MIMO system already optimized to exploit both multiplexing and beamforming gains, our analysis answers a simple question: What is the multiplicative throughput boost obtained from introducing reasonably-sized receiver-side caches?
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Brunero, Federico. "Unearthing the Impact of Structure in Data and in Topology for Caching and Computing Networks." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS368.pdf.

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La mise en cache s'est avérée être un excellent moyen de réduire la charge de trafic dans les réseaux de données. Une étude de la mise en cache en théorie de l'information, connue sous le nom de mise en cache codée, a représenté une percée clé dans la compréhension de la façon dont la mémoire peut être efficacement transformée en débit de données. La mise en cache codée a également révélé le lien profond entre la mise en cache et les réseaux informatiques, qui présentent le même besoin de solutions algorithmiques novatrices pour réduire la charge de trafic. Malgré la vaste littérature, il reste quelques limitations fondamentales, dont la résolution est critique. Par exemple, il est bien connu que le gain de codage assuré par la mise en cache codée n'est pas seulement linéaire dans les ressources globales de mise en cache, mais s'avère également être le talon d'Achille de la technique dans la plupart des paramètres pratiques. Cette thèse a pour but d'améliorer et d'approfondir la compréhension du rôle clé que joue la structure, que ce soit dans les données ou dans la topologie, pour le cache et les réseaux informatiques. Premièrement, nous explorons les limites fondamentales de la mise en cache sous certains modèles de la théorie de l'information qui imposent une structure dans les données, ce qui signifie que nous supposons savoir à l'avance quelles données sont intéressantes pour qui. Deuxièmement, nous étudions les ramifications impressionnantes de la structure de la topologie des réseaux. Tout au long du manuscrit, nous montrons également comment les résultats de la mise en cache peuvent être utilisés dans le contexte de l'informatique distribuée
Caching has shown to be an excellent expedient for the purposes of reducing the traffic load in data networks. An information-theoretic study of caching, known as coded caching, represented a key breakthrough in understanding how memory can be effectively transformed into data rates. Coded caching also revealed the deep connection between caching and computing networks, which similarly show the same need for novel algorithmic solutions to reduce the traffic load. Despite the vast literature, there remain some fundamental limitations, whose resolution is critical. For instance, it is well-known that the coding gain ensured by coded caching not only is merely linear in the overall caching resources, but also turns out to be the Achilles heel of the technique in most practical settings. This thesis aims at improving and deepening the understanding of the key role that structure plays either in data or in topology for caching and computing networks. First, we explore the fundamental limits of caching under some information-theoretic models that impose structure in data, where by this we mean that we assume to know in advance what data are of interest to whom. Secondly, we investigate the impressive ramifications of having structure in network topology. Throughout the manuscript, we also show how the results in caching can be employed in the context of distributed computing
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Beg, Azam Muhammad. "Improving instruction fetch rate with code pattern cache for superscalar architecture." Diss., Mississippi State : Mississippi State University, 2005. http://library.msstate.edu/etd/show.asp?etd=etd-06202005-103032.

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Palki, Anand B. "CACHE OPTIMIZATION AND PERFORMANCE EVALUATION OF A STRUCTURED CFD CODE - GHOST." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/363.

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This research focuses on evaluating and enhancing the performance of an in-house, structured, 2D CFD code - GHOST, on modern commodity clusters. The basic philosophy of this work is to optimize the cache performance of the code by splitting up the grid into smaller blocks and carrying out the required calculations on these smaller blocks. This in turn leads to enhanced code performance on commodity clusters. Accordingly, this work presents a discussion along with a detailed description of two techniques: external and internal blocking, for data access optimization. These techniques have been tested on steady, unsteady, laminar, and turbulent test cases and the results are presented. The critical hardware parameters which influenced the code performance were identified. A detailed study investigating the effect of these parameters on the code performance was conducted and the results are presented. The modified version of the code was also ported to the current state-of-art architectures with successful results.
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Gupta, Saurabh. "PERFORMANCE EVALUATION AND OPTIMIZATION OF THE UNSTRUCTURED CFD CODE UNCLE." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/360.

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Numerous advancements made in the field of computational sciences have made CFD a viable solution to the modern day fluid dynamics problems. Progress in computer performance allows us to solve a complex flow field in practical CPU time. Commodity clusters are also gaining popularity as computational research platform for various CFD communities. This research focuses on evaluating and enhancing the performance of an in-house, unstructured, 3D CFD code on modern commodity clusters. The fundamental idea is to tune the codes to optimize the cache behavior of the node on commodity clusters to achieve enhanced code performance. Accordingly, this work presents discussion of various available techniques for data access optimization and detailed description of those which yielded improved code performance. These techniques were tested on various steady, unsteady, laminar, and turbulent test cases and the results are presented. The critical hardware parameters which influenced the code performance were identified. A detailed study investigating the effect of these parameters on the code performance was conducted and the results are presented. The successful single node improvements were also efficiently tested on parallel platform. The modified version of the code was also ported to different hardware architectures with successful results. Loop blocking is established as a predictor of code performance.
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Seyr, Luciana. "Manejo do solo e ensacamento do cacho em pomar de bananeira 'Nanicão'." Universidade Estadual de Londrina. Centro de Ciências Agrárias. Programa de Pós-Graduação em Agronomia, 2011. http://www.bibliotecadigital.uel.br/document/?code=vtls000166653.

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O Brasil é o quarto produtor mundial de banana, com uma produção anual de 6,99 milhões de toneladas. É uma fruta de grande importância econômica e social, visto que é cultivada de Norte a Sul do país, garantindo emprego, renda e alimento para milhões de brasileiros durante o ano inteiro. No Paraná é a terceira fruta mais produzida no estado, com área de 9.900 ha. A maior parte da produção brasileira é destinada ao mercado interno, visto que é a segunda fruta mais consumida no país, e também devido à baixa qualidade da maior parte do produto. Essa baixa qualidade é o reflexo da falta de tecnologia das condições em que é cultivada, desde a condução na lavoura até a colheita. Uma tecnologia já utilizada em outras culturas mas pouco difundida entre os produtores de banana é o uso de plantas de cobertura para proteção do solo contra a erosão. Esse manejo é importante principalmente na implantação do bananal, pois até o início da produção decorre um tempo de cerca de 13 meses no qual o solo fica descoberto, exposto a erosão. Outra tecnologia importante para a qualidade das frutas é o ensacamento dos cachos logo após a sua formação, permanecendo como proteção até a colheita. Apesar dessa técnica ter vantagens já comprovadas em outras condições, para o estado do Paraná não existem dados relativos ao uso do ensacamento dos cachos. Assim, o trabalho foi dividido em dois projetos, ambos realizados no norte do Paraná. O objetivo do primeiro foi avaliar os efeitos da utilização de adubação verde de inverno, no estabelecimento de um pomar de bananeiras; e o segundo foi avaliar o efeito do ensacamento de cachos de banana, e o seu custo para o agricultor.
Brazil is the fourth largest producer of bananas, with an annual production of 6.99 million tons. Banana is a fruit of great economic and social importance, since it is grown from North to South of the country, generating jobs, income and food for millions of Brazilians, throughout the year. It is the third most produced fruit of the state of Paraná, with an area of 9,900 ha. Most of the Brazilian's production is destined for the domestic market, since it is the second most consumed fruit in the country, and also due to the low quality of most of the product. Such a poor quality is due to the lack of technology of the conditions in which it is grown, from the planting to the harvest. A technology which has already been used in other crops, but it is still not well known among banana producers, is the use of cover crops for soil protection against erosion. This management is particularly important for the implementation of the banana crops, because until the beginning of production, follows a period of about 13 months in which the ground is bare, exposed to erosion. Another important technology for the quality of fruit is the bagging of bunches soon after its formation, protecting until the harvest. In spite of this technique has proven to have advantages in other conditions, for the state of Paraná there is no data concerning the use of bagging bunches. Thus, the work has been divided into two subprojects, both held in the Northern of Paraná. The objective of the first was to evaluate the effects of the use of green manure on the establishment of a banana crop. The second was to evaluate the effect of bagging bunches of bananas, and its cost to the growers.
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Kristipati, Pavan K. "Performance optimization of a structured CFD code GHOST on commodity cluster architectures /." Lexington, Ky. : [University of Kentucky Libraries], 2008. http://hdl.handle.net/10225/976.

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Thesis (M.S.)--University of Kentucky, 2008.
Title from document title page (viewed on February 3, 2009). Document formatted into pages; contains: xi, 144 p. : ill. (some col.). Includes abstract and vita. Includes bibliographical references (p. 139-143).
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Malik, Adeel. "Stochastic Coded Caching Networks : a Study of Cache-Load Imbalance and Random User Activity." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS045.pdf.

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Dans cette thèse, nous élevons la mise en cache codée de son cadre purement théorique de l'information à un cadre stochastique où la stochasticité des réseaux provient de l'hétérogénéité des comportements de demande des utilisateurs. Nos résultats soulignent que la stochasticité des réseaux assistés par cache peut conduire à la disparition des gains de la mise en cache codée. Nous déterminons l'étendue exacte du goulot d'étranglement du déséquilibre de la charge du cache codé dans les réseaux stochastiques, ce qui n'a jamais été exploré auparavant. Notre travail fournit des techniques pour atténuer l'impact de ce goulot d'étranglement pour le scénario où les associations d'état entre l'utilisateur et le cache sont restreintes par des contraintes de proximité entre les utilisateurs et les nœuds d'aide (c.-à-d. un cadre de cache partagé) ainsi que pour le scénario où les stratégies d'associations d'état entre l'utilisateur et le cache sont considérées comme un paramètre de conception (c.-à-d. un cadre contraint par la mise en sous-paquets)
In this thesis, we elevate coded caching from their purely information-theoretic framework to a stochastic setting where the stochasticity of the networks originates from the heterogeneity in users’ request behaviors. Our results highlight that stochasticity in the cache-aided networks can lead to the vanishing of the gains of coded caching. We determine the exact extent of the cache-load imbalance bottleneck of coded caching in stochastic networks, which has never been explored before. Our work provides techniques to mitigate the impact of this bottleneck for the scenario where the user-to-cache state associations are restricted by proximity constraints between users and helper nodes (i.e., shared-cache setting) as well as for the scenario where user-to-cache state associations strategies are considered, as a design parameter (i.e., subpacketization-constrained setting)
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Dias, Wanderson Roger Azevedo. "Arquitetura pdccm em hardware para compressão/descompressão de instruções em sistemas embarcados." Universidade Federal do Amazonas, 2009. http://tede.ufam.edu.br/handle/tede/2950.

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In the development of the design of embedded systems several factors must be led in account, such as: physical size, weight, mobility, energy consumption, memory, cooling, security requirements, trustiness and everything ally to a reduced cost and of easy utilization. But, on the measure that the systems become more heterogeneous they admit major complexity in its development. There are several techniques to optimize the execution time and power usage in embedded systems. One of these techniques is the code compression, however, most existing proposals focus on decompress and they assume that the code is compressed in compilation time. Therefore, this work proposes the development of an specific architecture, with its prototype in hardware (using VHDL and FPGAs), special for the process of compression/decompression code. Thus, it is proposed a technique called PDCCM (Processor Memory Cache Compressor Decompressor). The results are obtained via simulation and prototyping. In the analysis, benchmark programs such as MiBench had been used. Also a method of compression, called of MIC was considered (Middle Instruction Compression), which was compared with the traditional Huffman compression method. Therefore, in the architecture PDCCM the MIC method showed better performance in relation to the Huffman method for some programs of the MiBench analyzed that are widely used in embedded systems, resulting in 26% less of the FPGA logic elements, 71% more in the frequency of the clock MHz and in the 36% plus on the compression of instruction compared with Huffman, besides allowing the compression/decompression in time of execution.
No desenvolvimento do projeto de sistemas embarcados vários fatores têm que ser levados em conta, tais como: tamanho físico, peso, mobilidade, consumo de energia, memória, refrescância, requisitos de segurança, confiabilidade e tudo isso aliado a um custo reduzido e de fácil utilização. Porém, à medida que os sistemas tornam-se mais heterogêneos os mesmos admitem maior complexidade em seu desenvolvimento. Existem diversas técnicas para otimizar o tempo de execução e o consumo de energia em sistemas embarcados. Uma dessas técnicas é a compressão de código, não obstante, a maioria das propostas existentes focaliza na descompressão e assumem que o código é comprimido em tempo de compilação. Portanto, este trabalho propõe o desenvolvimento de uma arquitetura, com respectiva prototipação em hardware (usando VHDL e FPGAs), para o processo de compressão/descompressão de código. Assim, propõe-se a técnica denominada de PDCCM (Processor Decompressor Cache Compressor Memory). Os resultados são obtidos via simulação e prototipação. Na análise usaram-se programas do benchmark MiBench. Foi também proposto um método de compressão, denominado de MIC (Middle Instruction Compression), o qual foi comparado com o tradicional método de compressão de Huffman. Portanto, na arquitetura PDCCM o método MIC apresentou melhores desempenhos computacionais em relação ao método de Huffman para alguns programas do MiBench analisados que são muito usados em sistemas embarcados, obtendo 26% a menos dos elementos lógicos do FPGA, 71% a mais na freqüência do clock em MHz e 36% a mais na compressão das instruções comparando com o método de Huffman, além de permitir a compressão/descompressão em tempo de execução.
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Books on the topic "Cache codée"

1

The cache code. [United States]: Knowonder! Publishing, 2016.

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Bella, Arman, ed. Le code caché de votre destin. Paris: J'ai lu, 2010.

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Yu-fang, Chʻen, and United States. National Aeronautics and Space Administration., eds. The Effect of code expanding optimizations on instruction cache design. [Urbana, IL]: Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, College of Engineering, University of Illinois at Urbana-Champaign, 1991.

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Helen Foresman Spencer Museum of Art, ed. Secrets of the sacred: Empowering Buddhist images in clear, in code, and in cache. Seattle: Spencer Museum of Art in association with the University of Washington Press, 2011.

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Le code caché de Botticelli: Minerve et le Centaure, Les deux testaments. Levallois-Perret: Pépin, 2011.

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The Macintosh system fitness plan: Easy exercises to improve performance and reclaim disk space. Reading, Mass: Addison-Wesley Pub. Co., 1995.

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Takenaka, Norio. TB3186 - How to Achieve Deterministic Code Performance Using a Cortex M Cache Controller (KC). Microchip Technology Incorporated, 2018.

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James, Hillman. Le Code caché de votre destin : Prendre en main son existence. J'ai lu, 2002.

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Aiyappa, Rekha. How to Achieve Deterministic Code Performance Using a Cortex(tm)-M Cache Controller Tech Brief. Microchip Technology Incorporated, 2018.

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Hillman, James. Le code caché de votre destin : Prendre en main son existence en élevant sa conscience de soi. Robert Laffont, 1999.

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Book chapters on the topic "Cache codée"

1

Sklar, David. "Accelerating with Code Caches." In Essential PHP Tools: Modules, Extensions, and Accelerators, 297–330. Berkeley, CA: Apress, 2004. http://dx.doi.org/10.1007/978-1-4302-0714-6_13.

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Simner, Ben, Shaked Flur, Christopher Pulte, Alasdair Armstrong, Jean Pichon-Pharabod, Luc Maranget, and Peter Sewell. "ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures." In Programming Languages and Systems, 626–55. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-44914-8_23.

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AbstractComputing relies on architecture specifications to decouple hardware and software development. Historically these have been prose documents, with all the problems that entails, but research over the last ten years has developed rigorous and executable-as-test-oracle specifications of mainstream architecture instruction sets and “user-mode” concurrency, clarifying architectures and bringing them into the scope of programming-language semantics and verification. However, the system semantics, of instruction-fetch and cache maintenance, exceptions and interrupts, and address translation, remains obscure, leaving us without a solid foundation for verification of security-critical systems software.In this paper we establish a robust model for one aspect of system semantics: instruction fetch and cache maintenance for ARMv8-A. Systems code relies on executing instructions that were written by data writes, e.g. in program loading, dynamic linking, JIT compilation, debugging, and OS configuration, but hardware implementations are often highly optimised, e.g. with instruction caches, linefill buffers, out-of-order fetching, branch prediction, and instruction prefetching, which can affect programmer-observable behaviour. It is essential, both for programming and verification, to abstract from such microarchitectural details as much as possible, but no more. We explore the key architecture design questions with a series of examples, discussed in detail with senior Arm staff; capture the architectural intent in operational and axiomatic semantic models, extending previous work on “user-mode” concurrency; make these models executable as test oracles for small examples; and experimentally validate them against hardware behaviour (finding a bug in one hardware device). We thereby bring these subtle issues into the mathematical domain, clarifying the architecture and enabling future work on system software verification.
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Lin, Chun-Chieh, and Chuen-Liang Chen. "Cache Sensitive Code Arrangement for Virtual Machine." In Transactions on High-Performance Embedded Architectures and Compilers III, 24–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19448-1_2.

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Genkin, Daniel, Lev Pachmanov, Eran Tromer, and Yuval Yarom. "Drive-By Key-Extraction Cache Attacks from Portable Code." In Applied Cryptography and Network Security, 83–102. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-93387-0_5.

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Arslan, Sanem, Haluk Rahmi Topcuoglu, Mahmut Taylan Kandemir, and Oguz Tosun. "Protecting Code Regions on Asymmetrically Reliable Caches." In Architecture of Computing Systems – ARCS 2016, 375–87. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30695-7_28.

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Guha, Apala, Kim Hazelwood, and Mary Lou Soffa. "Reducing Exit Stub Memory Consumption in Code Caches." In High Performance Embedded Architectures and Compilers, 87–101. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-69338-3_7.

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Palkowski, Marek, and Wlodzimierz Bielecki. "Parallel Tiled Cache and Energy Efficient Code for Zuker’s RNA Folding." In Parallel Processing and Applied Mathematics, 25–34. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-43222-5_3.

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Palkowski, Marek, Wlodzimierz Bielecki, and Mateusz Gruzewski. "Automatic Generation of Parallel Cache-Efficient Code Implementing Zuker’s RNA Folding." In Artificial Intelligence and Soft Computing, 646–54. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-61401-0_60.

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Nikolopoulos, Dimitrios S. "Code and Data Transformations for Improving Shared Cache Performance on SMT Processors." In Lecture Notes in Computer Science, 54–69. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39707-6_5.

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Novac, O., St Vari-Kakas, F. I. Hathazi, M. Curila, and S. Curila. "Aspects Regarding the Implementation of Hsiao Code to the Cache Level of a Memory Hierarchy with Fpga Xilinx Circuits." In Advanced Techniques in Computing Sciences and Software Engineering, 539–43. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3660-5_92.

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Conference papers on the topic "Cache codée"

1

Baiocchi, José A., and Bruce R. Childers. "Heterogeneous code cache." In the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630103.

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Musoll, Enric, and Mario Nemirovsky. "A study on the performance of two-level exclusive caching." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19771.

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This work presents a study on the performance of a level-two cache configured as a victim storage for the evicted lines of the level-one cache. This two-level cache configuration, known as exclusive caching, is evaluated for a wide range of level-one and level-two sizes and associalivily degrees, and the miss ratios of both levels are compared to those of the two-level inclusive caching. Although the two-level exclusive strategy has lower miss ratios than the inclusive one by increasing the effective associativity and capacity, the replacement policy of the exclusive caching organization forces the invalidation of cnlries in the level-two cache, which reduces the benefits of having a victim level-two cache. The effect of these invalidalions on the overall performance of a level-two exclusive caching organization is evaluated. For typical two-level cache configurations in which the level-two cache is direct-mapped, the performance of the exclusive caching is as much as 60% better for code fetches and as much as 75% for data accesses.
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Aftab, Fakhra, and Muhammad Ali Ismail. "Web Ontology based multi-level CACHE Simulator." In 2017 International Conference on Communication, Computing and Digital Systems (C-CODE). IEEE, 2017. http://dx.doi.org/10.1109/c-code.2017.7918928.

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Kim, Junghoon, Inhyuk Kim, and Young Ik Eom. "Code-based cache partitioning for improving hardware cache performance." In the 6th International Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2184751.2184803.

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Bin Bao and Chen Ding. "Defensive loop tiling for shared cache." In 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO). IEEE, 2013. http://dx.doi.org/10.1109/cgo.2013.6495008.

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Roy, Probir, Shuaiwen Leon Song, Sriram Krishnamoorthy, and Xu Liu. "Lightweight detection of cache conflicts." In CGO '18: 16th Annual IEEE/ACM International Symposium on Code Generation and Optimization. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3168819.

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Xu, Chengfa, Chengcheng Li, and Bin Tang. "DSP code optimization based on cache." In 2012 International Conference on Graphic and Image Processing, edited by Zeng Zhu. SPIE, 2013. http://dx.doi.org/10.1117/12.2010893.

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Tesone, Pablo, Guillermo Polito, and Stéphane Ducasse. "Profiling code cache behaviour via events." In MPLR '21: 18th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3475738.3480720.

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Falk, Heiko, and Helena Kotthaus. "WCET-driven cache-aware code positioning." In the 14th international conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2038698.2038722.

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Moreira, Francis Birck, Eduardo Henrique Molina da Cruz, Marco Antonio Zanata Alves, and Philippe Olivier Alexandre Navaux. "Scratchpad Memories for Parallel Applications in Multi-core Architectures." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2011. http://dx.doi.org/10.5753/wscad.2011.17263.

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Scratchpad memories are largely used in embedded processors due to their reduced energy consumption and area compared to traditional cache memories. In multi-core architectures, these memories are an interesting solution for the storage of shared data and data which is used intensively. However, these memories present some challenges, such as the need for manual choice of the content. Furthermore, different sizes of scratchpad memories result in the need to modify the source code of the application. In this article, we propose the use of a scratchpad memory in a multi-core architecture which alleviates these disadvantages. We added the scratchpad to an architecture consisting of 4 cores, reducing the size of L2 cache in order to give chip area to the scratchpad memory. We evaluated our proposed design by executing the NAS Parallel Benchmark (NPB) applications in a simulator. We improved performance by up to 45% compared to the base architecture, reducing cache invalidations by up to 85%.
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