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1
Lee, Hyun Ho. "A thin film transistor driven microchannel device." Texas A&M University, 2004. http://hdl.handle.net/1969.1/1439.
Full textAbstract:
Novel electrophoresis devices for protein and DNA separation and identification
have been presented and studied. The new device utilizes a contact resistance change
detection method to identify protein and DNA in situ. The devices were prepared with a
microelectronic micromechanical system (MEMS) fabrication method. Three model
proteins and six DNA fragments were separated by polyacrylamide gel microchannel
electrophoresis and surface electrophoresis. The detection of the proteins or DNA
fragments was accomplished using the contact resistance increase of the detection
electrode due to adsorption of the separated biomolecules. Key factors for the success of
these devices were the optimization of fabrication process and the enhancement of
detection efficiency of the devices. Parameters, such as microchannel configuration, size
of electrode, and affinity of protein or polyacrylamide gel to the microchannel sidewall
and bottom surface were explored in detail. For DNA analysis, the affinity to the bottom
surface of the channel was critical. The surface modification method was used to
enhance the efficiency of the microchannel surface electrophoresis device. The
adsorption of channel separated protein and DNA on the detection electrode was
confirmed with the electron spectroscopy for chemical analysis (ESCA) method. The
electrical current (I) from the protein microchannel electrophoresis was usually noisy
and fluctuated at the early stage of the electrophoresis process. In order to remove the
current perturbation, an amorphous silicon (a-Si:H) thin film transistor (TFT) was
connected to the microchannel device. The self-aligned a-Si:H TFT was fabricated with
a two-photomask process. The result shows that the attachment of the TFT successfully
suppressed the current fluctuation of the microchannel electrophoresis process. In
summary, protein and DNA samples were effectively separated and detected with the
novel TFT-driven or surface microchannel electrophoresis device.
2
Bu, Ian Yi-Yu. "Plasma nitrogenation for thin film transistor applications." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.615998.
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3
Aschenbeck, Jens. "Novel amorphous silicon thin film transistor structures." Thesis, University of Cambridge, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.620172.
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4
Islam, Mujahid-ul. "Polysilicon thin film transistor systems and circuits." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.613019.
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5
Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.
Full textAbstract:
n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs)
with copper electrodes prepared by a novel plasma etching process have been fabricated
and studied. Their characteristics are similar to those of TFTs with molybdenum
electrodes. The reliability was examined by extended high-temperature annealing and
gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this
plasma etching method.
Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different
experimental stages have been measured. The gamma-ray irradiation damaged bulk
films and interfaces and caused the shift of the transfer characteristics to the positive
voltage direction. The field effect mobility, on/off current ratio, and interface state
density of the TFTs were deteriorated by the irradiation process. Thermal annealing
almost restored the original state's characteristics.
Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a-
Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The
hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large
charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been
detected. Charge storage is related to properties of the embedded a-Si:H layer and its
interfaces in the gate dielectric structure. Discharge efficiencies with various methods,
i.e., thermal annealing, negative gate bias, and light exposure, separately, were
investigated. The charge storage and discharge efficiency decrease with the increase of
the drain voltage under a dynamic operation condition. Optimum operating temperatures
are low temperature for storage and higher temperature for discharge.
a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film
embedded in the silicon nitride gate dielectric stack has been characterized for memory
functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage
curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded
a-Si:H layer had a charge storage capacity six times that of the capacitor without the
embedded layer. The nonvolatile memory device has potential for low temperature
circuit applications.
6
Xiong, Zhibin. "Novel scaled-down poly-Si thin-film transistor devices and technologies /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20XIONG.
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7
Vorona, Mikhail. "Anthracene-Based Molecules for Organic Thin-Film Transistor Integration." Thesis, Université d'Ottawa / University of Ottawa, 2020. http://hdl.handle.net/10393/41536.
Full textAbstract:
Organic electronics are devices based on semiconductors derived from carbon based molecules and polymers. These devices can be made flexible, lightweight and potentially inexpensive with the development of economies of scale. Specific examples of organic electronics include organic thin-film transistors (OTFTs), organic light-emitting diodes (OLEDs) and organic photovoltaic (OPVs). Anthracene-based semiconductors are materials that have generated great interest primarily because of their structural planarity, potential for strong intermolecular interactions, air stability and ideal frontier molecular orbital energy levels. In this thesis, we detail two publications that examined functionalized anthracene molecules integrated into OTFTs, along with their thermal, electrochemical and optical properties. We started by examining seven novel 9,10-anthracene-based molecules. It was found that functionalization of the 9,10-positions with different phenyl derivatives resulted in negligible variation in the optical properties with minor (±0.10 eV) changes in electrochemical behaviour, while the choice of phenyl derivative greatly affected the thermal stability whereby the decomposition temperatures (Td) varied by as much as 128 °C between certain functionalized derivatives. The findings suggested that functionalization of the 9,10-position of anthracene leads to an effective handle for tuning of the thermal stability while having little to no effect on the optical properties and the solid-state arrangement. We continued with the synthesis of several novel anthracene derivatives which were di-substituted at the 2,6-positions. It was found that 2,6-functionalization with various fluorinated phenyl derivatives led to negligible changes in the optical behaviour while influencing the electrochemical properties (±0.10 eV). Furthermore, the choice of fluorinated phenyl moiety had noticeable effects on melting point and thermal stability (ΔTm < 55 °C and ΔTd < 65 °C). OTFTs were fabricated and characterized using the 2,6-anthracene derivatives as the semiconducting layer. The addition of fluorine groups on the phenyl groups led to a transition from p-type behaviour to n-type behaviour in BGBC OTFTs. The results indicated that the choice of functional group as well as its functionalization location, at the 9,10- and 2,6-positions, can act as powerful handles to engineer high performance OTFTs.
8
Chow, Thomas. "A conduction model for intrinsic polycrystalline silicon thin film transistor based on discrete grains /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20CHOW.
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9
Hein, Moritz. "Organic Thin-Film Transistors." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-167894.
Full textAbstract:
Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose.
In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K.
From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor.
However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.
10
Herlogsson, Lars. "Electrolyte-Gated Organic Thin-Film Transistors." Doctoral thesis, Linköpings universitet, Institutionen för teknik och naturvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69636.
Full textAbstract:
There has been a remarkable progress in the development of organic electronic materials since the discovery of conducting polymers more than three decades ago. Many of these materials can be processed from solution, in the form as inks. This allows for using traditional high-volume printing techniques for manufacturing of organic electronic devices on various flexible surfaces at low cost. Many of the envisioned applications will use printed batteries, organic solar cells or electromagnetic coupling for powering. This requires that the included devices are power efficient and can operate at low voltages. This thesis is focused on organic thin-film transistors that employ electrolytes as gate insulators. The high capacitance of the electrolyte layers allows the transistors to operate at very low voltages, at only 1 V. Polyanion-gated p-channel transistors and polycation-gated n-channel transistors are demonstrated. The mobile ions in the respective polyelectrolyte are attracted towards the gate electrode during transistor operation, while the polymer ions create a stable interface with the charged semiconductor channel. This suppresses electrochemical doping of the semiconductor bulk, which enables the transistors to fully operate in the field-effect mode. As a result, the transistors display relatively fast switching (≤ 100 µs). Interestingly, the switching speed of the transistors saturates as the channel length is reduced. This deviation from the downscaling rule is explained by that the ionic relaxation in the electrolyte limits the channel formation rather than the electronic transport in the semiconductor. Moreover, both unipolar and complementary integrated circuits based on polyelectrolyte-gated transistors are demonstrated. The complementary circuits operate at supply voltages down to 0.2 V, have a static power consumption of less than 2.5 nW per gate and display signal propagation delays down to 0.26 ms per stage. Hence, polyelectrolyte-gated circuits hold great promise for printed electronics applications driven by low-voltage and low-capacity power sources.
11
Ma, Qinghua. "ITO/a-Si:H photodiode and thin film transistor for optical imaging." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0027/NQ51211.pdf.
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12
Jin, Yoonsil. "Toxic gas sensors using thin film transistor platform at low temperature." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/46669.
Full textAbstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.Includes bibliographical references (leaves [71-73]).
Semiconducting metal-oxides such as SnO₂, TiO₂, ZnO and WO₃ are commonly used for gas sensing in the form of thin film resistors (TFRs) given their high sensitivity to many vapor species, simple construction and capability for miniaturization. Furthermore, they are generally more stable than polymer-based gas sensors. However, unlike polymers, metal oxide gas sensors must typically be operated between 200-400°C to insure rapid kinetics. Another problem impacting TFR performance and reproducibility is related to poorly understood substrate-semiconductor film interactions. Space charges at this heterojunction are believed to influence chemisorption on the semiconductor-gas interface, but unfortunately, in an unpredictable manner. In this study, the feasibility of employing illumination and the thin film transistor (TFT) platform as a means of reducing operation temperature was investigated on ZnO based TFTs for gas sensors applications. Response to NO₂ is observed at significantly reduced temperature. Photoconductivity measurements, performed as a function of temperature on ZnO based TFRs, indicate that this results in a photon-induced desorption process. Also, transient changes in TFT channel conductance and transistor threshold voltage are obtained with application of gate bias, suggesting that TFTs offer additional control over chemisorption at the semiconductor-gas interface.
by Yoonsil Jin.
S.M.
13
He, David Da. "An organic thin-film transistor circuit for large-area temperature-sensing." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45833.
Full textAbstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (leaves 81-84).
This thesis explores the application of organic thin-film transistors (OTFTs) for temperature-sensing. The goal of this work is twofold: the understanding of the OTFT's electrical characteristics' temperature dependence, and the creation of OTFT temperature-sensing circuits. We find that OTFTs have temperature-dependent current-voltage (I-V) characteristics that are determined by trap states inside the bandgap. Based on this understanding, a DC OTFT circuit model is developed which accurately fits the measured I-V data in all regions of device operation and at different temperatures. Using this model, we design and fabricate two OTFT temperature-sensing circuits. The first circuit achieves a responsivity of 22mV/°C with 12nW of power dissipation, but has a nonlinear temperature response that is dependent on threshold voltage shifts. The second circuit achieves a responsivity of 5.9mV/°C with 88nW of power dissipation, and has a highly linear temperature response that is tolerant of threshold voltage shifts. Both circuits exceed silicon temperature sensors' typical temperature responsivity of 0.5 - 4mrV/C while dissipating less power. These traits, along with the OTFT's ability to be fabricated on large-area and flexible substrates, allow OTFT temperature sensors to be used in both existing and new application environments.
by David Da He.
S.M.
14
Rex, A. "Interplay between the Mechanics of Flexible Substrates and Performance of Thin Film Transistors: Role of Buckled Geometry." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/5319.
Full textAbstract:
Buckled Thin Film Transistor (TFT) resulting from the stress induced instability
of thin films realized on a
exible substrate can behave di erently than that of
a planar device. The aim of this thesis is twofold: To understand the in
uence
of the buckled geometry on the device physics of TFT & How can we use this
characteristics to design circuits area e ciently. The study comprises of theoretical
estimates, simulations and experimental investgations.
Theoretical estimates of the buckled geometry's in
uence on the two important
variables: unit area gate capacitance Ci and, electrostatic potential ' are presented
as a function of the interface curvature. Simulation results to elucidate these
estimations are presented. As per the classification followed, the applied stress
is fundamental towards the naturally buckled geometry. Drain to source current
(IDS) of the Naturally Buckled TFTs (NBTs), as per the theory, depends on the
angle between the direction of applied stress and channel. While in the case of the
stress perpendicular to the channel, integral of the Ci curve within the wavelength
of the NBTs is the governing factor, for stress parallel case, integral of the invese
Ci is the governing factor. Simulation results presented in this regards are in
agreement with this theory. Extreme assymetricity in the buckling, which is the
case of pure bending is also studied. While for the case of the pure bending
leading to the field amplification at the channel region, increment in the IDS is
expected, for the attenuation case, as per the theory IDS decreases. Simulation
results presented in this regards are in agreement with the theory.
As per the classification followed, realizing non-planar gate geometry, on top of
which TFTs are fabricated is fundamental towards the Artificially Buckled TFTs
(ABTs). In case of ABTs, as per the theory, the Ci profile becomes a function of
Pitch and Height of the gate geometry's unit element. Such feature of ABTs can
in
uence the effective layout area of the ABTs. Derived transconductances from
the simulated IV characteristics are analyzed to elucidate this e ect. Simulated
Voltage Transfer Characteristics of the n-channel only CSAs with the ABTs as a
load device is in agreemnet with the theory.
Experimental results to verify the in
uence of artificially buckled geometry on
the TFT and amplifier design is presented.
15
Chen, Yi-Ming, and 陳逸銘. "Organic thin film transistor." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/92956758326867871048.
Full textAbstract:
碩士國立臺灣大學
光電工程學研究所
95
Organic thin film transistors (OTFTs) have attracted much attention because of the advantages of low-cost, large-area and flexible-substrate capability which can be widely used in the applications such as radio frequency identification tags, electronic papers, and flexible display. Although a lot of research groups focus on organic material synthesis, a self sustained electrical model for such devices is far from perfect right now. To understand the electrochemistry of organic materials and find the solution of stabilities of organic materials, a complete modeling and research on DC and AC is needed. In this paper, we started our simulations from the basic current-voltage equations of a semiconductor metal-oxide-semiconductor (MOS) device to build the DC modeling and extract the parameters. Comparing the differences between the organic and semiconductor devices, we found that, in an OTFT, the current-voltage characteristics are quite different from that in a semiconductor-MOS, and we developed the petacene grain size model to explain the experiment. And we perform DC stress to investigate the stability of organic material. And we try to investigate the variations of physical and modeling parameters that respond to AC current changes. Therefore, starting from small signal and large signal AC models, we built up the macroscopic AC response models from carrier point of view, which is essential to AC modeling since the polystalline property of OTFTs hasn''t been considered in AC model previously. Furthermore, we perform AC stress test to study the device failure mechanism. The results will be helpful to identify better material and device structures. Finally, we carry out the quasi-stable C-V test in a pentacene OTFT. The quais-stable C-V is a low frequency test to realize carrier transport behaviors under different applied voltages, swing durations and gate channel sizes. Our results indicate that carrier trap and de-trap process will affect the C-V profiles under different stress.
16
Li, Flora. "Organic Thin Film Transistor Integration." Thesis, 2008. http://hdl.handle.net/10012/3745.
Full textAbstract:
This thesis examines strategies to exploit existing materials and techniques to advance organic thin film transistor (OTFT) technology in device performance, device manufacture, and device integration. To enhance device performance, optimization of plasma enhanced chemical vapor deposited (PECVD) gate dielectric thin film and investigation of interface engineering methodologies are explored. To advance device manufacture, OTFT fabrication strategies are developed to enable organic circuit integration. Progress in device integration is achieved through demonstration of OTFT integration into functional circuits for applications such as active-matrix displays and radio frequency identification (RFID) tags.
OTFT integration schemes featuring a tailored OTFT-compatible photolithography process and a hybrid photolithography-inkjet printing process are developed. They enable the fabrication of fully-patterned and fully-encapsulated OTFTs and circuits. Research on improving device performance of bottom-gate bottom-contact poly(3,3'''-dialkyl-quarter-thiophene) (PQT-12) OTFTs on PECVD silicon nitride (SiNx) gate dielectric leads to the following key conclusions: (a) increasing silicon content in SiNx gate dielectric leads to enhancement in field-effect mobility and on/off current ratio; (b) surface treatment of SiNx gate dielectric with a combination of O2 plasma and octyltrichlorosilane (OTS) self-assembled monolayer (SAM) delivers the best OTFT performance; (c) an optimal O2 plasma treatment duration exists for attaining highest field-effect mobility and is linked to a “turn-around” effect; and (d) surface treatment of the gold (Au) source/drain contacts by 1-octanethiol SAM limits mobility and should be omitted. There is a strong correlation between the electrical characteristics and the interfacial characteristics of OTFTs. In particular, the device mobility is influenced by the interplay of various interfacial mechanisms, including surface energy, surface roughness, and chemical composition. Finally, the collective knowledge from these investigations facilitates the integration of OTFTs into organic circuits, which is expected to contribute to the development of new generation of all-organic displays for communication devices and other pertinent applications. A major outcome of this work is that it provides an economical means for organic transistor and circuit integration, by enabling use of the well-established PECVD infrastructure, yet not compromising the performance of electronics.
17
Esmaeili, Rad Mohammad Reza. "Nanocrystalline Silicon Thin Film Transistor." Thesis, 2008. http://hdl.handle.net/10012/3757.
Full textAbstract:
Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that
a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure.
The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface.
The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the
a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained.
The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.
18
Yu, Ching Ming, and 俞正明. "Fabrication of Thin Film Transistor." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/56182264133731033306.
Full textAbstract:
碩士國立中興大學
材料工程學研究所
85
In this thesis, inverted staggered amorphous silicon thin film transistors (TFTs) were fabricated on the 10×10 cm2glass substrate by a totally wet etching process. The thesis can be divided into two main parts : one is the fabrication of a- SiNx:H films. The refractive index, dark conductivity and the bonding ratio N-H/Si-H of a-SiNx:H filmswere analyzed to find out the influence of deposition conditions.The results of analysis were shown as follows.N-H/Si-H ratio : (1)Under larger NH3:SiH4 gas ratio, the value is larger, (2)Under larger power density, the value is larger. Dark conductivity : There is no apparent relationship between the dark conductivityand the variations of deposition conditions. Refractive index : Under larger NH3:SiH4 gas ratio, the value is smaller . The other part of this thesis is the fabrication of the a-Si:H thin film transistors including mask design、photolithography and fabrication process . Different etching solutions were tested to find out the suitable solution and etching rate for each layer of TFT. Three masks were used to fabricate TFT devices. The Ion/Ioff of device was less than 100 and the threshold voltage(Vth) was about -1V.
19
Lee, Chih-Hung, and 李至弘. "The Study of HfZnO Thin Film and Thin Film Transistor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/03339234857014398090.
Full textAbstract:
博士國立臺灣大學
應用力學研究所
103
This thesis reports the properties of the HfxZn1-xO thin films deposited by rf-sputtering and sol-gel method. The sputter-deposited HfxZn1-xO thin films were then used as the active layers of thin film transistors (TFTs) on the glass substrates. The sputtering HfxZn1-xO thin films with various Hf contents are sputter-deposited on glass substrates from HfxZn1-xO (x = 0, 2.5, 5, 7.5 and 10 at%) targets at room temperature. The incorporation of Hf in the ZnO film leads to the amorphization of the materials. As the annealing temperature increases, the built-in stresses in the thin films are relaxed. The optical bandgap increases with the Hf content, yet it decreases with the annealing temperature. This can be attributed to the alteration of strain (stress) status in the films and the slight grain growth. Hf doping increases the resistivity of ZnO owing to the disorder of the material structure and the higher bandgap. The electrical properties of the rf-sputtered HfxZn1-xO/ZnO heterostructures were also investigated. A highly conductive interface is formed at the interface between HfxZn1-xO and ZnO thin films as the ZnO annealing temperature exceeds 500°C, leading to the apparent decrease of the electrical resistance. The resistance decreases with an increase of either thickness or Hf content of the HfxZn1-xO capping layer. The second part of thesis reports the characterization of sol-gel derived HfxZn1-xO thin films deposited on glass substrates. The incorporation of Hf in the films increases the crystallinity of the as-deposited films. The bandgap increases with the Hf content but reduces after thermal annealing because of the relaxation of built-in stress, atomic rearrangement, and precipitation of HfO2. The resistivity of ZnO decreases as the annealing temperature increases owing to the improvement of crystallinity and reduction of defect densities. On the contrary, the resistivity of HfxZn1-xO thin films increases with the annealing temperature owing to the precipitation of HfO2 and reduction of oxygen vacancies. The electrical properties of sol-gel derived Hf0.1Zn0.9O/ZnO and ZnO/HfxZn1-xO heterostructures were also investigated. The amount of resistance reduction increases as the bottom layer annealing temperature increases. According to the XPS result, the incorporation of Hf in the films improves the Zn-O bonding state, and thermal annealing enhances metal-oxygen bonding. Sputtered HfxZn1-xO (x=0.005, 0.01 and 0.025) is used as the channel layer of the bottom-gate TFT with MgO dielectric layer deposited by e-beam evaporation. The Hf0.005Zn0.995O shows the better device performance. The Vth, S.S., μlin and on-off ratio values for the Hf0.005Zn0.995O TFT were 4.1 V, 1.66 V/dec, 9.0 cm2/Vs and >107. In the top gate TFTs, Hf0.1Zn0.9O/ZnO hetertstructure is used as the channel of TFTs. The multilayer enhances the electrical properties of TFTs. The Vth, S.S., and μlin, values for the Hf0.1Zn0.9O/ZnO TFT were 0.38 V, 1.79 V/dec, and 158 cm2/Vs.
20
Chien, Yu-Hsin Chang, and 張簡聿心. "Analysis and Application for Transparent Oxide Thin Film Transistor and Organic Thin Film Transistor Type Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/tnh8ge.
Full textAbstract:
碩士國立中央大學
化學工程與材料工程學系
106
The research can be divided into two parts. The first one is Solution-processable low-voltage driven transparent oxide thin film transistor. The second is Donor Acceptor and linkage effect for transistor type memory devices application. In the first part, we use ITO glass as substrate and gate. Then, about 120 nm TSO thin film was deposited on ITO glass. Its capacitance is approximately 172 nF cm-2, dielectric constant is 27.5. The TSO/ITO glass substrate was preheated to 400 oC, and then 65 nm ZnO semiconductor layer was deposited on it by using spray coating method, followed by annealing at 400 oC for 1 min. The elecrtrode was fabricated by two steps. Firstly, we deposited AgNWs through a shadow mask by using spray coating method. Then, we deposited another PEDOT:PSS layer through the shadow mask on the same position as we deposited AgNWs. The operation voltage of the thin film transistor is only 3 V, on/off current ratio 105, threshold voltage 0.36 V, subthreshold swing 815 mv dec-1, electron mobility 9.1 cm2 V-1 s-1. The results show the thin film transistor possessed well electrical characteristics and was stable under ambient air while doing experiment. In the second part, we use SiO2/Si as substrate and deposited electret by using spin coating method. Electret layer is fabricated for the purpose of storing holes or electrons. In this work, the electrets are TPA-PIS (Triphenylamine Sulfonyl-containing polyimide)、TPA-PES (Triphenylamine Sulfonyl-containing polyether) and TPA-PETS (Triphenylamine Sulfonyl-containing polyester), respectively. By researching and analyzing the electric characteristics and structure effects, we can be told that transistor type memory devices based on the three materials are all volatile memory. Yet, different structure, energy level or other relative characteristics can influent electric characteristics of transistor type memory. Therefore, we can learn knowledge by analyzing the relationships between structure and its effects on memory characteristics.
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Yang, Neng-Jye, and 楊能傑. "Studies on polymer thin film transistor." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/73628553819444921085.
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Wang, Min-Chuan, and 王敏全. "Novel Technology of Thin-Film Transistor." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/52513437935891706052.
Full textAbstract:
博士國立清華大學
材料科學工程學系
95
Due to the RC propagation line delay for the fabrication of large-area and high-resolution active- matrix liquid-crystal displays (AM-LCD’s), the low resistivity metal Cu was introduced to reduce the RC propagation line delay .The feasibility of using Cu/CuMg as the gate electrode and source/drain metal for a-Si:H thin film transistors (TFTs) has been investigated. The issue of adhesion with the glass substrates and the n+-a-Si layer has been overcome by introducing the Cu/CuMg alloy. Furthermore, a wet etching process of Cu-based metal has been proposed by using the copper etchant in the conventional printed circuit boards (PCBs). The suppression of Schottky leakage current in metal/a-Si:H structure was also observed in the island-in a-Si:H TFT. The main objectives for flat panel display application are to enhance the field effect mobility and to reduce the off-state leakage current under back light illumination. In addition to reduce the RC propagation line delay for the fabrication of large-area and high-resolution active- matrix liquid-crystal displays (AM-LCD’s), the reduction of the TFT off-state leakage current under back light illumination is also an important issue for keeping signal. For effectively reducing the off-state signal loss resulted from the a-Si:H TFTs photo leakage current, the photo leakage current (IPLC) characteristic of F incorporated a-Si:H thin film transistor is smaller than that of conventional a-Si:H TFTs in the density of states (DOS) limited region, stemmed from the higher recombination centers present in a-Si:H(:F) material. However, the higher IPLC is observed in the hole conduction region, resulted from the larger Ea in the a-Si:H(:F) TFTs. The a-Si:H TFTs with the use of ITO as source-drain metal have been also fabricated. A remarkable transformation in photo leakage current has been observed under the backlight illumination. The photo generation holes blocked in the Schottky barrier could be effectively resulted in the different characteristic of photo leakage current. The numerous trap states existed in a-Si layer seriously strict the transporting of carriers The application of microcrystalline silicon thin film transistors (μ-Si:H TFTs) is attractive due to the higher mobility. On the other hand, the ohmic-contact characteristic of the μ-Si:H was also important for the application of μ-Si:H TFTs. The feasibility of using CuMg as source/drain metal electrodes for n+-doped-layer free µ-Si:H TFTs has been investigated. The ohmic-contact characteristic has been achieved by using the CuMg alloy as source/drain metal. The proposed µ-Si:H TFT has shown the similar electrical characteristic with the µ-Si:H TFT with n+-doped layer. For flexible display application, display panels are required to sustain a certain degree of bending. The effect of mechanical strain on the performance of a-Si:H TFTs with different channel lengths was studied under uniaxial compressive and tensile strain applied parallel to the TFT source-drain current path. The source/drain parasitic resistance, and channel sheet conductance were extracted to explain the device performance under mechanical strain. These results indicate that the compressive bending leads to a significant decrease (~16%) in the source-drain parasitic resistance. The channel sheet conductance has shown a 6% variation under mechanical bending. The variation under mechanical bending strain is originated from the evolution of defect state density in a-Si:H channel material. Furthermore, the instability of a-Si:H TFTs under uniaxial strain has been studied. Compared to the effect of tensile bias stress, larger threshold voltage (Vth) shift is observed under compressive bias stress. However, the Vth shift of devices on the re-flattened substrate is larger after tensile strain than that of compressive strain. The defeat diminished effect of tensile situation is decreased after re-flattening the device. Therefore, after re-flattening substrate the Vth shift resulted from tensile bias stress is larger than that of compressive one.
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Heineck, Daniel Philip. "Zinc tin oxide thin-film transistor circuits." Thesis, 2008. http://hdl.handle.net/1957/9975.
Full textAbstract:
The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice due to its low cost and ability to be deposited via DC reactive sputtering. In the absence of an acceptable ZTO wet etch process, a plasma-etching process using Ar/CH₄ is developed for both 1:1 and 2:1 ZTO compositions. An Ar/CH₄ plasma etch process is also designed for indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). Ar/CH₄ dry etches have excellent selectivity with respect to SiO₂, providing a route for obtaining patterned ZTO channels. A critical asset of ZTO process integration involves removing polymer deposits after ZTO etching without active layer damage.
A ZTO process is developed for the fabrication of integrated circuits which use ZTO channel enhancement-mode TFTs. Such ZTO TFTs exhibit incremental and average mobilities of 23 and 18 cm²V⁻¹s⁻¹, respectively, turn-on voltages approximately 0 to 1.5 V and subthreshold swings below 0.5 V/dec when annealed in air at 400 °C for 1 hour. Several types of ZTO TFT circuits are realized for the first time. Despite large parasitic capacitances due to large gate-source and gate-drain overlaps, AC/DC rectifiers are fabricated and found to operate in the MHz range. Thus, they are usable for RFID and other equivalent-speed applications. Finally, a ZTO process for simultaneously fabricating both enhancement-mode and depletion-mode TFTs on a single substrate using a single target and anneal step is developed. This dual-channel process is used to build a high-gain two-transistor enhancement/depletion inverter. At a rail voltage of 10 V, this inverter has a gain of 10.6 V/V, the highest yet reported for an AOS-based inverter. This E/D inverter is an important new functional block which will enable the realization of more complex digital logic circuits.Graduation date: 2009
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Rost, Timothy Alan. "A thin film lithium niobate ferroelectric transistor." Thesis, 1991. http://hdl.handle.net/1911/16480.
Full textAbstract:
The incorporation of a thin film of LiNbO$\sb3$ in a conventional MOS (metal-oxide-semiconductor) structure gives the possibility of two fundamentally different types of computer memory architectures. One, based on ferroelectric switching, involves the reorganization of charge in the transistor channel to compensate for the change in surface polarization. Another, based on the bulk photovoltaic effect, creates a change in the threshold of the transistor when exposed to incident light. With the use of a molybdenum liftoff process, such ferroelectric transistors have been realized. The properties of these transistors have been measured before and after exposure to laser illumination, and before and after the application of voltage pulses.
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WU, MENG-YUE, and 吳孟岳. "Study of a-Si:H thin film transistor." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/65655624416647470138.
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蔡尚公. "Thin Film Transistor measurement by transient current." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/56915664649493885048.
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Chang, Chao-Yuan, and 張朝淵. "Study of Tungsten-Diselenide Thin Film Transistor." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/51164854459632505577.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
102
In 2004, the renowned 2D material, graphene, was successfully produced by Andre Geim and Konstantin Novoselov, the laureates of 2010 Nobel Prize in Physic. This amazing achievement has proved that the 2-D structured monolayer is not only a scientific hypothesis but a truly existing material system. It also inspired the explosive research on graphene and other 2-D materials, for example, Transition-Metal- Dichalcogenides (TMD). From bulk to few layers, TMD has shown promising potentials in electronic and optical devices. When it comes to Integrated Circuits (IC), large-area and high-quality TMD thin films are required. Therefore, we have coworked with the group led by Dr. Lance Li, Institute of Atomic and Molecular Sciences, Academia Sinica. The WSe2 film is produced using a CVD method at Academia Sinica. Then we produce top-gate WSe2 Thin Film Transistor (TFT) in Nano Facility Center, National Chiao Tung University and National Nano Device Laboratories. We have already constructed the basic process flow of making top-gate WSe2 TFT with reasonable characteristics. In this thesis, I will show our experiment results, including statistics of device parameters. We focus particularly on the different gate oxide deposition methods and their impacts on the device performance. The 150℃ low-temperature ALD deposited HfO2 is the best in our devices, and the SiO2/high-k dielectric bilayer oxide also improve yield but limited device performance. Although there are still many problems to be solved before realizing high-performance devices, the current study serves as a good starting point for future research on WSe2 TFT.
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Liao, Jia Hong, and 廖家鴻. "Fluorinated Graphene Apply on Thin Film Transistor." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/96395666842423319127.
Full textAbstract:
碩士長庚大學
電子工程學系
101
Graphene, it is a 2D material which the film is composed of carbon atoms in a hexagonal honeycomb lattice. graphene is also triggered a lively academic attention since it seperated from graphite. Until now, graphene is still the hotest research topic. Firt part of this article is the synthesis of graphene by chemical vapor deposition ,next analysis by Raman spectrum, we made the monolayer and defect free graphene. Next, we put the sample to the CF4 plasma system to fluorination, with fluorine atom bonded to carbon atom(from 27.4 to 5.6), to the effect of the insulation(sheet resistance from 1.6 K ~1 M ohm/sq). we control the fluorinated graphene's conduction(semi-metal -> semiconductor -> insulator). Finally we concluded the bandgap of grapheme can be tuned to 2.9eV. Second part of this article will combine the method of gold bufflayer , we can control the degree of fluorination by one-step fluorination. With the electrical measurement, we can know the change of current's on/off ratio is 10.1,it’s 3-fold higher than that of the device made from pristine graphene. The third part come up with the fluorination of multilayer grapheme,and use the multilayer graphene as insulator,finally, we hope to creat a graphene transistor.
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Chen, Wei-Hao, and 陳韋皓. "Poly-Si Nanowire Junctionless Thin Film Transistor on Nitride Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/85654305503152599493.
Full textAbstract:
碩士國立中興大學
光電工程研究所
104
To continuously reduce the transistor’s size with higher device’s performance is necessary, when poly-Si thin-film transistors (TFTs) are further applied to system-on-panel (SOP) and three-dimensional integrated circuits (3-D ICs). In recent years, many studies have paid attentions to junctionless TFT’s, not only planer TFT’s structure is fabricated but also multiple-gate junctionless nanowire transistors are proposed and showing good device’s performances. In this paper, we focus on the fabrication of nanowire junctionless thin film transistor on nitride film, and by this fabrication we can get the better process in nanowire structure. As well-known, the gate-all-around (GAA) and double gate structures can obtain the great characteristics in TFTs. But there are some problems in the fabricating procedures. For the GAA structure, the nanowire channels must be suspended in the air, and the suspended nanowire channels might be subjected to more physical damages, and more chemical injure in the cleaning process of wet bench. For the double gate structure, it can achieve good characteristics without suspended nanowire channels, but it needs extra fabricating steps to form a bottom gate before fabricating the nanowire channels, Therefore the fabrication of double gate TFTs is more complicated, and the fabrication cost is also higher than the conventionl ones. In this paper, the nanowire channels are fabricated on the nitride film to prevent from the physical and chemical damages during the fabricating procedures. The junctionless poly-Si TFTs with triple-gate and multiple nanowires structures exhibit good electrical characteristics without complex processes and higher cost.And the yield of the proposed TFTs can be improved to 92%, as compared to that of wet oxide film TFT only being 44%.
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Sundholm, Eric Steven. "Nontraditional amorphous oxide semiconductor thin-film transistor fabrication." Thesis, 2012. http://hdl.handle.net/1957/34019.
Full textAbstract:
Fabrication techniques and process integration considerations for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this dissertation. Within this theme three primary areas of focus are pursued.
The first focus involves formulating a general framework for assessing passivation. Avoiding formation of an undesirable backside accumulation layer in an AOS bottom-gate TFT is accomplished by (i) choosing a passivation layer in which the charge neutrality level is aligned with (ideal case) or higher in energy than that of the semiconductor channel layer charge neutrality level, and (ii) depositing the passivation
layer in such a manner that a negligible density of oxygen vacancies are present at the channel-passivation layer interface. Two AOS TFT passivation schemes are explored. Sputter-deposited zinc tin silicon oxide (ZTSO) appears promising for suppressing
the effects of negative bias illumination stress (NBIS) with respect to ZTO and IGZO TFTs. Solution-deposited silicon dioxide is used as a barrier layer to subsequent PECVD silicon dioxide deposition, yielding ZTO TFT transfer curves showing that the dual-layer passivation process does not significantly alter ZTO TFT
electrical characteristics.
The second focus involves creating an adaptable back-end process compatible with flexible substrates. A detailed list of possible via formation techniques is presented with particular focus on non-traditional and adaptable techniques. Two of the
discussed methods, "hydrophobic surface treatment" and "printed local insulator," are demonstrated and proven effective.
The third focus is printing AOS TFT channel layers in order to create an adaptable and additive front-end integrated circuit fabrication scheme. Printed zinc indium aluminum oxide (ZIAO) and indium gallium zinc oxide (IGZO) channel layers are demonstrated using a SonoPlot piezoelectric printing system.
Finally, challenges associated with printing electronic materials are discussed. Organic-based solutions are easier to print due to their ability to "stick" to the substrate and form well-defined patterns, but have poor electrical characteristics due
to the weakness of organic bonds. Inorganic aqueous-based solutions demonstrate good electrical performance when deposited by spin coating, but are difficult to print because precise control of a substrate's hydrophillic/hydrophobic nature is required. However, precise control is difficult to achieve, since aqueous-based solutions either spread out or ball up on the substrate surface. Thickness control of any printed solution
is always problematic due to surface wetting and the elliptical thickness profile of a dispensed solution.Graduation date: 2013
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鄭閔仁. "Fabrication and characteristics of organic thin-film transistor." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/55977712923566799261.
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Yang, Yu-bang, and 楊育邦. "Development of Single-Grain Thin Film Transistor Devices." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/956p92.
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碩士國立臺灣科技大學
電子工程系
94
In order to obtain high-performance thin-film transistor(TFTs),the channel position of TFTs to keep away from the seed and inside a location-controlled single crystal which grain size is 10μm by using microlenses array. In addition, we have successfully accomplished 12um lateral growth on amorphous silicon and polysilicon layer by semi-photosensitive layer enhance crystallization. To analysis by EBSD, the orient of amorphous silicon and polysilicon layer of lattice crystalline is principal in <111>.
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Chen, Yu-Han, and 陳昱翰. "Asymmetric Raised Drain Poly-Si Thin Film Transistor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/bmv7z3.
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Kuo, Dong-Lin, and 郭東霖. "Studies of ZnO-Based Transparent Thin-Film Transistor." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/42233240051946527537.
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碩士國立成功大學
電機工程學系碩博士班
97
Abstract In this thesis, we demonstrate an all sputtering, all lithography technology process to fabricate low voltage operational, enhancement mode N-Type ZnO-TFT by using high-k material (Y2O3) as the gate oxide. The effects of different processing parameters of ZnO layer and device geometric structures to the electrical performance of device will be discussed in Chapter 4. We also did some applications of saving device area、driving OLED and fabricating TTFT array on glass substrate. Finally by improve the series resistance of TFT device, we fabricated devices had characters as field effect mobility (μFE) 6.5(cm2/V.s), ION/OFF~105, and Vth<5V. There are two parts in this thesis. In the first part, we discuss the ZnO-TFT characters when we use different sputtering parameters and structures. The thin film and devices were analyzed by XRD、AFM、SEM/EDS、C-V and I-V measurements. In the second part, by reducing the series resistance we can fabricate good performance TFT devices; finally, we fabricate a TTFT array of ZnO-TFT on glass substrate.
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Ni, Jia-Ning, and 倪佳寧. "Investigation of Spin-On Organic Thin Film Transistor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/06254015033634554477.
Full textAbstract:
碩士國立交通大學
電子工程系所
94
Recently, with the development of organic semiconductor materials, Organic Thin Film Transistors(OTFTs) have been widely investigated for low-cost, low-temperature and flexible display devices. In this thesis, we chose poly-3-hexylthiophene or P3HT as the active layer, SiO2 as the gate insulator, and deposited the organic thin film by spin coating process, organic thin film transistors have been successfully fabricated with “bottom contact”structure. First, we studied the possibility of low-temperature process. We deposited SiO2 as gate insulator by Plasma-Enhanced Chemical Vapor Deposition(PECVD) and Liquid-Phase Deposition(LPD). The advantages of LPD process include low-temperature, large coverage area, and low-cost. The performance of OTFT with LPD SiO2 as gate insulator is comparable with that with PECVD SiO2 except for the gate leakage current. To ameliorate the gate leakage current, we demonstrated a stacked structure which additional SiO2 was deposited by Selective LPD(S-LPD) as an isolation layer under source and drain electrodes. The gate leakage current was successfully reduced about one order, but the ON-current was reduced about half due to extra channel length. Next we studied how various plasma treatments on gate insulator affected device performance. We tried O2 plasma, N2O plasma, and NH3 plasma to remove residual contaminant on gate insulator, improving the performance of devices. With various plasma treatment time, we found that field-effect mobility and threshold voltage showed irregular variation with plasma exposure time, obviously shown with on current. In our experiment of plasma treatment, we also obtained the optimal condition according to various plasma sources and exposure time. Compared with devices with HMDS treatment, both mobility and threshold voltage of devices with plasma treatment have been improved.
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Cheng, Ming-Ren, and 鄭閔仁. "Fabrication and Characteristics of organic thin-film transistor." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/76773113465825891465.
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Beaumont, Ana Cecilia Marques de. "ZTO Thin film transistor parameter extraction and modeling." Master's thesis, 2017. http://hdl.handle.net/10362/31875.
Full textAbstract:
Transistor models are of utmost importance for device behaviour prediction and circuit design. Physical modelling has the advantage of the parameters being correlated based on device physics. This allows to gain insight on the device during the analysis and extraction of parameters phase. However, the extraction methods may not consider possible non-idealities of the device, which can cause modelling issues when working with novel thin film transistors (TFTs).
A simple physical DC and AC model was applied to a novel zinc tin oxide TFT annealed at low temperatures (200 ºC). The characteristic curves of four devices with different dimensions were measured and analysed, and the model parameters were extracted. The characterization and optimization of the models were implemented through the analysis of the fitting with the measured data. Two DC models were developed, the main difference being the contact resistance extraction - using the classic transmission-line method or a procedure based on MOSFETs with non-ideal behaviour that considers the possible bias dependency of the parameter. The latter method allowed to simulate the device characteristic curves more effectively. The AC model did not fit for frequencies above the cut-off and differed slightly for lower frequencies due to the simplicity of the model applied.
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Lin, Chang-Yu, and 林昶宇. "The study of ambipolar organic thin-film transistor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/72418196450623142941.
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LI, SHENG-HONG, and 李聖宏. "Amorphous-silicon thin film transistor-fabrication and characterization." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/14357964934939886781.
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Hsiao, Wei-Chih, and 蕭偉志. "Ti-doped Zinc Tin Oxide Thin Film Transistor." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/06620977321865715282.
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碩士國立中正大學
光機電整合工程所
98
In this thesis, we use titanium doped zinc tin oxide (Ti-doped ZTO) transparent thin film as a semiconductor layer to fabricated thin film transistors. To preparing Ti-doped ZTO target to controlled TiO2 content, and used pulsed laser deposition (PLD) system to growth Ti-doped ZTO thin films on silica/silicon (SiO2/Si) substrate by controlling laser pulse energy, laser repetition rate, and O2 gas flow. We fabricated bottom gate thin film transistors for Ti-doped ZTO thin film as channel material and measured the I-V characteristics. To compared different TiO2 content of Ti-doped ZTO TFT I-V characteristics. We fixed bottom gate and top contact (Al) TFT structure. When TiO2 doping content is 1.3 wt%, we can get a transistor characteristics. The data showed that the threshold voltage (Vth) is 13V, on-off ratio is 1.63 × 103 and field effect mobility (μfe ) is 11.2 cm2/Vs. At Vds = 40 and Vgs = 40V, the operating current of up to ~ 1mA. We fabricated bottom gate Ti-doped ZTO TFTs for top contact (ITO) and bottom contact (ITO) to compare the different structure of Ti-doped ZTO TFT I-V characteristics. To compared relationship between different TiO2 content of Ti-doped ZTO TFT and mobility. With XPS analysis, Ti atoms tend toward to use Ti2+ replace the Zn2+, and have few in the form of Ti4+ exists in Ti-doped ZTO thin films and the formation of oxygen vacancies, to increase mobility. When TiO2 content is excessive, Ti4+ can become scattering center, resulting poor mobility. With XRD analysis, Ti-doped ZTO thin films considered as an amorphous material. With UV-Vis analysis, transmittance above 80% in the visible range for Ti-doped ZTO thin films.
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Fan, Kung-Chih, and 范剛誌. "The Investigation of Rubrene Organic Thin Film Transistor." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/2796z6.
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碩士國立彰化師範大學
光電科技研究所
107
This thesis mainly discusses the use of organic small molecule polymer-rubrene to make p-type organic thin film transistor. Since the rubrene film is amorphous after evaporation, it needs to give some energy to let it be crystallization. The fluorene film produces a crystalline phase, so this paper successfully produced a rubrene film transistor element by using a four-stage annealing method under a nitrogen atmosphere. The first part mainly finds the way of multi-four-stage annealing, successfully produces a stable rubrene thin film transistor component, and uses AFM to observe the surface difference of the film before and after annealing, and finds the fourth stage of the finished rubrene. The surface of the film has a large change in morphology, and then the annealing temperature and the change of the Buffer layer are tried, and the current-voltage characteristics are measured to calculate the carrier mobility (μ), the On/Off ratio, and the threshold voltage (VTH). And the electrical parameter value of the subthreshold swing (SS). The second part is to explore the effect of temperature effect on the Rubrene thin film transistor. It can be known from experiments that the higher the ambient temperature, the higher the current of the rubrene film transistor component, which can be explained by trap binding. When the temperature is increased, the trap binding energy becomes smaller, so the carrier can pass more easily, so the carrier mobility is also increased.
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Chen, kuan jen, and 陳冠任. "Study of New Generation Field-Effect Transistor and Thin-Film Transistor Technology." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/80139597613652112896.
Full textAbstract:
碩士國立臺灣師範大學
光電科技研究所
97
Today, as MOSFET’s gate length getting small, to increase driving current and enhance gate control capability. in order to satisfy these requirements , It isn't comform to the semiconductor nowadays that SiO2 uses for gate oxide. Because the thickness of the insulator SiO2 will need to be reduced to small nanometer length, while keeping the EOT (equivalent oxide thickness) to maintain the characteristics of the devices. In the paper, in nanometer technology node, however, the electrons of the gate can flow through gate oxide into drain by tunneling in this place , and produce large leakage current . Using a new material with a dielectric constant greater than that of SiO2 to replace SiO2 film as gate dielectrics is an indispensable task.. Using insulators with high dielectric constant is one of the attractive and popular method to research the problem. Besides, SiGe materials has an important technique for improving the device performance other than conventional scaling method. Germanium can provide large mobility enhancement for CMOS. It will be of great importance to know the theoretical limit of mobility under various channel direction, and substrate orientation for device. In this research, we use the anneal process and fabrication that get good quality of HfSiOx film and metal TiN. There are suppression of leakage current and reduce of oxide layer for the device.
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許明朗. "Thin-Film LED and Transistor Fabricated by Using a." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/73885707846186406838.
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碩士國立中央大學
電機工程研究所
87
The conventional plasma-enhanced chemical vapor deposition (PECVD) system with an additional stainless steel (s.s.) mesh attached to cathode was used to fabricate Si-based thin-film light-emitting diode (TFLED) at a low substrate temperature (~180 ℃). The obtained TFLED had a brightness (B) of 1060 cd/m2 at an injection current density (J) of 600 mA/cm2 and a threshold voltage (Vth) of 12.6 V, which were much better than those of 330 cd/m2 and 18.5 V for an amorphous Si-based TFLED fabricated by the same PECVD system without a s.s. mesh. The improvements of opto-electronic characteristics for this TFLED would be mainly due to the used s.s. mesh, which would result in a deposited film with less plasma damages. The thin-film transistor (TFT) fabricated with the PECVD system with (without) a s.s. mesh had a saturation current of 22 (2.8) mA when its VGS was 25 V. We also found that the threshold voltage of the TFT fabricated with the PECVD system with (without) a s.s. mesh was 8 (13) V. The field-effect mobility was improved from 0.13 cm2/V-s to 0.44 cm2/V-s with the employed s.s. mesh. The improvements of device characteristics maybe result from the good-quality films deposited with the PECVD system having an additional s.s. mesh.
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Yen, Wen-Cheng, and 顏文正. "Effects of NH3-Annealing on Polysilicon Thin Film Transistor." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/44871242465686423841.
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碩士國立交通大學
電子研究所
83
In this thesis,we had complete investigated the joint effect of the low pressure NH3-annealing and the H2-plasma treatment to improve the performance of TFT's. Different temperatures, times and pressures were performed on both n- and p-channel TFT's. Above treated TFT's had better electrical characteristics. The improvement is believed to be due to nitrogen passivation effec When too much nitrogen was incorporated into the oxide and poly film, devices was improved only a little. An NH3-annealing at 800C for 40min or 900C 20min in combination with an H2-plasma treatment, before oxidation of n-channel TFT's, a optimum condition. For p-channel TFT's, the annealing condition was at 900C, 40min. However, for the NH3-annealing samples after oxidation in combination with the H2-plasma treatment, the optimum condition was 900C for 60min. The TFT's with the NH3 annealing brfore oxidation had better electrical characteristics.After the H2-plasma treatment, the TFT's with the NH3-annealing after oxidation had the larger electrical improvement. In contrast to the MOSFET with the nitrided-oxide, transconductance increased at low and high gate voltage for the NH3 annealing n- and p-channel TFT's.
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Yang, Hsiu-Ju, and 楊琇如. "STUDIES ON CHARACTERISTICS OF PENTACENE ORGANIC THIN-FILM TRANSISTOR." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/47x366.
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碩士大同大學
化學工程學系(所)
95
The main aim of this thesis is the enhancement on the characteristics of pentacene organic thin film transistor. Three kinds of different chlorosilane treated agents were employed to modify hydrophilic character of dielectric layer, and promoted the electric characteristics of organic thin-film transistor (OTFT). We investigated the electrical properties of the OTFTs using pentacene fabricated by thermal evaporation in a high vacuum with the three kinds of dielectric surface treating agent: octadecyltrichlorosilane (C18H37SiCl3) (OTS), phenyltrichlorosilane (C6H5SiCl3) (PTS), and phenethyltrichlorosilane (C6H5C2H4SiCl3) (PETS). Studies on properties of pentacene thin film and the performance of the device are affected by self-assembled monolayer (SAM) via the analysis of water contact angle, atom force microscope (AFM), X-ray diffractometer (XRD), field emission gun scanning electron microscopy (SEM), and semiconductor parametric test system (HP 4155C) have been carried out. Water contact angle of OTS-treated SiO2 surface is 84°, 85°, 86°, and 90°for the OTS concentration of 0.1, 0.5, 1.0, and 1.5 wt%, respectively. Water contact angle of PTS-treated SiO2 surface is 74°, 76°, and 81°for the PTS concentration of 0.5, 1.0, and 2.5 wt%, respectively. Therefore, the analysis result that the water contact angle of SiO2 surface increases with increasing the concentration of treating agent. The optimal evaporated temperature of pentacene OTFT with PTS-treated SiO2 was substrate temperature at 120℃ and pentacene evaporation temperature at 435℃. The field-effect mobility, on/off current ratio, threshold voltage, and subthreshold slope of pentacene OTFT were 9.97 ´ 10-2 cm2/Vs, 2.28 × 107, -15.7 V, and 1.05 V/decade, respectively. Through different concentration of OTS-treated SiO2 used, it is found that the best characteristics of OTFT occurs by 0.1 wt% OTS-treated SiO2. The field-effect mobility, on/off current ratio, threshold voltage, and subthreshold slope of OTFT were 3.57 × 10-1 cm2/Vs, 1.76 × 107, -7.7 V, and 1.01 V/decade, respectively. For the same reason, PTS and PETS-treated SiO2 can improve the characteristics of OTFT. The field-effect mobility, and on/off current ratio of pentacene OTFT with 2.5 wt% PTS-treated SiO2 were 2.09 ´ 10-1 cm2/Vs, and 3.66 × 106, respectively. The field-effect mobility, and on/off current ratio of pentacene OTFT with 0.3 wt% PETS-treated SiO2 were 2.28 ´ 10-1 cm2/Vs, and 3.99 × 107, respectively. The best performance of device is obtained using OTS as self-assembly monolayer agent. The field-effect mobility, and on/off current ratio of pentacene OTFT with OTS-treated SiO2 were enhanced one to two orders of magnitude, larger than those of untreated device. Photographs of Atom Force Microscope (AFM) and Scanning Electron Microscopy (SEM) showed that the size of crystals was smaller, and similar. The surface of pentacene was more flatness. Therefore, it lead to the packing of pentacene thin-film being more compact and less trap, hence enhanced OTFT’s electrical property. The intensity of single crystal phase of pentacene thin film deposited on the surface of 0.1 and 0.5wt% OTS-treated SiO2 exhibits 1642 and 804, respectively. The corresponding field-effect mobility is 3.57 × 10-1 and 1.17 × 10-1 cm2/Vs. Similarly, the intensity of single crystal phase of pentacene thin film deposited on the surface of 0.1, 1.5 and 2.5wt% PTS-treated SiO2 exhibits 1390, 2090, and 4198, respectively. The corresponding field-effect mobility is 1.48 × 10-1, 1.48 × 10-1 and 2.09 × 10-1cm2/Vs. Therefore, XRD shows that the higher the intensity of single crystal / thin film phase, the better the electric properties. The less amount of water in a air at lower pressure, resulting in the trap was less in the material. It enhanced the characteristics of OTFT. The field-effect mobility and on/off current ratio of pentacene OTFT with 0.1 wt% OTS treated SiO2 are 4.12 ×10-1 cm2/Vs and 3.04 × 107, respectively, at the pressure of 4.6 × 10-2 torr. The field-effect mobility and on/off current ratio of pentacene OTFT with 2.5 wt% PTS treated SiO2 are 2.09 ×10-1 cm2/Vs and 108, respectively, at the pressure of 4.9 × 10-2 torr. The field-effect mobility and on/off current ratio of pentacene OTFT with 0.3 wt% PETS treated SiO2 are 2.65 ×10-1 cm2/Vs and 3.43 × 107, respectively, at the pressure of 19 torr.
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Lin, Chia-Sheng, and 林佳盛. "Reliability and Degradation Mechanism of Polysilicon Thin-Film Transistor." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/43rn86.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
95
In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics. The two mechanisms of the electrical stress are ac and dc stress. On the dc stress, we can separate the two degradation mechanisms from fixed drain voltage and various the gate voltage. The first mechanism is hot carrier effect, and second is self-heating effect. We were study the degradation mechanisms cause by above-mentioned phenomenon. On the other hand, we were confirmed the position and type of the defects by measured capacitance. In the ac stress, device degradation depends on the emission rate and energy of the hot carrier. We will study the degradation mechanism which fixed the drain voltage and various the Vg_low and falling time under different temperature. Another way of the ac stress condition will be used here. The drain and source are directly connected to ground. The gate is directly connected to the pulse. At this stress condition, carrier will push to the junction near the drain and source when gate pulse is switch from high to low. This degradation mechanism is the function of the temperature. We are going to employ a C-V measurement to examination of the defect cause by stress.
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Chen, Sui-chih, and 陳綏之. "The Organic Thin Film Transistor with Submicron Planar Structure." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/8e4jxd.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
99
There are two main structures of organic thin film transistor (OTFT), Top contact (TC) and Bottom contact (BC). The former structure with lower contact resistance has better electrical performance than the latter one. But the TC structure has some problems about scaling-down of device dimension and large area process. We modified the BC structure in order to reduce the contact resistance and to improve the performance of device. While retaining the advantages of the original BC structure, we can also fabricate the sub-micron device. We introduce a planer BC structure with bi-layer insulator. This new structure could make the growth quality of organic active layer be better than those of original structure because there is no a step height between source/drain electrodes and gate insulator. As the reasons we mentioned above, the new structure has much lower contact resistance. Finally, we scaled down the dimension of devices and proved that the planar structure, which has better growth quality of organic active layer, has the better electrical performance and uniformity than the original structure.
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Weng, Chi-feng, and 翁崎峰. "Inverstigation on Reliability of Poly-Silicon Thin-Film Transistor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80939684902119161134.
Full textAbstract:
碩士國立中山大學
物理學系研究所
93
The influence of grain boundary (GB) on stability of poly-silicon thin film transistor (TFT) have been investigated in this work. The work was supported by the National Science Council of the Republic of China and AUO. We used ac stress and dc stress conditions to stress different TFTs, and investigate the influence of grain boundary by use of electrical analysis. The SLS poly-Si TFT which does contain GB perpendicular to the channel direction owns the higher ability against dc stress and poorer ability against ac stress than the poly-Si TFT which does not contain GB. The physical mechanism for these results has been reasonably deduced by use of TFT device simulation tool (ise-tcad).
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Chang, Yu-chuan, and 張裕詮. "Study on fabrication of high performance thin film transistor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/12499652013068779922.
Full textAbstract:
碩士國立中山大學
光電工程研究所
94
In recently yesrs,Thin-film transistors (TFTs) including an active layer of amorphous silicon or polycrystalline silicon have been widely employed as the pixel-driving elements of a liquid crystal display (LCD). Particularly, a-Si:H TFT is advantageous to the production of large screen displays and facilitates mass-production. a-Si:H has high photoconductivity which results in high off-state leakage currents of a-Si:H TFT under light illumination . Particularly, the off-state leakage current under light illumination is a serious problem in the projection and/or video displays which require high intensity backlight illumination.As the resolutions is higher , the TFT’s performance must be higher to achieve the short charge time each line can charge. The performance includes mobility ,on current, off current, photo leakage current, threshold voltage ,and subthrehold swing. Furthermore, the to improve the mobility of thin-film transistors (TFT) to enable total integration of peripheral electronics in flat panel displays and imagers has led to recrystallized polycrystalline silicon (poly-Si) as the material of choice. However, laser recrystallized polycrystalline silicon suffers from high cost , complex processing, and significant nonuniformity over a large area. Indeed, the direct deposition of good-quality low-temperature poly films is highly desirable and constitutes a promising alternative. In this thesis, we use HDPCVD to fabricate direct deposition poly-TFT successfully.Through plasma passivation, we improve the characteristic of device. The photo-Leakage current have been reduced obviously to our device under light illumination, and is benefit to higher intensity light of large screen display. And our TFT device exhibits stable characteristics with voltage and current stress , and it’s also confirmed that the device is reliable. On the characteristic of device, the direct-deposited poly TFT device exhibits higher effective carrier mobility than that of conventional one. For that reason, the high performance provides the potential of the direct-deposited poly TFT to apply for AMLCD and AMOLED technology.
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Tsai, Zen-Jay, and 蔡仁傑. "The study of n-type organic thin film transistor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/65220922414485665359.
Full textAbstract:
碩士國立成功大學
光電科學與工程研究所
94
Abstract An electron accumulation-mode operation in organic field-effect transistor (OFET) using a thin film of pentacene and Al source-drain electrode was demonstrated. Most of the reported transistors use organic semiconductors capable of transporting holes(p-type). The organic dielectrics play a important role to realize electrons transport. Appearance of the electron accumulation-mode in OFET was ascribed to the lowering of barrier for electron injection at a source electrode and introduced a complex dielectric. The present study indicates that the morphology of the semiconductor interface at the organic semiconductor/organic dielectric is a critical parameter for OFET properties such as electrons transport.