Relevant bibliographies by topics / Blocker Tolerant Receiver

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Blocker Tolerant Receiver'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "Blocker Tolerant Receiver"

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Ul Haq, Faizan, Mikko Englund, Yury Antonov, Miikka Tenhunen, Kari Stadius, Marko Kosunen, Kim B. Ostman, Kimmo Koli, and Jussi Ryynanen. "A Six-Phase Two-Stage Blocker-Tolerant Harmonic-Rejection Receiver." IEEE Transactions on Microwave Theory and Techniques 68, no. 5 (May 2020): 1964–76. http://dx.doi.org/10.1109/tmtt.2020.2966152.

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Lenka, Manas Kumar, and Gaurab Banerjee. "A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 5 (May 2019): 993–1006. http://dx.doi.org/10.1109/tvlsi.2019.2895624.

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Murphy, David, Hooman Darabi, Asad Abidi, Amr A. Hafez, Ahmad Mirzaei, Mohyee Mikhemar, and Mau-Chung Frank Chang. "A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications." IEEE Journal of Solid-State Circuits 47, no. 12 (December 2012): 2943–63. http://dx.doi.org/10.1109/jssc.2012.2217832.

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Wu, Hao, Mohyee Mikhemar, David Murphy, Hooman Darabi, and Mau-Chung Frank Chang. "A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal Noise Cancellation." IEEE Journal of Solid-State Circuits 50, no. 12 (December 2015): 2948–64. http://dx.doi.org/10.1109/jssc.2015.2458956.

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Kaltiokallio, Mikko, Risto Valkonen, Kari Stadius, and Jussi Ryynanen. "A 0.7–2.7-GHz Blocker-Tolerant Compact-Size Single-Antenna Receiver for Wideband Mobile Applications." IEEE Transactions on Microwave Theory and Techniques 61, no. 9 (September 2013): 3339–49. http://dx.doi.org/10.1109/tmtt.2013.2274434.

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Mincey, John S., Jose Silva-Martinez, Aydin Ilker Karsilayan, and Christopher T. Rodenbeck. "Blocker-Tolerant and High-Sensitivity $\Delta \Sigma $ Correlation Digitizer for Radar and Coherent Receiver Applications." IEEE Transactions on Microwave Theory and Techniques 65, no. 9 (September 2017): 3453–63. http://dx.doi.org/10.1109/tmtt.2017.2679008.

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Lenka, Manas Kumar, and Gaurab Banerjee. "Corrections Corrections to “A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback” [May 19 993-1006]." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 5 (May 2019): 1238. http://dx.doi.org/10.1109/tvlsi.2019.2902297.

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Shin, Donguk, Kyudo Lee, and Kuduck Kwon. "A Blocker-Tolerant Receiver Front End Employing Dual-Band N-Path Balun-LNA for 5G New Radio Cellular Applications." IEEE Transactions on Microwave Theory and Techniques 70, no. 3 (March 2022): 1715–24. http://dx.doi.org/10.1109/tmtt.2021.3136295.

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Wu, Hao, Ning-Yi Wang, Yuan Du, and Mau-Chung Frank Chang. "A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS." IEEE Transactions on Microwave Theory and Techniques 63, no. 3 (March 2015): 1053–62. http://dx.doi.org/10.1109/tmtt.2015.2393310.

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Trotskovsky, Konstantin, Amy Whitcombe, Gregory Lacaille, Antonio Puglielli, Pengpeng Lu, Zhongkai Wang, Nathan Narevsky, et al. "A 0.25–1.7-GHz, 3.9–13.7-mW Power-Scalable, −10-dBm Harmonic Blocker-Tolerant Mixer-First RF-to-Digital Receiver for Massive MIMO Applications." IEEE Solid-State Circuits Letters 1, no. 2 (February 2018): 38–41. http://dx.doi.org/10.1109/lssc.2018.2813010.

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Dissertations / Theses on the topic "Blocker Tolerant Receiver"

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Lenka, Manas Kumar. "Blocker-tolerant Receiver Design Suitable for Software-defined and Cognitive Radio Applications." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/4127.

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The ever growing demand for higher data rates and the heavy usage of wireless communication devices have created frequency congestion on certain bands of the radio spectrum. The push has been towards new standards that can quench this thirst for data capacity and more space on the spectrum. This has led to added complexity and cost for radio platforms. In particular, the increase in the number of antennas, switch banks and pre-select filters have made it challenging to implement these platforms cost-effectively. Therefore, concepts such as software-defined radio(SDR) and cognitive radio(CR) have been proposed to tackle this problem. These concepts, allow the use of a single wideband receiver which can handle multiple radio standards spread across the entire spectrum of interest. The introduction of a common flexible hardware platform eliminates the use of multiple off-chip RF pre-filters and thus lowers cost, reduces complexity and form factor. While attractive, these future radio receivers pose a number of unique challenges to the designer. This thesis focuses on frequency translation (FT) techniques and addresses two key SDR/CR challenges: the robustness to out-of-band interference (OBI) or block-ers and the compatibility with CMOS scaling and system-on-chip (SoC) integration. The thesis studies the principles and the performance limitations of existing FT tech-niques and proposes new circuit-and-system techniques to improve the performance of wideband receivers suitable for SDR and CR applications. First, the performance of the frequency translational resistive feedback receiver frontend is studied and analyzed. Instead of using a conventional LNA, the job of the LNA is shared along the receiver chain through the utilization of frequency translation techniques. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. Though frequency translation is at the core of the receiver functionality, it is accomplished using time-varying, strongly nonlinear passive mixer circuits. So the operation and noise performance cannot be understood using standard LTI circuit analysis techniques. To this end, an in-depth LTV analysis is presented which accurately captures the gain, input matching and the noise performance of the receiver. Next, a wideband blocker tolerant receiver with an RF frequency range of 0.1 GHz to 2.2 GHz is proposed. By using frequency-translational resistive shunt-feedback, the receiver achieves frequency selective input match across its entire range of operation. Four techniques for improving blocker tolerance of the receiver have been utilized: 1) voltage amplification only after baseband filtering 2) blocker rejection at the antenna interface using an N-path filter 3) blocker current cancellation in the baseband 4) frequency translational noise cancellation which uses an auxiliary path to cancel the noise of the main path. By introducing an auxiliary path, the value of the RF transconductor in the main path is halved which in turn relaxes the requirements of the main path and further improves the overall linearity of the receiver while degradation in the noise figure is prevented due to noise-cancellation. As a proof of concept, a receiver prototype is fabricated in a 130 nm CMOS process. The measurement results demonstrate that the receiver achieves +2dBm in-band IIP3 and +27dBm out-of-band IIP3. The measured noise figure varies from 2.6 dB at low frequencies to 3.2 dB at 2.2 GHz. The receiver can tolerate a +2.5 dBm blocker beyond a 40 MHz offset while achieving a blocker noise figure of 4.6 dB for a 0-dBm blocker at 40 MHz offset. Finally, architecture and circuit techniques are proposed to improve the receiver’s resilience to strong harmonic blockers. Designed in a 40nm standard CMOS process, the receiver can tolerate up to -1 dBm harmonic blockers. On the other hand, it achieves a 1-dB standard blocker compression point of +3 dBm and OB-IIP3 of +24 dBm at a 40 MHz offset from the LO frequency.
Department of Electronics and Information Technology, Govt. of India.
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Ahmed, Ramy 1981. "Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers." Thesis, 2012. http://hdl.handle.net/1969.1/148047.

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The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (ΔƩ) ADCs show up as an attractive option. CT ΔƩ ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ΔƩ ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ΔƩ modulators in presence of OOB blockers. Also, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ΔƩ modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn’t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719µwatts from 1.3V supply.
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Conference papers on the topic "Blocker Tolerant Receiver"

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Ying, Robin, Matthew Morton, and Alyosha Molnar. "A HBT-based 300 MHz-12 GHz blocker-tolerant mixer-first receiver." In ESSCIRC 2017 - 43rd IEEE European Solid-State Circuits Conference. IEEE, 2017. http://dx.doi.org/10.1109/esscirc.2017.8094518.

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Babakrpur, Esmail, and Won Namgoong. "A 4-phase blocker tolerant wideband receiver with MMSE harmonic rejection equalizer." In 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2016. http://dx.doi.org/10.1109/rfic.2016.7508296.

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Murphy, David, Amr Hafez, Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi, Mau-Chung Frank Chang, and Asad Abidi. "A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure." In 2012 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2012. http://dx.doi.org/10.1109/isscc.2012.6176935.

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Kim, Duksoo, and Sanzwook Nam. "A Blocker-Tolerant Double Noise-Cancelling Wideband Receiver Front-End Using Linearized Transconductor." In 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2018. http://dx.doi.org/10.1109/rfic.2018.8428975.

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Ye, Yuting, Shushu Yu, and Gengzhen Qi. "A design of High-linearity Blocker Tolerant RF Receiver Based on Four-Path Filter." In 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2022. http://dx.doi.org/10.1109/icicm56102.2022.10011280.

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Sung, Barosaim, Chilun Lo, Jaehoon Lee, Sangdon Jung, Seungjin Kim, Jaehong Jung, Seungyong Bae, et al. "A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS." In 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2019. http://dx.doi.org/10.1109/a-sscc47793.2019.9056898.

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Qi, Nan, Zheng Song, Zehong Zhang, Yang Xu, Baoyong Chi, and Zhihua Wang. "A multi-mode blocker-tolerant GNSS receiver with CT sigma-delta ADC in 65nm CMOS." In 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2013. http://dx.doi.org/10.1109/asscc.2013.6691050.

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Cai, Chenxiang, Gengzhen Qi, and Pui-In Mak. "A Low-Power Blocker-Tolerant Receiver with Wideband Negative-Feedback Technique Achieving 22.4dBm OOB-IIP3." In 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2022. http://dx.doi.org/10.1109/icicm56102.2022.10011388.

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Ramella, Matteo, Ivan Fabiano, Danilo Manstretta, and Rinaldo Castello. "A 1.7–2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS." In 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2015. http://dx.doi.org/10.1109/asscc.2015.7387493.

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Liu, Renzhi, Asma Beevi K. T., Richard Dorrance, Deepak Dasalukunte, Mario A. Santana Lopez, Vinod Kristem, Shahrnaz Azizi, Minyoung Park, and Brent R. Carlton. "An 802.11ba 495μW -92.6dBm-Sensitivity Blocker-Tolerant Wake-up Radio Receiver Fully Integrated with Wi-Fi Transceiver." In 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2019. http://dx.doi.org/10.1109/rfic.2019.8701780.

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You might also be interested in the extended bibliographies on the topic 'Blocker Tolerant Receiver' for particular source types:
Journal articles
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