Dissertations / Theses on the topic 'Block turbo codes'
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Martin, Philippa Anne. "Adaptive iterative decoding : block turbo codes and multilevel codes." Thesis, University of Canterbury. Electrical and Electronic Engineering, 2001. http://hdl.handle.net/10092/7853.
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New adaptive, iterative approaches to the decoding of block Turbo codes and multilevel codes are developed. Block Turbo codes are considered as they can readily provide high data rates, low decoding complexity and good performance. Multilevel codes are considered as they provide a moderate complexity approach to a high complexity code and can provide codes with good bandwidth efficiency.
The work develops two adaptive sub-optimal soft output decoding algorithms for block Turbo codes. One is based on approximation and the other on the distance properties of the component codes. They can be used with different codes, modulation schemes, channel conditions and in different applications without modification. Both approaches provide improved performance compared to previous approaches on the additive white Gaussian noise (AWGN) channel. The approximation based adaptive algorithm is also investigated on the uncorrelated Rayleigh fiat fading channel and is shown to improve performance over previous approaches.
Multilevel codes are typically decoded using a multistage decoder (MSD) for complexity reasons. Each level passes hard decisions to subsequent levels. If the approximation based adaptive algorithm is used to decode component codes in a traditional MSD it improves performance significantly. Performance can be improved further by passing reliability (extrinsic) information to all previous and subsequent levels using an iterative MSD. A new iterative multistage decoding algorithm for multilevel codes is developed by treating the extrinsic information as a Gaussian random variable. If the adaptive algorithms are used in conjunction with iterative multistage decoding on the AWGN channel, then a significant improvement in performance is obtained compared to results using a traditional MSD.
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Sholiyi, Abiodun Olugbenga. "Irregular block turbo codes for communication systems." Thesis, Swansea University, 2011. https://cronfa.swan.ac.uk/Record/cronfa43150.
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Hirst, Simon. "Iterative decoding techniques for block based error correction codes." Thesis, Lancaster University, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.289060.
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Wang, Charles C., and Tien M. Nguyen. "USING SHORT-BLOCK TURBO CODES FOR TELEMETRY AND COMMAND." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608708.
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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, NevadaThe turbo code is a block code even though a convolutional encoder is used to construct codewords. Its performance depends on the code word length. Since the invention of the turbo code in 1993, most of the bit error rate (BER) evaluations have been performed using large block sizes, i.e., sizes greater than 1000, or even 10,000. However, for telemetry and command, a relatively short message (<500 bits) may be used. This paper investigates the turbo-coded BER performance for short packets. Fading channel is also considered. In addition, biased channel side information is adopted to improve the performance.
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Šedý, Jakub. "Turbo konvoluční a turbo blokové kódy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219287.
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The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.
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Ganti, Kamalakar. "Interleaver design for modified circular simplex turbo block coded modulator." Ohio : Ohio University, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1107805760.
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Pirestani, Shervin. "Source-controlled block turbo coding." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 69 p, 2008. http://proquest.umi.com/pqdlink?did=994238721&sid=2&Fmt=2&clientId=8331&RQT=309&VName=PQD.
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Chapalain-Le, Floc'h Nadine. "Application des Turbo Codes en blocs pour les réseaux locaux sans fil à haut débit." Brest, 2002. http://www.theses.fr/2002BRES2033.
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Cette thèse s'inscrit dans le cadre général des communications numériques et comporte deux parties. La première partie est consacrée à l'évaluation et l'analyse des performances des turbo codes en blocs (BTC) dans l'environnement radio-mobile HIPERLAN/2 (HIgh PERformance Local Area Network type 2). Dans cette partie, deux algorithmes à entrées e t sorties pondérées sont étudiés, l'algorithme sous-optimal de Chase-Pyndiah de complexité raisonnable qui minimise la probabilité d'erreur par mot du code élémentaire et l'algorithme optimal de Nazarov qui minimise la probabilité d'erreur symbole à symbole mais dont la complexité est nettement plus élevée. Cette étude montre que pour une transmission sur un canal aux atténuations fortement corrélées de type HIPERLAN/2, la répartition de la corrélation en entrée du turbo décodeur a une grande influence sur les performances et qu'un entrelaceur doit être défini de manière à répartir les échantillons corrélés uniformément dans la matrice du code. La deuxième partie présente l'étude et l'optimisation de la mise en ouvre de l'algorithme de turbo décodage de Chase-Pyndiah sur le DSP TMS320C6201 (1600 Mips à 200MHz) à virgule fixe de Texas Instrument. Cette dernière partie vise à démontrer la faisabilité de la mise en couvre des turbo codes en blocs sur DSP, et ceci pour des débits de plus en plus élevés. Cette mise en rouvre a été réalisée en langage C pour permettre une portabilité du code pour d'autres applications et sur d'autres DSP. La mise en couvre permet d'atteindre un débit utile de 394 Kb/s pour un turbo décodage du BTC(1024, 676) avec 4 itérationsThis thesis deals with digital wireless communication and is divided in two parts. In the first part, the performance of block turbo codes (BTC) is evaluated and analysed in the HIPERLAN/2 (HIgh PERformance Local Area Network type 2) radio mobile environment. In this part, two soft-input soft-output decoding algorithms are studied, the sub-optimal Chase-Pyndiah algorithm of reasonable complexity that minimises the elementary code word error probability, and the optimal Nazarov algorithm that minimises the symbol error probability but is much more complex. This work shows that for channels with highly correlated atténuation (i. E. HIPERLAN/2 type channels), the distribution of the corrélation at the input of the turbo decoder has a big impact on the performance and that an interleaver should be defined in order to spread uniformly the correlated samples in the code matrix. The second part focuses on the study and optimisation of the implementation of the Chase-Pyndiah turbo decoding algorithm on the fixed point DSP TMS320C6201 (1600 Mips à 200MHz) provided by Texas Instrument. This work intends to demonstrate the feasibility of the implementation of block turbo codes on DSP while providing increasing data rates. The algorithm was implemented in C language in order to enable the code portability for other applications and on other DSP. With this implementation, a data rate of 394 Kb/s can be reached for the turbo decoding of the BTC(1024, 676) with 4 itérations
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Chinchilla, Rigoberto. "Interleaver design for the circular simplex turbo block coded modulator." Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1178129287.
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Shaheem, Asri. "Iterative detection for wireless communications." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2008. http://theses.library.uwa.edu.au/adt-WU2008.0223.
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[Truncated abstract] The transmission of digital information over a wireless communication channel gives rise to a number of issues which can detract from the system performance. Propagation effects such as multipath fading and intersymbol interference (ISI) can result in significant performance degradation. Recent developments in the field of iterative detection have led to a number of powerful strategies that can be effective in mitigating the detrimental effects of wireless channels. In this thesis, iterative detection is considered for use in two distinct areas of wireless communications. The first considers the iterative decoding of concatenated block codes over slow flat fading wireless channels, while the second considers the problem of detection for a coded communications system transmitting over highly-dispersive frequency-selective wireless channels. The iterative decoding of concatenated codes over slow flat fading channels with coherent signalling requires knowledge of the fading amplitudes, known as the channel state information (CSI). The CSI is combined with statistical knowledge of the channel to form channel reliability metrics for use in the iterative decoding algorithm. When the CSI is unknown to the receiver, the existing literature suggests the use of simple approximations to the channel reliability metric. However, these works generally consider low rate concatenated codes with strong error correcting capabilities. In some situations, the error correcting capability of the channel code must be traded for other requirements, such as higher spectral efficiency, lower end-to-end latency and lower hardware cost. ... In particular, when the error correcting capabilities of the concatenated code is weak, the conventional metrics are observed to fail, whereas the proposed metrics are shown to perform well regardless of the error correcting capabilities of the code. The effects of ISI caused by a frequency-selective wireless channel environment can also be mitigated using iterative detection. When the channel can be viewed as a finite impulse response (FIR) filter, the state-of-the-art iterative receiver is the maximum a posteriori probability (MAP) based turbo equaliser. However, the complexity of this receiver's MAP equaliser increases exponentially with the length of the FIR channel. Consequently, this scheme is restricted for use in systems where the channel length is relatively short. In this thesis, the use of a channel shortening prefilter in conjunction with the MAP-based turbo equaliser is considered in order to allow its use with arbitrarily long channels. The prefilter shortens the effective channel, thereby reducing the number of equaliser states. A consequence of channel shortening is that residual ISI appears at the input to the turbo equaliser and the noise becomes coloured. In order to account for the ensuing performance loss, two simple enhancements to the scheme are proposed. The first is a feedback path which is used to cancel residual ISI, based on decisions from past iterations. The second is the use of a carefully selected value for the variance of the noise assumed by the MAP-based turbo equaliser. Simulations are performed over a number of highly dispersive channels and it is shown that the proposed enhancements result in considerable performance improvements. Moreover, these performance benefits are achieved with very little additional complexity with respect to the unmodified channel shortened turbo equaliser.
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Zhou, Rong. "Etude des Turbo codes en blocs Reed-Solomon et leurs applications." Rennes 1, 2005. http://www.theses.fr/2005REN1S027.
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Cette thèse porte sur l’étude des turbo codes en blocs (TCB) construits à partir de codes de Reed-Solomon (RS) et sur les applications potentielles de ce schéma de codage. Nous commençons par rechercher un algorithme de décodage à entrée souple applicable aux codes RS et offrant un compromis raisonnable entre performances et complexité. Nous montrons que l’algorithme Chase-II implémenté au niveau binaire répond bien à ces critères lorsque l’on se restreint à la classe des codes RS 1 ou 2-correcteurs. Nous examinons ensuite l’influence du choix des codes RS constituants sur les performances du TCB-RS en considérant une transmission MDP-4 sur canal BABG et en mesurant l’écart entre les résultats obtenus et la limite de Shannon corrigée pour les codes de longueur finie. Nous montrons ainsi que les codes produits résultant de la concaténation au niveau symbole de deux codes RS classiques de pouvoir de correction égal à 1 offrent le meilleur compromis performance/complexité. A rendement équivalent, les performances obtenues sont très proches de la limite de Shannon et sont comparables à celles des TCB construits à partir de codes BCH. En revanche, la taille du code est trois fois moindre dans le cas des TCB-RS, ce qui se traduit en retour par une réduction substantielle de la quantité mémoire nécessaire, de la complexité du décodage et du retard de restitution. Nous montrons également que les TCB-RS ainsi construits atteignent des performances proches de l’optimal à la fois sur le canal binaire symétrique et sur le canal à effacement, ce qui les rend particulièrement attractifs pour les systèmes de communication optiques à haut débit et les systèmes de stockages. Nous nous intéressons ensuite à l’association pragmatique des TCB-RS avec des modulations à grand nombre d’états de type MAQ-M sur canal BABG. Nous montrons que les performances obtenues se situent à moins de 1 dB de la capacité du canal, sous réserve que la condition Q >= M soit respectée (Q désignant ici l’ordre du corps de Galois utilisé). Ce résultat se situe à l’opposé de ce qui est habituellement observé avec des turbo codes binaires (l’écart par rapport à la capacité augmentant avec l’ordre de la modulation) et souligne ainsi l’intérêt des TCB-RS pour les applications à forte efficacité spectrale (DSL, TNT, réseaux d’accès radio). Des simulations similaires sont présentées à la fois sur le canal de Rayleigh et pour d’autres modulations (MDP-8 et MDP-16). Nous observons alors une dégradation des performances. Ce dernier point nécessite des travaux de recherche ultérieurs dans le but de définir des règles générales de construction de bons codes adaptés à l’environnement de transmission et capables d’opérer au plus proche de la capacité du canal
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Martins, João Paulo Trierveiler. "Turbo decodificadores de bloco de baixa potência para comunicação digital sem fio." Universidade de São Paulo, 2004. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-27092004-161308/.
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Turbo códigos têm se tornado um importante ramo na pesquisa de codificação de canal e já foram adotados como padrão para a terceira geração de comunicação móvel. Devido ao seu alto ganho de codificação, os turbo códigos são vistos como fortes candidatos a serem adotados como padrão das futuras gerações de redes sem fio. Esse esquema de codificação é baseado na decodificação iterativa, onde decodificadores de entrada e saída suaves produzem refinamento da informação a cada iteração. Essa dissertação apresenta resultados de um estudo comparativo entre dois esquemas de codificação: turbo códigos de bloco e turbo códigos convolucionais. Os resultados mostram que os dois esquemas de codificação têm desempenho funcional complementar, sendo importante a especificação de um alvo em termos de relação sinal/ruído ou taxa de erro de bits para a escolha do esquema de codificação mais adequado. Com o mesmo modelo em linguagem de programação C foi feita uma exploração do algoritmo visando diminuição do consumo de potência. Essa exploração em parte foi feita segundo uma metodologia de exploração sistemática das possibilidades de transferência e armazenamento de dados (DTSE). Com a exploração, a redução total de consumo de potência para o armazenamento de dados foi estimada em 34%.Turbo codes have become an important branch on channel coding research and have been adopted as standard in the third generation of mobile communication systems. Due to their high coding gain, turbo codes are expected to be part of the next generations of wireless networks standards. This coding scheme is based on iterative decoding, as soft input/soft output decoders produce an information refinement in each iteration. This dissertation shows the results of a comparative performance study of two different turbo coding schemes: block turbo codes and convolutional turbo codes. The results obtained show that the two schemes have complementary performance. It is necessary to specify a target in terms of bit error rate or signal/noise ratio. With the same C model an exploration aiming at reducing power consumption was done. Part of this exploration was done following a systematic methodology of data transfer and storage exploration (DTSE). With this exploration, a reduction of 34% on power consumption was estimated.
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Gunnam, Kiran Kumar. "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1049.
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Nordmark, Oskar. "Turbo Code Performance Analysis Using Hardware Acceleration." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-137666.
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The upcoming 5G mobile communications system promises to enable use cases requiring ultra-reliable and low latency communications. Researchers therefore require more detailed information about aspects such as channel coding performance at very low block error rates. The simulations needed to obtain such results are very time consuming and this poses achallenge to studying the problem. This thesis investigates the use of hardware acceleration for performing fast simulations of turbo code performance. Special interest is taken in investigating different methods for generating normally distributed noise based on pseudorandom number generator algorithms executed in DSP:s. A comparison is also done regarding how well different simulator program structures utilize the hardware. Results show that even a simple program for utilizing parallel DSP:s can achieve good usage of hardware accelerators and enable fast simulations. It is also shown that for the studied process the bottleneck is the conversion of hard bits to soft bits with addition of normally distributed noise. It is indicated that methods for noise generation which do not adhere to a true normal distribution can further speed up this process and yet yield simulation quality comparable to methods adhering to a true Gaussian distribution. Overall, it is show that the proposed use of hardware acceleration in combination with the DSP software simulator program can in a reasonable time frame generate results for turbo code performance at block error rates as low as 10−9.
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Ta, Thomas. "Implémentation sur FPGA d'un turbo codeur-décodeur en blocs à haut débit avec une faible complexité." Rennes 1, 2003. http://www.theses.fr/2003REN1S145.
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Inventés par C. Berrou et al. En 1992 à l'ENST Bretagne, les Turbo Codes Convolutifs (TCC) sont devenus la référence des codes correcteurs d'erreurs grâce à leur pouvoir de correction avoisinant la limite théorique de Shannon. En 1993, R. Pyndiah et al. Ont proposé un nouvel algorithme itératif de décodage des codes produits dont les performances sont comparables à celles des TCC, voire meilleures pour les codes de rendement supérieur à 0,7. Cet algorithme baptisé Turbo Code en Blocs (TCB) est en fait un équivalent des TCC pour les codes en blocs. Cette thèse présente une implémentation sur FPGA d'un turbo codeur-décodeur en blocs à haut-débit avec une faible complexité. Pour satisfaire ces contraintes, nous proposons d'utiliser l'architecture itérative à traitement par blocs. Les simulations en langage C et la synthèse en VHDL ont permis de montrer que notre implémentation peut atteindre un débit de 50 Mbit/s avec une complexité de moins de 4500 éléments logiques.
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Diatta, Ibrahima. "Étude de turbo codes blocs de Reed-Solomon appliqués à la boucle locale filaire haut débit." Paris 12, 2004. http://www.theses.fr/2004PA120036.
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La demande croissante en débit des applications, combinée au succès de l’ADSL (Asynchronous Digital Subscriber Line), ont poussé à la recherche d’une nouvelle génération de technologies xDSL utilisant la paire bifilaire comme support physique de transmission. L’importance des débits visés (jusqu’à 52 Mbits/s) par ce nouveau système dénommé VDSL (Very high bit rate Digital Subscriber Line) nécessite des traitements du signal et de l’information sophistiqués pour s’approcher de la capacité offerte par la boucle locale filaire. L’objectif de cette thèse est l’étude des performances des turbo codes blocs de Reed-Solomon afin de les appliquer au système VDSL. Après avoir défini le cadre de la boucle locale par rapport aux réseaux existants, nous décrivons les caractéristiques de la paire bifilaire, qui est le principal support physique de transmission utilisé par le VDSL, avant de détailler les principales caractéristiques du point de vue des communications numériques du système VDSL. La dernière partie de cette thèse est consacrée à l’étude des turbo codes blocs et leur application au système VDSL. Les turbo codes, dont le principe de décodage est basé sur l’algorithme de Pyndiah, ont permis d’obtenir des performances très appréciables en termes de gain de codage et débit, malgré des conditions très contraignantes du canal filaire. On montre en particulier que les gains de portée appréciables peuvent être obtenus pour des forts débitsThe increasing request for the flow of applications combined with the success of the ADSL (Asynchronous Digital Subscriber Line) pushed in the search of a new generation of technologies xDSL using the two-wire pair as a physical support of transmission. The importance of the flows aimed (up to 52 Mbits/s) by this new system called VDSL (Very high bit rate Digital Subscriber Line) requires sophisticated treatments of the signal and information to approach the capacity offered by the local loop. The objective of this thesis is the study of the performances of the block turbo codes Reed-Solomon in order to apply them to the VDSL system. After recalling the local loop principle in the network context, we describe the characteristics of the two-wire pair, which is the principal physical media of transmission used by the VDSL, before detailing the principal characteristics of the VDSL system. The last part of this thesis is devoted to the study of the block turbo codes and their application to the VDSL system. The turbo codes, whose principle of decoding is based on the algorithm of Pyndiah, made it possible to obtain very appreciable performances in terms of coding gain and bit rate, in spite of very constraining conditions of the channel. It is shown in particular that the appreciable ranging gain can be obtained for strong bit rates
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Diatta, Ibrahima Geller Benoît Lemoine Jacques. "Étude de turbo codes blocs de Reed-Solomon appliqués à la boucle locale filaire haut débit." Créteil : Université de Paris-Val-de-Marne, 2004. http://doxa.scd.univ-paris12.fr:80/theses/th0214120.pdf.
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Wavegedara, Kapila Chandika B. "Advanced receivers for space-time block-coded single-carrier transmissions over frequency-selective fading channels." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/620.
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In recent years, space-time block coding (STBC) has emerged as an effective transmit-diversity technique to combat the detrimental effects of channel fading. In addition to STBC, high-order modulation schemes will be used in future wireless communication systems aiming to provide ubiquitous-broadband wireless access. Hence, advanced receiver schemes are necessary to achieve high performance. In this thesis, advanced and computationally-efficient receiver schemes are investigated and developed for single-carrier space-time (ST) block-coded transmissions over frequency-selective fading (FSF) channels.
First, we develop an MMSE-based turbo equalization scheme for Alamouti ST block-coded systems. A semi-analytical method to estimate the bit error rate (BER) is devised. Our results show that the proposed turbo equalization scheme offers significant performance improvements over one-pass equalization. Second, we analyze the convergence behavior of the proposed turbo equalization scheme for Alamouti ST block-coded systems using the extrinsic information transfer (EXIT)-band chart technique.
Third, burst-wise (BW)-STBC is applied for uplink transmission over FSF channels in block-spread-CDMA systems with multiuser interference-free reception. The performances of different decision feedback sequence estimation (DFSE) schemes are investigated. A new scheme combining frequency-domain (FD) linear equalization and modified unwhitened-DFSE is proposed. The proposed scheme is very promising as the error-floor behavior observed in the existing unwhitened DFSE schemes is eliminated.
Fourth, we develop a FD-MMSE-based turbo equalization scheme for the downlink of ST block-coded CDMA systems. We adopt BW-STBC instead of Alamouti symbol-wise (SW)-STBC considered for WCDMA systems and demonstrate its superior performance in FSF channels. Block spreading is shown to be more desirable than conventional spreading to improve performance using turbo equalization. We also devise approximate implementations (AprxImpls) that offer better trade-offs between performance and complexity. Semi-analytical upper bounds on the BER are derived.
Fifth, turbo multicode detection is investigated for ST block-coded downlink transmission in DS-CDMA systems. We propose symbol-by-symbol and chip-by-chip FD-MMSE-based multicode detectors. An iterative channel estimation scheme is also proposed. The proposed turbo multicode detection scheme offers significant performance improvements compared with non-iterative multicode detection. Finally, the impact of channel estimation errors on the performance of MMSE-based turbo equalization in ST block-coded CDMA systems is investigated.
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Piriou, Erwan. "Apport de la modélisation et de la synthèse haut niveau dans la conception d'architecture flexible dédiée aux turbocodes en blocs." Télécom Bretagne, 2007. http://www.theses.fr/2007TELB0029.
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Cette thèse s’inscrit dans la continuité des travaux menés au sein du département électronique de l'ENST-Bretagne sur l’implantation des turbo-décodeurs de codes produits. Le premier axe de recherche de l’étude concerne l’implantation d’une architecture flexible d’un turbo-décodeur. Le second axe s’intéresse à l’évolution des flots de conception, des langages de description et de leurs applications. L'ensemble est validé par la mise en oeuvre d’un prototype. L’architecture que nous proposons se compose à la fois d’une partie matérielle réalisant la fonction de décodage et d’une partie logicielle remplissant le rôle de contrôleur. Une étude de complexité en amont a permis de caractériser les paramètres de l’application. L’innovation de notre architecture repose sur le caractère flexible permettant de choisir le code composant (BCH ou Reed Solomon) et le pouvoir de correction pour des longueurs de code variables. Il est à noter qu’il s’agit de la première intégration d’un turbo-décodeur à base de code Reed Solomon. Ce travail a en particulier bénéficié de l'expertise algorithmique de l'ENST Bretagne sur les turbocodes. Dans le cadre de cette thèse, un flot de conception dit de haut niveau a été expérimenté. Dans un premier temps, le développement de la chaîne de transmission numérique a été effectué à l’aide du langage système de description SystemC sous l'environnement System Studio de Synopsys. Puis, les synthèses logiques avec l’outil SystemC Compiler de Synopsys ont permis d’obtenir des descriptions au niveau netlist. De plus, des synthèses de haut niveau ont ensuite été effectuées à travers l’utilisation d’outils tels que GAUT et Agility Compiler. Elles ont été menées sur les différents éléments de l’architecture afin d’évaluer les apports de cette approche. Le prototypage de l’architecture novatrice a été effectué sur un FPGA Altera Stratix sur une carte de développement NIOS II. En effet, au début de ces travaux, en 2003, la société Altera proposait des solutions matures par rapport à celles du concurrent Xilinx pour les processeurs soft embarqués, c'est ce qui a principalement motivé notre choix. Ce travail s’inscrit donc dans une forte évolution des cibles matérielles et des outils durant ces trois dernières années. Sur notre plate-forme, un processeur logiciel NIOS II sert de structure de contrôle et est relié à la partie matérielle de décodage via un bus système dédié de type Avalon. Le processus de turbo décodage met en oeuvre des codes BCH(32,26) (resp. (32,21)) et des codes Reed Solomon (31,29) (resp. (31,27)) d’un pouvoir de correction t=1 (resp. T=2). Les applications potentielles, pouvant bénéficier de cette architecture flexible, sont nombreuses notamment dans le domaine des télécommunications mobiles, des transmissions optiques, du stockage en masse ou du xDSLThis thesis’ work continues previous research undertaken at the electronics department of the ENST Bretagne on the implementation of a turbo decoding architecture for product codes. The first research area studies the implementation of a flexible turbo decoding architecture. The second concerns the evolution of design flow, description languages and their applications. The results are validated by prototyping a platform. The proposed architecture includes two main design blocks. The first is a hardware module performing the decoding process. The second is a software based control unit. A study of system complexity was carried out to identify the various parameters of the application. The innovative aspect of our architecture is the flexibility in the choice of a component code (BCH or Reed Solomon) and its error correcting power. This is the first architecture known to date implementing Reed-Solomon block turbo codes. This work benefited from the knowledge of ENST Bretagne on turbocodes. Within the context of this thesis, a high level design flow was used, and the method was divided into two steps. First, a digital communication chain was developped with the help of the SystemC description language and System Studio design tool. Then, netlist descriptions were obtained by performing logic synthesis with SystemC compiler tool from Synopsys. The usage of a high level synthesis on sub-modules of the architecture allows us to quantify the benefits of this approach. The architecture was mapped to an Altera Stratix FPGA on a NIOS II development board. In fact, our choice of solutions from Altera was motivated by the fact that at the beginning of this work, Altera offered the best solution concerning software processors when compared to Xilinx. In our design, the control task is achieved by the NIOS II embedded processor. An avalon system bus binds the hardware decoding part and the processor. The turbo decoding process concerns BCH(32,26) (resp. (32,21)) and Reed Solomon (31,29) (resp. (31,27)) codes with t=1 (resp. T=2) as error correcting power. Many potential applications such as mobile communications, optical transmission, data storage and xDSL can benefit from flexible architectures dedicated to block turbo codes
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Kwak, Yongjun. "Near Shannon Limit and Reduced Peak to Average Power Ratio Channel Coded OFDM." Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10176.
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Solutions to the problem of large peak to average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems are proposed. Although the design of PAPR reduction codewords has been extensively studied and the existence of asymptotically good codes with low PAPR has been proved, still no reduced PAPR capacity achieving code has been constructed. This is the topic of the current thesis.This goal is achieved by implementing a time-frequency turbo block coded OFDM.
In this scheme, we design the frequency domain component code to have a PAPR bounded by a small number. The time domain component code is designed to obtain good performance while the decoding algorithm has reasonable complexity. Through comparative numerical evaluation we show that our method achieves considerable improvement in terms of PAPR with slight performance degradation compared to capacity achieving codes with similar block lengths. For the frequency domain component code, we used the realization of Golay sequences as cosets of the fi rst order Reed-Muller code and the modi cation of dual BCH code. A simple MAP decoding algorithm for the modi ed dual BCH code is also provided. Finally, we provide a flexible and practical scheme based on probabilistic approach to a PAPR problem. This approach decreases the PAPR without any signi cant
performance loss and without any adverse impact or required change to the system.Engineering and Applied Sciences
21
Jacq, Sylvie. "Décodage itératif des codes produits : "turbo-codes en blocs", et évaluations de leurs performances pour des modulations MDP et MAQ sur canal de Gauss et de Rayleigh." Limoges, 1996. http://www.theses.fr/1996LIMO0056.
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Huang, Hsian-Cheng, and 黃憲政. "Investigate block turbo codes and performance analysis." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/17888468956101319955.
Full textAbstract:
碩士中華大學
電機工程學系碩士班
98
In the last ten years, the wireless communication techniques have been developed rapidly. In the future, the wireless communication systems will be requested to have higher data transmission rate. The transmitted signal will be seriously disturbed by the interference and noise. And then the system performance will be important. The block turbo codes have more excellent decoding performance and low complexity. Thus the decoding algorithm of block turbo codes will be investigated. Finally, for the IEEE 802.16 system, the performance of block turbo codes will be analyzed.
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Li, Ssu-Hsien, and 李思賢. "Concatenation of Turbo Product Codes and Space Time Block Codes." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/42h364.
Full textAbstract:
碩士中原大學
電機工程研究所
92
Abstract The multipath wireless channel suffers severe attenuation. The Effective techniques to mitigate multipath fading are time and frequency diversity. Foschini,Gans and Telatar proved that multiple input multiple output can introduce spatial diversity and increased information capacity. These results have motivated a new area in error correcting codes . Space-Time Coding (STC) schemes can combine the channel code design and the use of multiple transmit antennas . The Space Time Trellis Codes (STTC) proposed by Tarkoh combine the trellis coding with symbol mapping into multiple transmit antennas . The Coding scheme expansion is done in antenna space. The Turbo Codes proposed by Berrou have powerful error correcting abilities. It would be benefit to design turbo codes for multiple antenna systems. To design space-time turbo codes with maximum space diversity and outstanding performance is still an open question. The Turbo Codes exhibited a troublesome error floor. Besides, the MAP algorithm which performs maximum likelihood bit estimation has a very large computation complexity . Recently turbo product codes (TPC) have been proposed . It can proved the performance of turbo codes. It is expected that TPC for multiple antenna systems would be powerful coding schemes with maximum diversity gain and large coding gain.
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Yin, Bo. "Trellis decoding of 3-D block turbo codes." Thesis, 2002. http://spectrum.library.concordia.ca/1815/1/MQ72917.pdf.
Full textAbstract:
Forward Error Correction (FEC) technique provides a method to detect and correct errors in transmitted data. It is also a valuable technique to reduce the power requirement, thus have an important role in these systems. This reduction in power requirement is achieved at the expense of an increase in bandwidth requirement. The objective is usually to find error control techniques that give good tradeoff between power and bandwidth requirements. In this thesis, we present results for FEC technique using Turbo Block Codes and Turbo Product Codes. It is shown that these codes, not only in theory but also in hardware implementation, are capable of providing significant performance gains over other error-correction schemes. This thesis investigates Trellis based iterative decoding techniques applied to concatenated coding schemes, Turbo Block Codes. We use RM( n, k ) to construct 2-D and multi-dimensional Turbo Block Codes. Our objective is to get high code rates and long block sizes for more bandwidth efficiency and improving the performance of the optimised maximum a posterior decoding algorithm
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Wang, Chin Tai, and 王璟玳. "A Novel Hybrid Decoder for Block Turbo Codes." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02803500974514200902.
Full textAbstract:
碩士長庚大學
電機工程學系
98
This thesis proposes extrinsic-information-based decoding algorithms for original block turbo codes (BTCs) and hybrid block turbo codes. Since the number of algebraic decodings dominates the complexity of BTC decoding, it is important for BTC research to reduce the number of algebraic decodings without noticeable loss of bit-error rate performance. In each iterative decoding process, the algorithm compares the extrinsic information of the mth iteration and the (m-1)th iteration to determine when the HIHO decoding starts. Additionally, in BTC decoding, the decoder can use the other proposed algorithm to determine the rows/columns that are decoded using HIHO decoding to achieve the reduction of the number of algebraic decodings.
26
Lee, Jia-Jhan, and 李佳展. "Design Scheme of Space-Time Block Codes Concatenated with Turbo Codes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65108082199099493675.
Full textAbstract:
碩士中興大學
電機工程學系所
95
The wireless channel suffers severe attenuation caused by multipath fading. The effective technique to mitigate multipath fading is to use the time or frequency diversity. The communication system with multiple input multiple output can combat the channel attenuation by spatial diversity and increase the channel information capacity. The principle of space-time coding schemes is to combine the concept of channel coding design and multiple transmit antennas, which are then effectively applied to multipath wireless channel. Since the amount of data transfer of the modern digital or mobile communication is increasing, the reliability of the data transfer has become more and more important. Therefore, the error correction coding has played a very important role in wireless communication channel. The turbo code is one of the most popular error correction codes at present due to its good error correction ability. Besides, the turbo code is adopted in the 3G mobile communication standard. In this thesis, we present the application of several important concepts of wireless digital communications, i.e., serial concatenation, turbo coding, and temporal and antenna diversity . We combine the turbo code and the space-time block code and use the LogMAP algorithm to implement the soft in/soft out decoding algorithms of turbo code. Finally, we present our simulation results under different encoding scheme of the space time block code. Furthermore, we also present the comparison of the simulation result under different rate of space-time block codes but the same number of transmit antennas.
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Chow, William. "Concatenated space-time block codes and turbo codes with unstructured interference." 2004. http://hdl.handle.net/1828/452.
Full textAbstract:
The performance of space-time block codes in providing transmit diversity is severely degraded when strong localized interference is present. This problem is addressed by investigating a recently proposed coherent space-time block code decoding algorithm for unknown interference suppression. The algorithm assumes a Gaussian noise and interference approximation and is based on a cyclic-based maximum-likelihood estimation technique (CML). In this thesis, simulations are done applying CML in a coherent system with unstructured interference to validate previous work. An extension of these results is obtained by examining factors that affect CML performance and modifying CML for use in a noncoherent system. To improve bit error rate performance, a turbo code for channel coding was added to both systems. This addition required the development of reliability metrics for soft-information transfer between the space-time block code detector and the turbo code decoder. Significant coding gains exceeding 8dB at a bit error rate of are achieved for the turbo-coded system when compared to that of an uncoded system.
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Huei-Min, Huang, and 黃暉閔. "Performance Evaluation of Space-Time Block Codes Concatenated with Turbo Codes and LDPC Codes." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/96876167066577233975.
Full textAbstract:
碩士國立中興大學
電機工程學系所
96
The multi-input-multi-output (MINO) technique is one in the breakthroughs of wireless communications. Space time block code (STBC) with maximal ratio receive combining (MRRC) is one of the systems using MIMO to reduce error rate by increasing the numbers of antennas in transmitter and receiver. The system performance can be greatly improved by applying error correcting coding, such as turbo codes and low density party check (LDPC) codes which are known because of performance approaching their to Shannon limits. In this thesis, we first introduce the traditional MRRC with 1 transmitter antenna and multi receiver antennas. Then we describe the property of STBC with multi transmitter antennas and multi receiver antennas. For error correcting codes, we use turbo codes and LDPC codes. In turbo codes, we use two parallel concatenated convolution codes for encoding and BCJR algorithm for decoding. For LDPC codes, we use IEEE 802.16e standard for encoding and sum-product algorithm for decoding. Finally, we combine turbo codes and LDPC codes with MIMO system and discuss the bandwidth efficiency of these combinations.
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Chou, Chih Lin, and 周志霖. "Study on Improving the Performance for Block Turbo Codes." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/82122774067019421024.
Full textAbstract:
碩士長庚大學
電機工程學系
98
In a general decoding algorithm of block turbo codes(BTCs), the weighting factor α and reliability factors β are fixed in each decoding iteration. However, for time-variant channels predefined α and β are not appropriate in BTC decoding. The thesis proposes a method to set the values of α and β dynamically based on input and output values of the decoder. BTC decoding algorithms use an iterative decoding procedure to achieve high bit error rate performance typically with eight half decoding iterations. However, the requirement of the number of decoding iterations is related to the channel;i.e., the larger the noise is, the more number of iterations is required. Three novel stopping criterions are proposed in the thesis. Simulation results demonstrate that these proposed stopping criterions substantially reduce the number of decoding iterations. For example, about 64% iterations can be saved (on average) at Eb/No=5dB without the noticeable loss of BER performance.
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Zheng, Yan-Xiu, and 鄭延修. "Inter-block permutation interleaver design for high throughput turbo codes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/80119601906015718864.
Full textAbstract:
博士國立交通大學
電信工程系所
96
With all its remarkable performance, the classic turbo code (TC) suffers from prolonged latency due to the relatively large iteration number and the lengthy interleaving delay required to ensure the desired error rate performance. We present a systematic approach that solves the dilemma between decoding latency and error rate performance. Our approach takes both algebraic and hardware constraints into account. From the algebraic point of view, we try to build large interleavers out of small interleavers. The structure of classic TC implies that we are constructing long classic TCs from short classic TCs in the spirit of R. M. Tanner. However, we go far beyond just presenting a new class of interleavers for classic TCs. The proposed inter-block permutation (IBP) interleavers meet all the implementation requirements for the parallel turbo decoding such as memory contention-free, low routing complexity and simple memory addressing circuitry. The IBP interleaver has simple algebraic form; it also allows flexible degrees of arallelism and is easily adaptable to variable interleaving lengths. Even without high throughput demand, the IBP design is capable of improving the distance property with increased equivalent interleaving length but not the decoding delay except for the initial blocks. We classify the IBP interleavers into block and stream ones. For both classes we derive codeword weight bounds for weight-2 input sequences that give us important guidelines for designing good IBP interleavers. We prove that the algebraic properties required to guarantee good distance properties satisfying the memory contention-free requirement as well. For block IBP interleavers, we propose memory mapping functions for flexible parallelism degrees and high-radix decoding units. A network-oriented design concept is introduced to reduce the routing complexity in the parallel decoding architectures. We suggest efficient interleaver design flows that offer a wide range of choices in the interleaving length. A VLSI design example is given to demonstrate that the proposed interleavers do yield high throughput/low complexity architecture and, at the same time, give excellent error rate performance. The stream-oriented IBP interleavers are designed for the pipeline decoding architecture which is suitable for high throughput applications but has to pay the price of large hardware complexity. In order to achieve optimal trade-off between hardware complexity and decoding throughput, a dynamic decoder architecture is proposed. We address the issues of decoding schedule and memory management and introduce the novel stopping mechanisms that incorporate both CRC code and sign check. With a proper decoding schedule, memory manager and early-stopping rule, we are able to reduce the hardware complexity and achieve improved error rate performance with a shorter average latency. In order to describe various parallel and pipeline iterative decoding schedules and analyze their behaviors, we develop a graphic tool called multi-stage factor graphs. Based on this new tool we derive a new decoding schedule which gives compatible error rate performance with less memory storage. For completeness, we show some irregular puncturing patterns that yield good error rate performance.
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Lu, Pen Yao, and 呂本堯. "The Study of the Decoding Algorithms for Reed-Solomon Codes and Block Turbo Codes." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/75477674722052582492.
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Botha, P. R. (Philippus Rudolph). "Iterative decoding of space-time-frequency block coded mimo concatenated with LDPH codes." Diss., 2013. http://hdl.handle.net/2263/33344.
Full textAbstract:
In this dissertation the aim was to investigate the usage of algorithms found in computer
science and apply suitable algorithms to the problem of decoding multiple-input multipleoutput
(MIMO) space-time-frequency block coded signals. It was found that the sphere
decoder is a specific implementation of the A* tree search algorithm that is well known in
computer science. Based on this knowledge, the sphere decoder was extended to include
a priori information in the maximum a posteriori probability (MAP) joint decoding of the
STFC block coded MIMO signals. The added complexity the addition of a priori information
has on the sphere decoder was investigated and compared to the sphere decoder without
a priori information. To mitigate the potential additional complexity several algorithms that
determine the order in which the symbols are decoded were investigated. Three new algorithms
incorporating a priori information were developed and compared with two existing
algorithms. The existing algorithms compared against are sorting based on the norms of the
channel matrix columns and the sorted QR decomposition.
Additionally, the zero forcing (ZF) and minimum mean squared error (MMSE) decoderswith and without decision feedback (DF) were also extended to include a priori information.
The developed method of incorporating a priori information was compared to an existing
algorithm based on receive vector translation (RVT). The limitation of RVT to quadrature
phase shift keying (QPSK) and binary shift keying (BPSK) constellations was also shown in
its derivation. The impact of the various symbol sorting algorithms initially developed for
the sphere decoder on these decoders was also investigated. The developed a priori decoders
operate in the log domain and as such accept a priori information in log-likelihood ratios
(LLRs). In order to output LLRs to the forward error correcting (FEC) code, use of the
max-log approximation, occasionally referred to as hard-to-soft decoding, was made.
In order to test the developed decoders, an iterative turbo decoder structure was used together
with an LDPC decoder to decode threaded algebraic space-time (TAST) codes in a Rayleigh
faded MIMO channel. Two variables that have the greatest impact on the performance of the
turbo decoder were identified: the hard limit value of the LLRs to the LDPC decoder and the
number of independently faded bits in the LDPC code.Dissertation (MEng)--University of Pretoria, 2013.
gm2014
Electrical, Electronic and Computer Engineering
unrestricted
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Le, Nong. "A new distance-based algorithm for block turbo codes : from concept to implementation." Thesis, 2005. http://spectrum.library.concordia.ca/8469/1/MR10240.pdf.
Full textAbstract:
List-based algorithms for decoding Block Turbo Codes (BTC) have gained popularity due to their low computational complexity. The normal way to calculate the soft outputs involves searching for a decision code word D and a competing codeword B. In addition, a scaling factor {460} and an estimated reliability value β are used. In this thesis, we present a new approach that does not require {460} and β. Soft outputs are generated based on the Euclidean distance property of decision code words. More importantly, such algorithm has very low computational complexity and is very attractive for practical applications. Based on the synthesis result of FPGA (Field Programmable Gate Array) implementations of the new algorithm, significant complexity saving (up to 79%) is achieved compared to commercially available products. In terms of error performance, we observe certain improvement (0.3dB coding gain) for BTCs of large Hamming distance and negligible performance degradation for BTCs of short Hamming distance.
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Huang, Kai Jie, and 黃楷傑. "An Improved Chase II Algorithm and the Application of Decoding Block Turbo Codes." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/70454072362999022385.
Full textAbstract:
碩士長庚大學
電機工程學研究所
97
This paper proposes a low-complex Chase-2 decoding algorithm and the decoding of block turbo codes (BTCs). In addition, we study the trend of extrinsic information to promote the bit-error-rate (BER) performance of BTCs. Chase proposed Chase-2 algorithm to reduce decoding complexity of soft-decision decoding for linear block codes. According to channel measurements, we can find a set of candidate codewords. From the set, we select the minimum squared Euclidean distance codeword D as the optimum decision, which reduces the complexity of the soft-decision decoding. This paper proposes a method to form a smaller candidate set to reduce the complexity of the traditional Chase algorithm. Simulation results show, the performance of threshold Chase-2 is almost the same as Chase-2. In [17], R. M. Pyndiah uses the maximum a posteriori (MAP) theorem to compute the extrinsic information of block turbo codes. We use Chase-2 to find the optimum decision D and the competing codeword. Then, we compute the soft outputs which are used to compute the extrinsic information. This paper proposes an improved Chase II algorithm and the application of decoding block turbo codes. By computer simulation, we set threshold equal to 1. The performance is almost the same as Chase-2, but we reduce the computation about 30.48%.
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Chen, Hui Cheng, and 陳惠禎. "A Reliability-Based Soft-input Soft-output Decoding Algorithm for Block Turbo Codes." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/25225241013050853015.
Full textAbstract:
碩士長庚大學
電機工程學系
98
Block turbo codes (BTCs) was proposed by Pyndiah in 1998 and it have be shown the performance of BTCs close to the Shannnon limit. In order to achieve a reasonable decoding complexity, generally the number of the least reliable bits is set four in most of decoding process. However, the soft outputs in some ambiguous sequences are unreliable that will cause causing the loss of BER. This thesis proposes a decoding algorithm for improving the performance of BTCs. The algorithm utilizes the average reliability to increase the number of the least reliable bits for those ambiguous sequences to obtain more accurate soft outputs. Compared with Pyndiah’s algorithm, the proposed algorithm offers a substantial BER performance improvement in the fifth iteration with a neglect cost of the decoding complexity.
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CHI, CHIA-HUNG, and 紀佳宏. "Study on Improving the Performance for Block Turbo Codes by Dynamically Estimating Weighting Factors Based on Mutual Information." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/d5775k.
Full textAbstract:
碩士明志科技大學
電子工程系碩士班
102
In a general decoding algorithm of block turbo codes(BTCs), the weighting factor α and reliability factor β are fixed in each static decoding iteration with increasing times. It’s difficult to decode codes under poor channel environment. However, the time-variant channels predefined α and β are not appropriate in BTC decoding because they are not easily being controlled. The thesis proposes a method to set the values of α and β dynamically based on input and output values of the decoder. BTC decoding algorithms use an iterative decoding procedure to achieve low bit error rate performance typically with eight half decoding iterations. However, the requirement for the number of decoding iterations is related to the channel; i.e. , the larger the noise is, the more the number of iterations is required. So in the traditional BTC decoders, we practically measure the input and output values of decoders, then establish entropy and mutual information concepts to make the decoding process work smoothly.
37
Liao, Jimmy J. M., and 廖俊閔. "Design and Implementation of Block Turbo Code Codec." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/pnsada.
Full textAbstract:
碩士國立交通大學
電子工程系所
96
In this thesis, a block turbo code of 802.16e is proposed. Unlike the conventional decoding algorithm requiring empirically derived parameters, the proposed geometric-like algorithm uses hamming distance to compensate the information. Not only improving the error performance, the proposed algorithm also facilitates hardware implementation. Moreover, a design methodology for parallel architecture is presented to meet various throughputs. The memory accessing hazard in parallel architecture can be overcome by the proposed multi-bank-array algorithm. The proposed algorithm is a partition and scheduling technique without extra memory. By the proposed algorithm and parallel design methodology, the block turbo code encoder and decoder defined in WiMAX(802.16e) is implemented. Note that, a design flow from algorithm level (in C language) to hardware level (in Verilog ) is presented. A systemC model is also built to provide a more efficient verification strategy and allows electronic system level design.
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Vlok, Jacobus David. "Sparse graph codes on a multi-dimensional WCDMA platform." Diss., 2007. http://upetd.up.ac.za/thesis/available/etd-07042007-155428.
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Chen, Zhi-Feng, and 陳志峰. "Turbo Block Coded Modulation with Interblock Memory." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/7na8nm.
Full textAbstract:
碩士中原大學
電機工程研究所
92
Turbo-codes are very powerful codes for power limited AWGN channels. The turbo-codes invented by Berrou et al. use two parallel-concatenated recursive systematic convolutional codes. The iterative decoding algorithm is good to operate at only a fraction of a dB from the Shannon limit. The discovery of turbo-codes does not put an end to the story of error control coding. On the contrary, it has resulted in a renaissance of coding research. By using the ‘turbo’ principle, many related codes have been discovering. The application of turbo-codes in bandwidth-efficient coded modulation techniques is one of the important issues. The coded modulation technique uses combined coding and modulation to achieve appreciable coding gains without sacrificing the bandwidth. Block coded modulation (BCM) is based on a block by block manner while trellis coded modulation (TCM) is based on a trellis code. We can easily construct BCM schemes with good error correcting abilities by choosing proper binary block codes. However, the huge decoding complexities for long block codes limit the practical usage of BCM with long block design. Block coded modulation with interblock memory (BCMIM) is an improved BCM scheme. Compared to BCM for which each block is independent of the others, the introduction of interblock coding can increase the coding rates and coding gains. The associated multi-stage decoding algorithm is optimum in each stage and has low decoding complexity. We’ll improve the bit error rate performance of BCMIM by introducing the concept of concatenated coding and iterative decoding. It is expected that further coding gains will be obtained.
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Ku, Hsien-Chun, and 顧賢俊. "An Architecture of Decoder for Reed-Solomon Block Turbo Code." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/82810967468479543019.
Full textAbstract:
碩士中華大學
電機工程學系碩士班
98
In the last few years, error correcting codes have been investigated because of the rapid development of wireless communications. Reed-Solomon code is one of error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been investigated. This was motivated by the higher code rate property of Reed-Solomon codes and their efficiency for burst error correction. For the next generation wireless technologies, Reed-Solomon block turbo codes can offer a good trade-off between complexity and performance for ultra-high throughputs. In fact, the main advantage of Reed-Solomon block turbo codes is for high code rate application. In this thesis, Reed-Solomon block turbo codes will be investigated and a decoder architecture for (31,29)2 Reed-Solomon block turbo codes using step-by-step Reed-Solomon decoder will be proposed.
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Chang, Wang-Yueh, and 張汪鉞. "Design and Implementation of high-speed step-by-step Reed-Solomon Block Turbo Code Decoder." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/82203425220273650664.
Full textAbstract:
碩士國立彰化師範大學
電信工程研究所
100
It is well known that the wireless communication technology has been developed towards broadband services. However, to keep the high quality and high throughput for wireless communication systems over wireless channel environment with noise and interferences is a real challenge. The forward error correction techniques can be employed to improve the performance and widely used in wireless communication systems. The concept of iterative decoding turbo code makes decoding performance close to the Shannon limit. Turbo code has established its future status in the wireless communication system. However, it has very high complexity and long latency delay. In this paper, based on the step-by-step decoding algorithm in RS codes, it has the properties of low-complexity and high-speed. A modified step-by-step decoding procedure for single-error-correcting RS codes is proposed. Moreover, a modified decoding procedure for Chase RS-BTC decoding with step-by-step RS decoding algorithm has also been proposed. The simulation result shows that the modified decoding procedure we proposed is improved for RS-BTC. This paper also proposed a high-speed step-by-step RS-BTC decoder architecture with low decoding complexity and short latency delay. The Verilog HDL is used here to construct RS-BTC decoder hardware and used to FPGA board to complete the decoder circuit design. This RS-BTC has a good balance between performance and complexity suitable to apply to the broadband wireless communication systems with high transmission speed and high bandwidth efficiency trends in the future.
42
Yin, Yizhi. "Le codage distribué pour un réseau de capteurs sans-fil basé sur les turbo codes en bloc." Phd thesis, 2012. http://tel.archives-ouvertes.fr/tel-00777396.
Full textAbstract:
Cette thèse étudie les performances d'un réseau de capteurs sans-fil coopératif, basé sur un codage réseau algébrique linéaire appliqué au relais. On considère un schéma coopératif basé sur le code produit en bloc où un grand nombre de sources transmettent des données indépendantes codées par un premier code en bloc vers un seul destinataire avec l'aide du relais. Dans ce schéma, le relais applique le codage réseau algébrique linéaire en utilisant un code correcteur d'erreur systématique linéaire en bloc sur les mots de code source détectés par le relais. Seule, la redondance générée par le relais est transférée vers le destinataire. Le destinataire observe un mot de code produit en bloc en combinant les observations des sources et du relais. Premièrement, on aborde la coopération en mode time-division multiple-access (TDMA) et suppose un canal source-relais bruité. On analyse les probabilités théoriques à l'entrée et à la sortie du relais pour différente stratégies de détection au relais. On établit aussi une borne théorique sur la probabilité d'erreur de trame pour le schéma coopératif proposé. Puis on évalue la coopération multi-relais afin de traiter la corrélation des erreurs dans la redondance générée par le relais. Différents configurations de coopération (mono ou multi-relais avec différentes stratégies au relais) sont comparées. On montre que la liaison source-relais est le maillon faible du réseau. On évalue ensuite la capacité du réseau sous la condition de taille finie du code. Ensuite, on étudie la coopération basée sur la technique code-division multiple-access (CDMA) appliqué au relais de telle sorte que le signal du relais est avec ceux des sources dans la même bande de fréquence radio. Pour simplifier l'analyse, on suppose un canal source-relais sans erreur. On propose une procédure de décodage itératif avec la neutralisation de l'interférence. On formule deux cas de coopération basé sur CDMA: TDMA-CDMA avec répartition orthogonale dans le temps entre les sources et FDMA-CDMA avec allocation de sous-bandes de fréquence disjointes pour les sources. Le ratio d'allocation d'énergie entre les sources et le relais est évalué en utilisant les simulations.