Journal articles on the topic 'Bit-level'
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Peters, Martine. "French, Bit By Bit Multimedia Level 1." CALICO Journal 21, no. 1 (December 4, 2017): 167–73. http://dx.doi.org/10.1558/cj.35193.
Full textPikus, Marcin, and Wen Xu. "Bit-Level Probabilistically Shaped Coded Modulation." IEEE Communications Letters 21, no. 9 (September 2017): 1929–32. http://dx.doi.org/10.1109/lcomm.2017.2704596.
Full textDong Ho Kim and Sang Wu Kim. "Bit-level stopping of turbo decoding." IEEE Communications Letters 10, no. 3 (March 2006): 183–85. http://dx.doi.org/10.1109/lcomm.2006.1603378.
Full textAGGOUN, A., A. ASHUR, and M. K. IBRAHIM. "Bit-level pipelined digit-serial multiplier." International Journal of Electronics 75, no. 6 (December 1993): 1209–19. http://dx.doi.org/10.1080/00207219308907196.
Full textGrover, Radhika S., Weijia Shang, and Qiang Li. "Bit-level two's complement matrix multiplication." Integration 33, no. 1-2 (December 2002): 3–21. http://dx.doi.org/10.1016/s0167-9260(02)00020-2.
Full textDonoho, David L. "Unconditional Bases and Bit-Level Compression." Applied and Computational Harmonic Analysis 3, no. 4 (October 1996): 388–92. http://dx.doi.org/10.1006/acha.1996.0032.
Full textWang, Peng, Cui Ni, Zhe Li, and Guangyuan Zhang. "Optimal CTU-level bit allocation in HEVC for low bit-rate applications." Multimedia Tools and Applications 78, no. 16 (May 9, 2019): 23733–47. http://dx.doi.org/10.1007/s11042-019-7680-7.
Full textHeule, Marijn, and Hans van Maaren. "Parallel SAT Solving using Bit-level Operations1." Journal on Satisfiability, Boolean Modeling and Computation 4, no. 2-4 (May 1, 2008): 99–116. http://dx.doi.org/10.3233/sat190040.
Full textRoy, Satyaki. "The Extensive Bit-level Encryption System (EBES)." International Journal of Information Technology and Computer Science 5, no. 5 (April 1, 2013): 67–73. http://dx.doi.org/10.5815/ijitcs.2013.05.09.
Full textKhanna, Neeraj, Dripto Chatterjee, Asoke Nath, and Joyshree Nath. "Bit Level Encryption Standard (BLES): Version-I." International Journal of Computer Applications 52, no. 2 (August 30, 2012): 41–46. http://dx.doi.org/10.5120/8177-1496.
Full textWagdy, M. F. "Diagnosing ADC nonlinearity at the bit level." IEEE Transactions on Instrumentation and Measurement 38, no. 6 (1989): 1139–41. http://dx.doi.org/10.1109/19.46415.
Full textAggoun, A., M. K. Ibrahim, and A. Ashur. "Bit-level pipelined digit-serial array processors." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 7 (July 1998): 857–68. http://dx.doi.org/10.1109/82.700933.
Full textKoç, Çetin K., and Ching Yu Hung. "Bit-level systolic arrays for modular multiplication." Journal of VLSI signal processing systems for signal, image and video technology 3, no. 3 (September 1991): 215–23. http://dx.doi.org/10.1007/bf00925832.
Full textRatan, Ram, and Arvind Yadav. "Security Analysis of Bit plane Level Image Encryption Schemes." Defence Science Journal 71, no. 2 (March 10, 2021): 209–21. http://dx.doi.org/10.14429/dsj.71.15643.
Full textSwords, Sol. "Term-Level Reasoning in Support of Bit-blasting." Electronic Proceedings in Theoretical Computer Science 249 (May 2, 2017): 95–111. http://dx.doi.org/10.4204/eptcs.249.7.
Full textMcWhirter, J., D. Wood, K. Wood, R. Evans, J. McCanny, and A. McCabe. "Multibit convolution using a bit level systolic array." IEEE Transactions on Circuits and Systems 32, no. 1 (January 1985): 95–99. http://dx.doi.org/10.1109/tcs.1985.1085589.
Full textZhang, Mu, Kui Cai, Qin Huang, and Shuai Yuan. "On Bit-Level Decoding of Nonbinary LDPC Codes." IEEE Transactions on Communications 66, no. 9 (September 2018): 3736–48. http://dx.doi.org/10.1109/tcomm.2018.2827994.
Full textKankaala, K., T. Ala-Nissila, and I. Vattulainen. "Bit-level correlations in some pseudorandom number generators." Physical Review E 48, no. 6 (December 1, 1993): R4211—R4214. http://dx.doi.org/10.1103/physreve.48.r4211.
Full textChang, L. W., and J. H. Lin. "A bit-level systolic array for median filter." IEEE Transactions on Signal Processing 40, no. 8 (1992): 2079–83. http://dx.doi.org/10.1109/78.150009.
Full textHonjo, T., K. Tanaka, and T. Nakamizo. "Bit level Systolic Implementation on LMS adaptive filter." Proceedings of the ISCIE International Symposium on Stochastic Systems Theory and its Applications 1995 (May 5, 1995): 1–6. http://dx.doi.org/10.5687/sss.1995.1.
Full textNayak, S. S., M. N. Murty, and H. Panda. "Bit-level systolic implementation of discrete orthogonal transforms." Signal Processing 81, no. 11 (November 2001): 2437–43. http://dx.doi.org/10.1016/s0165-1684(01)00021-4.
Full textJullien, G. A., W. C. Miller, R. Grondin, L. Del Pup, S. S. Bizzan, and Dapeng Zhang. "Dynamic computational blocks for bit-level systolic arrays." IEEE Journal of Solid-State Circuits 29, no. 1 (1994): 14–22. http://dx.doi.org/10.1109/4.272090.
Full textLu, Yang, Jun Xie, Hang Li, and Huijuan Cui. "GOP-level bit allocation using reverse dynamic programming." Tsinghua Science and Technology 14, no. 2 (April 2009): 183–88. http://dx.doi.org/10.1016/s1007-0214(09)70028-8.
Full textLukac, Rastislav, and Konstantinos N. Plataniotis. "Bit-level based secret sharing for image encryption." Pattern Recognition 38, no. 5 (May 2005): 767–72. http://dx.doi.org/10.1016/j.patcog.2004.11.010.
Full textHarrison, J. A., K. J. Blow, and A. J. Poustie. "All-optical bit-level retiming and jitter suppression." Optics Communications 240, no. 1-3 (October 2004): 221–26. http://dx.doi.org/10.1016/j.optcom.2004.06.015.
Full textBickel, Jessica E., Mina Khan, and Katherine E. Aidala. "A multi-level single-bit data storage device." Journal of Applied Physics 115, no. 17 (May 7, 2014): 17D511. http://dx.doi.org/10.1063/1.4867603.
Full textWu, Cheng-Wen, and Ming-Kwang Chang. "Bit-level systolic arrays for finite-field multiplications." Journal of VLSI signal processing systems for signal, image and video technology 10, no. 1 (June 1995): 85–92. http://dx.doi.org/10.1007/bf02407028.
Full textEl-Aasser, Minar, Phoebe Edward, Mohamed Mandour, Mohamed Ashour, and Tallal Elshabrawy. "A comprehensive hybrid bit-level and packet-level LoRa-LPWAN simulation model." Internet of Things 14 (June 2021): 100386. http://dx.doi.org/10.1016/j.iot.2021.100386.
Full textSanghun Park and Kiyoung Choi. "Performance-driven high-level synthesis with bit-level chaining and clock selection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 2 (2001): 199–212. http://dx.doi.org/10.1109/43.908436.
Full textBarannik, Vladimir, Yuriy Ryabukha, Pavlo Gurzhiy, Vitaliy Tverdokhlib, and Igor Shevchenko. "TRANSFORMANTS BIT REPRESENTATION ENCODING WITHIN VIDEO BIT RATE CONTROL." Information systems and technologies security, no. 1 (1) (2019): 52–56. http://dx.doi.org/10.17721/ists.2019.1.52-56.
Full textXue, Linlin, Jianhong Lv, and Zhongpeng Wang. "Performance Enhancement of Bit-Level XOR Compressed Image OFDM Transmission Systems." Mobile Information Systems 2022 (August 27, 2022): 1–12. http://dx.doi.org/10.1155/2022/4364706.
Full textSeo, Hwajeong, Hyunjun Kim, Kyoungbae Jang, Hyeokdong Kwon, Minjoo Sim, Gyeongju Song, and Siwoo Uhm. "Compact Implementation of ARIA on 16-Bit MSP430 and 32-Bit ARM Cortex-M3 Microcontrollers." Electronics 10, no. 8 (April 11, 2021): 908. http://dx.doi.org/10.3390/electronics10080908.
Full textSingha, Jayashree, Saikat Jana, and Souvik Singha. "Encoding Algorithm using Bit Level Encryption and Decryption Technique." International Journal of Computer Applications 160, no. 2 (February 15, 2017): 23–26. http://dx.doi.org/10.5120/ijca2017912975.
Full textTiwari, Shashwat, Ayushi Lal, Shivani Agarwal, Ayush Kumar, Anupam Singh, and Nitin Arora. "Novel bit-level Adaptive and Asymmetric Data Compression Technique." International Journal of Computer Applications 177, no. 35 (February 17, 2020): 14–17. http://dx.doi.org/10.5120/ijca2020919832.
Full textKito, Nobutaka, and Kazuyoshi Takagi. "An RSFQ flexible-precision multiplier utilizing bit-level processing." Journal of Physics: Conference Series 1975, no. 1 (July 1, 2021): 012025. http://dx.doi.org/10.1088/1742-6596/1975/1/012025.
Full textHubballi, Neminath, and Mayank Swarnkar. "$BitCoding$ : Network Traffic Classification Through Encoded Bit Level Signatures." IEEE/ACM Transactions on Networking 26, no. 5 (October 2018): 2334–46. http://dx.doi.org/10.1109/tnet.2018.2868816.
Full textChung-Chin Lu and Sy-Hann Huang. "On bit-level trellis complexity of Reed-Muller codes." IEEE Transactions on Information Theory 41, no. 6 (1995): 2061–64. http://dx.doi.org/10.1109/18.476337.
Full textBenkrid, Khaled. "New bit-level algorithm for general purpose median filtering." Journal of Electronic Imaging 12, no. 2 (April 1, 2003): 263. http://dx.doi.org/10.1117/1.1557153.
Full textVardy, A., and Y. Be'ery. "Bit-level soft-decision decoding of Reed-Solomon codes." IEEE Transactions on Communications 39, no. 3 (March 1991): 440–44. http://dx.doi.org/10.1109/26.79287.
Full textPetkov, Nikolai, and Fridrich Sloboda. "A bit-level systolic array for digital contour smoothing." Parallel Computing 12, no. 3 (December 1989): 301–13. http://dx.doi.org/10.1016/0167-8191(89)90088-4.
Full textChang, Long-Wen, and Ming-Chang Wu. "A bit level systolic array for Walsh-Hadamard transforms." Signal Processing 31, no. 3 (April 1993): 341–47. http://dx.doi.org/10.1016/0165-1684(93)90091-n.
Full textKnowles, S. C., J. G. McWhirter, R. F. Woods, and J. V. McCanny. "Bit-Level systolic architectures for high performance IIR filtering." Journal of VLSI signal processing systems for signal, image and video technology 1, no. 1 (August 1989): 9–24. http://dx.doi.org/10.1007/bf00932062.
Full textWoods, Roger F., John V. McCanny, and John G. McWhirter. "From Bit Level Systolic Arrays to HDTV Processor Chips." Journal of Signal Processing Systems 53, no. 1-2 (October 4, 2007): 35–49. http://dx.doi.org/10.1007/s11265-007-0132-z.
Full textHu, Z., and G. A. King. "A bit-level systolic implementation of the median filter." Microprocessors and Microsystems 19, no. 4 (January 1995): 185–86. http://dx.doi.org/10.1016/0141-9331(95)91857-z.
Full textAit-Boudaoud, D., M. K. Ibrahim, and B. R. Hayes-Gill. "Novel cell architecture for bit level systolic arrays multiplication." IEE Proceedings E Computers and Digital Techniques 138, no. 1 (1991): 21. http://dx.doi.org/10.1049/ip-e.1991.0003.
Full textUm, Junhyung, and Taewhan Kim. "Optimal bit-level arithmetic optimisation for high-speed circuits." Electronics Letters 36, no. 5 (2000): 405. http://dx.doi.org/10.1049/el:20000337.
Full textHoekstra, J. "Junction charge-coupled devices for bit-level systolic arrays." IEE Proceedings G (Electronic Circuits and Systems) 134, no. 4 (1987): 194. http://dx.doi.org/10.1049/ip-g-1.1987.0027.
Full textLin, Yi-Nan, Wei-Wen Hung, Tsan-Jieh Chen, and Erl-Huei Lu. "Modeling the bit-level stochastic correlation for turbo decoding." Computer Communications 29, no. 18 (November 2006): 3856–62. http://dx.doi.org/10.1016/j.comcom.2006.06.023.
Full textLi, Zhen, Changgen Peng, Weijie Tan, and Liangrong Li. "A Novel Chaos-Based Color Image Encryption Scheme Using Bit-Level Permutation." Symmetry 12, no. 9 (September 11, 2020): 1497. http://dx.doi.org/10.3390/sym12091497.
Full textHu, Yingchun, Simin Yu, and Zeqing Zhang. "On the Cryptanalysis of a Bit-Level Image Chaotic Encryption Algorithm." Mathematical Problems in Engineering 2020 (August 3, 2020): 1–15. http://dx.doi.org/10.1155/2020/5747082.
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