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Journal articles on the topic 'BIST memory'

Author: Grafiati

Published: 21 July 2022

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1

PARK, Youngkyu, Jaeseok PARK, Taewoo HAN, and Sungho KANG. "An Effective Programmable Memory BIST for Embedded Memory." IEICE Transactions on Information and Systems E92-D, no. 12 (2009): 2508–11. http://dx.doi.org/10.1587/transinf.e92.d.2508.

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2

V.M, Diksha. "Architecture of BIST for Memory Testing." International Journal for Research in Applied Science and Engineering Technology 7, no. 9 (September 30, 2019): 1023–26. http://dx.doi.org/10.22214/ijraset.2019.9146.

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3

Shauchenka, Mikalai. "Address Sequence Generator for Memory BIST." International Journal of Computer Science and Engineering 6, no. 11 (November 25, 2019): 55–59. http://dx.doi.org/10.14445/23488387/ijcse-v6i11p112.

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4

Daniel, Philemon, and Rajeevan Chandel. "A Flexible Programmable Memory BIST Architecture." IETE Journal of Education 51, no. 2-3 (May 2010): 67–74. http://dx.doi.org/10.1080/09747338.2010.10876069.

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5

Kim, Ilwoong, Woosik Jeong, Dongho Kang, and Sungho Kang. "Fully Programmable Memory BIST for Commodity DRAMs." ETRI Journal 37, no. 4 (August 1, 2015): 787–92. http://dx.doi.org/10.4218/etrij.15.0115.0040.

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6

, Dr. K Deepti, P. Aishwarya. "Design and Implementation of FSM Based MBIST using March Algorithm." International Journal for Modern Trends in Science and Technology, no. 8 (August 5, 2020): 18–21. http://dx.doi.org/10.46501/ijmtst060804.

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The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms to detect the faults in memory BIST architecture.The implementation of Memory BIST is done using Finite state machine model. The design of memory BIST is accomplished using Xilinx Vivado IDE for 32X8 memory.

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7

Imocha Singh, Nongthombam, and Prashant V. Joshi. "A Brief Review for Semiconductor Memory Testing Based on BIST Techniques." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 98. http://dx.doi.org/10.14419/ijet.v7i3.1.16807.

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With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.

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8

Sungju, Park, Youn Donkyu, Kim Taehyung, Kang Sangwon, Oh Heekuk, Doh Kyunggoo, and Moon Young Shik. "Microcode-Based Memory BIST Implementing Modified March Algorithms." Journal of the Korean Physical Society 40, no. 4 (April 1, 2002): 749. http://dx.doi.org/10.3938/jkps.40.749.

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9

Savir, Jacob. "BIST Analysis of an Embedded Memory Associated Logic." VLSI Design 12, no. 4 (January 1, 2001): 563–78. http://dx.doi.org/10.1155/2001/91710.

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Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

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10

Park, Youngkyu. "A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory." ETRI Journal 35, no. 5 (October 1, 2013): 808–18. http://dx.doi.org/10.4218/etrij.13.0112.0717.

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11

Praneeth, B. V. S. Sai. "Finite State Machine based Programmable Memory Built-in Self-Test." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 3805–9. http://dx.doi.org/10.22214/ijraset.2021.35875.

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We propose a methodology to design a Finite State Machine(FSM)-based Programmable Memory Built-In Self Test (PMBIST) which includes a planned procedure for Memory BIST which has a controller to select a test algorithm from a fixed set of algorithms that are built in the memory BIST. In general, it is not possible to test all the different memory modules present in System-on-Chip (SoC) with a single Test algorithm. Subsequently it is desirable to have a programmable Memory BIST controller which can execute multiple test algorithms. The proposed Memory BIST controller is designed as a FSM (Finite State Machine) written in Verilog HDL and this scheme greatly simplifies the testing process and it achieves a good flexibility with smaller circuit size compared with Individual Testing designs. We have used March test algorithms like MATS+, March X, March C- to build the project.

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12

Jidin, Aiman Zakwan, Razaidi Hussin, Lee Weng Fook, Mohd Syafiq Mispan, and Loh Wan Ying. "Automatic generation of user-defined test algorithm description file for memory BIST implementation." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 2 (July 1, 2022): 103. http://dx.doi.org/10.11591/ijres.v11.i2.pp103-114.

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Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.

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13

Mamikonyan, Narek, Suren Abazyan, and Vakhtang Janpoladov. "Multi-Memory Grouping Wrapper with Top Level BIST Algorithm." OALib 07, no. 05 (2020): 1–7. http://dx.doi.org/10.4236/oalib.1106294.

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14

J U, Drusya, and S. Prabu Venkateswaran. "Memory less Rotation Based BIST with Low Area Overhead." IOSR journal of VLSI and Signal Processing 4, no. 2 (2014): 12–17. http://dx.doi.org/10.9790/4200-04231217.

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15

Park, Youngkyu, Inhyuk Choi, and Sungho Kang. "IEEE std. 1500 based an Efficient Programmable Memory BIST." Journal of the Institute of Electronics Engineers of Korea 50, no. 2 (February 25, 2013): 114–21. http://dx.doi.org/10.5573/ieek.2013.50.2.114.

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16

MIYAZAKI, M. "A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips." IEICE Transactions on Information and Systems E89-D, no. 4 (April 1, 2006): 1490–97. http://dx.doi.org/10.1093/ietisy/e89-d.4.1490.

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17

Lin, Zhiting, Chunyu Peng, and Kun Wang. "A Novel Controllable BIST Circuit for embedded SRAM." Open Electrical & Electronic Engineering Journal 10, no. 1 (January 29, 2016): 1–10. http://dx.doi.org/10.2174/1874129001610010001.

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With increasingly stringent requirements for memory test, the complexity of the test algorithm is increasing. This will make BIST (Build-In-Self-Test) circuit more complex and the area of BIST circuit larger. This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testing operation modes. It controls the test patterns with three additional input ports. And it indicates the algorithm progress, the test result and the number of fails with three output ports. To achieve test patterns generation, analy-sis and test results recording, the proposed BIST circuit contains five internal functional modules, which are Address Gener-ator, Control Generator, Data Generator, Data Comparator and Fail Accumulator. The test patterns of the proposed BIST cir-cuit are controlled by external signals. It is not only suitable for any existing march algorithms but also leaves room for ex-tension if needed.

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18

Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.

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This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distributed RAM mode of the memory block, the TPG based on FSM is designed to provide March C-testing patterns. Besides, the comparator-based output response analyzer (ORA) and the cascaded ORA scan chain are used to locate the faulty CLB and propagate the comparison output in every row. Finally, fault-injection experiment results verify its ability to detect and diagnose multiple faulty CLBs in faulty FPGAs.

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19

Savir, Jacob. "BIST-Based Fault Diagnosis in the Presence of Embedded Memories." VLSI Design 12, no. 4 (January 1, 2001): 487–500. http://dx.doi.org/10.1155/2001/32515.

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An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

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20

Parvathi, M., N. Vasantha, and K. Satya Prasad. "BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (March 1, 2018): 1. http://dx.doi.org/10.11591/ijres.v7.i1.pp1-11.

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One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

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21

Yin, Shi Rong, and Chao Tao Liu. "A BIST Structure for ADC in Mixed-Signal SOC." Applied Mechanics and Materials 278-280 (January 2013): 950–53. http://dx.doi.org/10.4028/www.scientific.net/amm.278-280.950.

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A BIST structure for ADC test in Mixed-Signal SOC to characterize both the dynamic and static parameters was presented. A Sigma-Delta modulation based sinewave generator was built on the chip. The frequency, amplitude and phase of the sinusoidal signal can be adjusted through proper selecting generator parameters which are stored in ADC WBR. The response analyzer was built up from the memory and computational resource in the SOC.

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22

Singh, Balwinder, Arun Khosla, and Sukhleen Bindra Narang. "Area Overhead and Power Analysis of March Algorithms for Memory BIST." Procedia Engineering 30 (2012): 930–36. http://dx.doi.org/10.1016/j.proeng.2012.01.947.

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23

Mukherjee, Nilanjan, Artur Pogiel, Janusz Rajski, and Jerzy Tyszer. "High Volume Diagnosis in Memory BIST Based on Compressed Failure Data." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 3 (March 2010): 441–53. http://dx.doi.org/10.1109/tcad.2010.2041852.

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24

Yang, W., and R. Guo. "Efficient Failure Data Collection for Memory BIST Diagnosis in Production Test." ECS Transactions 52, no. 1 (March 8, 2013): 793–98. http://dx.doi.org/10.1149/05201.0793ecst.

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25

Harutyunyan, Gurgen, Samvel Shoukourian, and Yervant Zorian. "Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 3 (March 2019): 562–75. http://dx.doi.org/10.1109/tcad.2018.2818688.

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26

Harutyunyan, Gurgen, Aram Hakhumyan, Samvel Shoukourian, Valery A. Vardanian, and Yervant Zorian. "Symmetry Measure for Memory Test and Its Application in BIST Optimization." Journal of Electronic Testing 27, no. 6 (September 9, 2011): 753–66. http://dx.doi.org/10.1007/s10836-011-5251-6.

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27

Wen-Ben Jone, Der-Chen Huang, and S. R. Das. "An efficient BIST method for non-traditional faults of embedded memory arrays." IEEE Transactions on Instrumentation and Measurement 52, no. 5 (October 2003): 1381–90. http://dx.doi.org/10.1109/tim.2003.818546.

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28

Kerzérho, V., S. Bernard, P. Cauvet, and J. M. Janik. "A First Step for an INL Spectral-Based BIST: The Memory Optimization." Journal of Electronic Testing 22, no. 4-6 (December 2006): 351–57. http://dx.doi.org/10.1007/s10836-006-0186-z.

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29

Lu, Shyue-Kung, Yuang-Cheng Hsiao, Chia-Hsiu Liu, and Chun-Lin Yang. "Low-Power Built-In Self-Test Techniques for Embedded SRAMs." VLSI Design 2007 (October 29, 2007): 1–6. http://dx.doi.org/10.1155/2007/67019.

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The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL) architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

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30

Huang, D. C., and W. B. Jone. "A parallel transparent BIST method for embedded memory arrays by tolerating redundant operations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 5 (May 2002): 617–28. http://dx.doi.org/10.1109/43.998632.

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31

Zhang, Lijun, Ziou Wang, Youzhong Li, and Lingfeng Mao. "A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit." IETE Journal of Research 63, no. 4 (February 17, 2017): 473–81. http://dx.doi.org/10.1080/03772063.2017.1285259.

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32

Kumar Ojha, Sunil, O. P. Singh, G. R. Mishra, and P. R. Vaya. "An Efficient Use of Memory Grouping Algorithm for Implementation of BIST in Self Test." Journal of Engineering and Applied Sciences 14, no. 8 (December 31, 2019): 2695–700. http://dx.doi.org/10.36478/jeasci.2019.2695.2700.

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33

Nakamura, Y., T. Clouqueur, K. K. Saluja, and H. Fujiwara. "Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 7 (July 2007): 790–800. http://dx.doi.org/10.1109/tvlsi.2007.899235.

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34

Kumar, Mahesh. "An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]." American Journal of Electrical and Computer Engineering 3, no. 1 (2019): 38. http://dx.doi.org/10.11648/j.ajece.20190301.15.

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35

Voyiatzis, Ioannis. "A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences." VLSI Design 2008 (March 17, 2008): 1–8. http://dx.doi.org/10.1155/2008/680157.

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Test set embedding built-in self test (BIST) schemes are a class of pseudorandom BIST techniques where the test set is embedded into the sequence generated by the BIST pattern generator, and they displace common pseudorandom schemes in cases where reverse-order simulation cannot be applied. Single-seed embedding schemes embed the test set into a single sequence and demand extremely small hardware overhead since no additional control or memory to reconfigure the test pattern generator is required. The challenge in this class of schemes is to choose the best pattern generator among various candidate configurations. This, in turn, calls for a need to evaluate the location of each test pattern in the sequence as fast as possible, in order to try as many candidate configurations as possible for the test pattern generator. This problem is known as the test vector-embedding problem. In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(1). The applicability of the presented method for embedding test sets for the testing of real-world circuits is investigated through experimental results in some well-known benchmarks; comparisons with previously proposed schemes indicate that comparable test lengths are achieved, while the time required for the calculations is accelerated by more than 30 times.

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36

Pan, Hong Bo, Ming Xin Song, Xing Jin, and Jing Hua Yin. "Full Scan Structure Application in the Design of 16 Bit MCU." Advanced Materials Research 981 (July 2014): 78–81. http://dx.doi.org/10.4028/www.scientific.net/amr.981.78.

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A design project of 16 bit RISC MCU with full scan structure by the tool of SYNOPSYSTM DFT COMPILER. The flip-flops can be linked into the chains; the memory modules in the MCU were tested by the technology of BIST; and the circuits were tested by the test vectors by ATPG. The chip test circuit include 8 chains, and cover rate can reach at 99.20%.

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37

Vithya, G., and P. Krishnakumar. "An Efficient Ic On chip Test Framework To Embed Tsv Testing In Memory Bist Using Dynamic Technique." International Journal of Business Intelligents 5, no. 1 (June 15, 2016): 16–20. http://dx.doi.org/10.20894/ijbi.105.005.001.004.

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38

Mrozek, Ireneusz, and Vyacheslav Yarmolik. "Two-Run RAM March Testing with Address Decimation." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750031. http://dx.doi.org/10.1142/s0218126617500311.

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Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator.

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39

Jidin, Aiman Zakwan, Razaidi Hussin, Lee Weng Fook, and Mohd Syafiq Mispan. "A review paper on memory fault models and test algorithms." Bulletin of Electrical Engineering and Informatics 10, no. 6 (December 1, 2021): 3083–93. http://dx.doi.org/10.11591/eei.v10i6.3048.

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Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

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40

Pogra, Vivek, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Application." Sensor Letters 18, no. 1 (January 1, 2020): 31–38. http://dx.doi.org/10.1166/sl.2020.4176.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the Internet. The transfer of data between different networks and internet of things (IoT) platform is controlled by IoT platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to the fact that it is designed for IoT applications. It is described in VHDL at RTL level and simulation is done on the Vivado 2016.2.

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41

Liu, Yi Zhuo, Ke Xin Yin, Gang Liu, and Hui Ran Sun. "A DFT Strategy for an Industrial Communications SoC with JTAG." Advanced Materials Research 461 (February 2012): 513–16. http://dx.doi.org/10.4028/www.scientific.net/amr.461.513.

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In this paper a system level DFT strategy with JTAG is presented to test an industrial communication and control SoC . A SoC generally integrates that microprocessor, memories, some function blocks, PLL, D/A, A/D, etc. Cores originating from different sources need different test strategies. The different test techniques are used in testing of core-based SoC system which combines scan chains, Memory-BIST and Boundary-Scan. A SoC test with JTAG architecture is implemented through a real life case (0.18µm, million gates chip). The test pin counts are reduced, test time for board test is shorter and high test coverage is achieved.

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42

Ravichand, S., T. Madhu, and M. Sailaja. "A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage." International Journal of Emerging Research in Management and Technology 6, no. 8 (June 25, 2018): 235. http://dx.doi.org/10.23956/ijermt.v6i8.145.

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In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit. This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.

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43

Mohammad, Imran, and Ramananjaneyulu K. "FPGA Implementation of a 64-Bit RISC Processor Using VHDL." International Journal of Reconfigurable and Embedded Systems (IJRES) 1, no. 2 (July 1, 2012): 59. http://dx.doi.org/10.11591/ijres.v1.i2.pp59-66.

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In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.<em> </em>

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Karthick, R., and M. Sundararajan. "A novel 3-D-IC test architecture-a review." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 579. http://dx.doi.org/10.14419/ijet.v7i1.1.10227.

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Here, this paper completely examines the crosstalk noise of Through-Silicon-Vias (TSVs) in high speed operations by means of a novel 3-Dimensional-IC Test structural design. In order to decline the crosstalk, the fast rise time devices have to be circumvented except they are essential for performance in some certain circuit parts. It must be noted that this system simultaneously examines the TSVs and the memory and does not require spending additional area for a test pattern generator in case of the TSV test. With the intention of reprocessing the test patterns of new-fangled memory BIST, the value of “data” or “address” need to be fixed to some specific values. In accordance with the outcomes of the TSV grouping, here also implemented a high-efficiency, low-area-overhead TSV test structural design. The amount of test cycles essential for the purpose of finding failing TSVs and regulate the fault category effectively than that in related work.

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Karthick, R., and M. Sundararajan. "A novel 3-D-IC test architecture-a review." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 582. http://dx.doi.org/10.14419/ijet.v7i1.1.10228.

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Here, this paper completely examines the crosstalk noise of Through-Silicon-Vias (TSVs) in high speed operations by means of a novel 3-Dimensional-IC Test structural design. In order to decline the crosstalk, the fast rise time devices have to be circumvented except they are essential for performance in some certain circuit parts. It must be noted that this system simultaneously examines the TSVs and the memory and does not require spending additional area for a test pattern generator in case of the TSV test. With the intention of reprocessing the test patterns of new-fangled memory BIST, the value of “data” or “address” need to be fixed to some specific values. In accordance with the outcomes of the TSV grouping, here also implemented a high-efficiency, low-area-overhead TSV test structural design. The amount of test cycles essential for the purpose of finding failing TSVs and regulate the fault category effectively than that in related work.

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Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (September 1, 2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

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Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (June 19, 2022): 971. http://dx.doi.org/10.3390/mi13060971.

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

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VonBergen, Wade, and Madhu Basude. "A High Temp standalone 4MByte Flash memory with SPI Interface for 210C applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000066–71. http://dx.doi.org/10.4071/hitec-2012-tp11.

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This paper covers the internal architecture, testability & performance characterization of Texas Instruments ™ High-Temp 210C 4MByte standalone Flash storage device. It will be available in a 14-pin ceramic dual Flat pack package as well as a Known Good Die (KGD) option. The device is manufactured in TI's 180nm 1.8V flash process with 3.3V IOs. The design implements 8 banks of flash organized into 2M × 16 bits surrounded by a SPI controller. The SPI controller interfaces asynchronously with an internal flash controller. The flash controller is clocked by FCLK, and controls the flash charge pump to access & operate the flash to program, read, erase, validate etc. The SPI controller is responsible for translating and executing the high level SPI protocol commands to the internal flash controller & its registers. A simple and flexible protocol was developed to access the flash array via the SPI supporting various commands and configuration capabilities. Testability of critical parameters for reliable 210C flash operation is ensured with the implementation of an internal test port accessible through a parallel interface (for TI Internal use only). The test port, and a SPI initiated BIST controller are used to provide full & comprehensive characterization of the flash bit cell array, as well as the flash-pump across temperature & frequencies. The form factor, size, and pin out of this flash device is primarily focused on data logging for narrow & space limited extreme harsh environments such as the down-hole drilling industry.

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Querbach, Bruce, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Patrick Yin Chiang, and Joseph Crop. "Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC." IEEE Design & Test 33, no. 1 (February 2016): 59–67. http://dx.doi.org/10.1109/mdat.2015.2445053.

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O.S., Nisha, and Sivasankar K. "Architecture for an efficient MBIST using modified March-y algorithms to achieve optimized communication delay and computational speed." International Journal of Pervasive Computing and Communications 17, no. 1 (January 15, 2021): 135–47. http://dx.doi.org/10.1108/ijpcc-05-2020-0032.

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Purpose In this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified March Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)–based address generator is proposed. Design/methodology/approach Built in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role. Findings With the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. Originality/value To improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.

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