Relevant bibliographies by topics / BIST memory

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'BIST memory'

Author: Grafiati
Published: 21 July 2022

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Journal articles on the topic "BIST memory"

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PARK, Youngkyu, Jaeseok PARK, Taewoo HAN, and Sungho KANG. "An Effective Programmable Memory BIST for Embedded Memory." IEICE Transactions on Information and Systems E92-D, no. 12 (2009): 2508–11. http://dx.doi.org/10.1587/transinf.e92.d.2508.

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V.M, Diksha. "Architecture of BIST for Memory Testing." International Journal for Research in Applied Science and Engineering Technology 7, no. 9 (September 30, 2019): 1023–26. http://dx.doi.org/10.22214/ijraset.2019.9146.

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Shauchenka, Mikalai. "Address Sequence Generator for Memory BIST." International Journal of Computer Science and Engineering 6, no. 11 (November 25, 2019): 55–59. http://dx.doi.org/10.14445/23488387/ijcse-v6i11p112.

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Daniel, Philemon, and Rajeevan Chandel. "A Flexible Programmable Memory BIST Architecture." IETE Journal of Education 51, no. 2-3 (May 2010): 67–74. http://dx.doi.org/10.1080/09747338.2010.10876069.

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Kim, Ilwoong, Woosik Jeong, Dongho Kang, and Sungho Kang. "Fully Programmable Memory BIST for Commodity DRAMs." ETRI Journal 37, no. 4 (August 1, 2015): 787–92. http://dx.doi.org/10.4218/etrij.15.0115.0040.

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, Dr. K Deepti, P. Aishwarya. "Design and Implementation of FSM Based MBIST using March Algorithm." International Journal for Modern Trends in Science and Technology, no. 8 (August 5, 2020): 18–21. http://dx.doi.org/10.46501/ijmtst060804.

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The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms to detect the faults in memory BIST architecture.The implementation of Memory BIST is done using Finite state machine model. The design of memory BIST is accomplished using Xilinx Vivado IDE for 32X8 memory.
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Imocha Singh, Nongthombam, and Prashant V. Joshi. "A Brief Review for Semiconductor Memory Testing Based on BIST Techniques." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 98. http://dx.doi.org/10.14419/ijet.v7i3.1.16807.

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With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.
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Sungju, Park, Youn Donkyu, Kim Taehyung, Kang Sangwon, Oh Heekuk, Doh Kyunggoo, and Moon Young Shik. "Microcode-Based Memory BIST Implementing Modified March Algorithms." Journal of the Korean Physical Society 40, no. 4 (April 1, 2002): 749. http://dx.doi.org/10.3938/jkps.40.749.

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Savir, Jacob. "BIST Analysis of an Embedded Memory Associated Logic." VLSI Design 12, no. 4 (January 1, 2001): 563–78. http://dx.doi.org/10.1155/2001/91710.

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Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].
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Park, Youngkyu. "A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory." ETRI Journal 35, no. 5 (October 1, 2013): 808–18. http://dx.doi.org/10.4218/etrij.13.0112.0717.

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Dissertations / Theses on the topic "BIST memory"

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Vykydal, Lukáš. "Mikroprogramem řízený RAM BIST." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316440.

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The goal of this work is to understand types of defects in semiconductor memories and algorithms for their testing. In the second part the work describes design and implementation of programmable BIST controller with small digital block size requirments.
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Boutobza, Slimane. "Outils de génération de structures BIST/BISR pour mémoires." Grenoble INPG, 2002. http://www.theses.fr/2002INPG0166.

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Les Systems on Chip (SoC) actuels intègrent en général une grande proportion de mémoires enterrées. Ces mémoires sont de plus en plus denses et occupent des surfaces très importantes dans le circuit (jusqu'à 80%). Ces mémoires peuvent présenter un grand taux de défauts affectant ainsi d'une façon conséquente le rendement total du circuit. La qualité de la mémoire et donc cruciale pour la qualité de l'ensemble du circuit. D'autre part, la réduction du coût du développement passe par la réduction du coût du test. Enfin, le management de la complexité de test des structures de plus en plus complexes (e. G. , il existe actuellement des SoC contenant plus de 400 mémoires enterrées !), ne peut se faire d'une manière efficace sans la disposition et l'intégration des techniques de test les plus avancées. La clé du succès d'une bonne stratégie de test passe par les exigences d'une qualité élevée du test et de son automatisation. À travers la première partie des travaux réalisés dans cette thèse, nous avons tenté de répondre à l'exigence de la qualité de test en présentant un ensemble assez diversifié de solutions de test intégré (BIST) pour mémoires. Ces solutions couvrent les différents types de test d'une mémoire: test de caractérisation et de débuggage des processus de fabrication instables, test de production, test durant la phase opérationnelle et test d'analyse des défauts. Ces solutions permettent de palier aux limitations des techniques BIST existantes, telles que le meilleur compromis couverture de fautes/coût en surface et la garantie d'un test à la fréquence nominale. Ce dernier point a été pris en compte en proposant une technique d'optimisation temporelle (appelée Rapid BIST) des architectures BISTs élaborées, qui permet une réduction du temps de test et une meilleure couverture de faute en assurant un test à la fréquence nominale même pour les mémoires très rapides (afin de couvrir les fautes de délai). Ces différents avantages sont offerts sans pour autant négliger le coût additionnel en surface. Nous avons également développé une technique CBISR (Column BISR) qui permet d'assurer un rendement de production élevé et une durée de vie prolongée en particulier pour les mémoires de grandes tailles. La seconde partie de cette thèse adressait le problème de la génération automatique des solutions élaborées en concevant et implémentant un outil de synthèse de structures BIST/BISR pour mémoires. Cet outil innove à la fois par l'approche de son implémentation et par les fonctionnalités offertes. Afin de permettre une implémentation efficace, il utilise une approche originale de synthèse de BIST pour les tests de mémoires. Cette approche est basée sur la notion de perturbation par rapport à un axe médian représenté par les tests Marchs. Hormis quelques tests électriques, cette approche de synthèse permet de synthétiser (sur le tas) n'importe quel algorithme de test pour mémoires en une architecture BIST compacte. D'autre part, cette approche est suffisamment flexible pour pouvoir supporter la synthèse des algorithmes de test qui pourront être développés. Il suffit pour cela de supporter leurs perturbations. Les blocs matériels bas niveau sont conçus en utilisant un langage de description spéciale (CHDL) qui est lui-même modélisé sous forme de structure de données écrites dans un langage haut niveau (C++). L'outil implémente un ensemble assez large de solutions BIST/BISR notamment ceux développés dans le cadre de cette thèse. Il offre une indépendance vis à vis de : - La technologie à utiliser, en offrant des descriptions RTL synthétisables. - L'environnement de conception, en générant des scripts de synthèse pour une variété d'outils de synthèse (AMBIT, Design Compiler), et des scripts de simulation pour les simulateurs les plus connus. - Du langage de description de matériel supporté par l'environnement de conception, en décrivant les architectures implémentées dans un langage interne de haut niveau (CHDL) qui pourront ensuite être translatées en langage VHDL et/ou VERILOG. Il offre enfin un mécanisme pour explorer l'espace des solutions en prenant en compte différentes stratégies d'optimisation afin de délivrer l'architecture optimale, suivant le coût en surface, et/ou la fréquence de fonctionnement, et/ou la couverture de faute et/ou la capacité de réparation
Modern Systems on Chip usually include large embedded memories. These memories occupy the largest part of the circuit (up to 80% of the total circuit area). Furthermore, memories are more dense than logic and thus, more prone to faults. Therefore, the quality of the memory is crucial for the overall quality of the chip. On the other hand, the reduction of the development cost passes from the reduction of the test cost. Finally, the management of the test complexity of the increasingly complex structures cannot be made with an effective manner without the provision and integration of the advanced test techniques. In the first part of the present thesis, we try to answer to test quality requirement by presenting various memory Built In Self-Test (BIST) solutions that cover all the tests required for memory: characterization test, production test, field test and defects analysis test. The proposed solutions allow handling the limitations of the existing memory BIST techniques, such as the selection of the best trade-off between fault coverage/area overhead and the guarantee of the at-speed testing. We developed also a CBISR (Column Built In Self Repair) technique that allows a significant yield improvement and a prolonged product life in particular for large memories. The second part of this thesis addresses the problem of the automation of the BIST/BISR solutions generation. This is done by designing and implementing a synthesis tool for memories BIST/BISR. This tool innovates at the same time by its implementation approach and the offered features. In order to allow an effective implementation, it uses an original approach of BIST synthesis of the memory tests. This approach is based on the concept of disturbance by report to a median axis represented by the March tests. Except some electric tests, this synthesis approach allows to synthesize any memory test algorithm. Furthermore, by supporting the disturbances of these algorithms, this approach is flexible enough to allow supporting the synthesis of new test algorithms that could be introduced in the future. It offers finally, a mechanism to explore the solutions space by taking into account various optimization strategies in order to deliver optimal architecture, with respect to area cost, the operation frequency, the fault coverage and the repair efficiency
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Gadde, Priyanka. "A BIST Architecture for Testing LUTs in a Virtex-4 FPGA." University of Toledo / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.

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Zaourar, Lilia Koutchoukali. "Recherche opérationnelle et optimisation pour la conception testable de circuits intégrés complexes." Grenoble, 2010. http://www.theses.fr/2010GRENM055.

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Le travail de cette thèse est à l'interface des dom aines de la recherche opérationnelle et de la micro -électronique. Il traite de l'utilisation des techniques d'optimisation combinatoire pour la DFT (Design For Test) des Circuits Intégrés (CI). Avec la croissance rapide et la complexité des CI actuels, la qualité ainsi que le coût du test sont devenus des paramètres importants dans l'industrie des semi-conducteurs. Afin de s'assurer du bon fonctionnement du CI, l'étape de test est plus que jamais une étape essentielle et délicate dans le processus de fabrication d'un CI. Pour répondre aux exigences du marché, le test doit être rapide et efficace dans la révélation d'éventuels défauts. Pour cela, il devient incontournable d'appréhender la phase de test dès les étapes de conception du CI. Dans ce contexte, la conception testable plus connue sous l'appellation DFT vise à améliorer la testabilité des CI. Plusieurs problèmes d'optimisation et d'aide à la décision découlent de la micro-électronique. La plupart de ces travaux traitent des problèmes d'optimisation combinatoire pour le placement et routage des circuits. Nos travaux de recherche sont à un niveau de conception plus amont, la DFT en présynthèse au niveau transfert de registres ou RTL (Register Transfer Level). Cette thèse se découpe en trois parties. Dans la première partie nous introduisons les notions de bases de recherche opérationnelle, de conception et de test des CI. La démarche suivie ainsi que les outils de résolution utilisés dans le reste du document sont présentés dans cette partie. Dans la deuxième partie, nous nous intéressons au problème de l'optimisation de l'insertion des chaîne s de scan. A l'heure actuelle, le "scan interne" est une des techniques d'amélioration de testabilité ou de DFT les plus largement adoptées pour les circuits intégrés numériques. Il s'agit de chaîner les éléments mémoires ou bascules du circuit de sorte à former des chaînes de scan qui seront considérées pendant la phase de test comme points de contrôle et d'observation de la logique interne du circuit. L'objectif de notre travail est de développer des algorithmes permettant de générer pour un CI donné et dès le niveau RTL des chaînes de scan optimales en termes de surface, de temps de test et de consommation en puissance, tout en respectant des critères de performance purement fonctionnels. Ce problème a été modélisé comme la recherche de plus courtes chaînes dans un graphe pondéré. Les méthodes de résolution utilisées sont basées sur la recherche de chaînes hamiltoniennes de longueur minimale. Ces travaux ont été réalisés en collaboration avec la start-up DeFacTo Technologies. La troisième partie s'intéresse au problème de partage de blocs BIST (Built In Self Test) pour le test des mémoires. Le problème peut être formulé de la façon suivante : étant données des mémoires de différents types et tailles, ainsi que des règles de partage des colliers en série et en parallèle, il s'agit d'identifier des solutions au problème en associant à chaque mémoire un collier. La solution obtenue doit minimiser à la fois la surface, la consommation en puissance et le temps de test du CI. Pour résoudre ce problème, nous avons conçu un prototype nommé Memory BIST Optimizer (MBO). Il est constitué de deux phases de résolution et d'une phase de validation. La première phase consiste à créer des groupes de compatibilité de mémoires en tenant compte des règles de partage et d'abstraction des technologies utilisées. La deuxième phase utilise les algorithmes génétiques pour l'optimisation multi-objectifs afin d'obtenir un ensemble de solutions non dominées. Enfin, la validation permet de vérifier que la solution fournie est valide. De plus, elle affiche l'ensemble des solutions à travers une interface graphique ou textuelle. Cela permet à l'utilisateur de choisir la solution qui lui correspond le mieux. Actuellement, l'outil MBO est intégré dans un flot d'outils à ST-microelectronics pour une utilisation par ses clients
This thesis is a research contribution interfacing operations research and microelectronics. It considers the use of combinatorial optimization techniques for DFT (Design For Test) of Integrated Circuits (IC). With the growing complexity of current IC both quality and cost during manufacturing testing have become important parameters in the semiconductor industry. To ensure proper functioning of the IC, the testing step is more than ever a crucial and difficult step in the overall IC manufacturing process. To answer market requirements, chip testing should be fast and effective in uncovering defects. For this, it becomes essential to apprehend the test phase from the design steps of IC. In this context, DFT techniques and methodologies aim at improving the testability of IC. In previous research works, several problems of optimization and decision making were derived from the micro- electronics domain. Most of previous research contributions dealt with problems of combinatorial optimization for placement and routing during IC design. In this thesis, a higher design level is considered where the DFT problem is analyzed at the Register Transfer Level (RTL) before the logic synthesis process starts. This thesis is structured into three parts. In the first part, preliminaries and basic concepts of operations research, IC design and manufacturing are introduced. Next, both our approach and the solution tools which are used in the rest of this work are presented. In the second part, the problem of optimizing the insertion of scan chains is considered. Currently, " internal scan" is a widely adopted DFT technique for sequential digital designs where the design flip-flops are connected into a daisy chain manner with a full controllability and observability from primary inputs and outputs. In this part of the research work, different algorithms are developed to provide an automated and optimal solution during the generation of an RTL scan architecture where several parameters are considered: area, test time and power consumption in full compliance with functional performance. This problem has been modelled as the search for short chains in a weighted graph. The solution methods used are based on finding minimal length Hamiltonian chains. This work was accomplished in collaboration with DeFacTo Technologies, an EDA start-up close to Grenoble. The third part deals with the problem of sharing BIST (Built In Self Test) blocks for testing memories. The problem can be formulated as follows: given the memories with various types and sizes, and sharing rules for series and parallel wrappers, we have to identify solutions to the problem by associating a wrapper with each memory. The solution should minimize the surface, the power consumption and test time of IC. To solve this problem, we designed a prototype called Memory BIST Optimizer (MBO). It consists of two steps of resolution and a validation phase. The first step creates groups of compatibility in accordance with the rules of abstraction and sharing that depend on technologies. The second phase uses genetic algorithms for multi-objective optimization in order to obtain a set of non dominated solutions. Finally, the validation verifies that the solution provided is valid. In addition, it displays all solutions through a graphical or textual interface. This allows the user to choose the solution that fits best. The tool MBO is currently integrated into an industrial flow within ST-microelectronics
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Johnson, Patricia Lynn. "The Influence of Individual Differences on Emotional Processing and Emotional Memory." Scholar Commons, 2014. https://scholarcommons.usf.edu/etd/5245.

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Emotional material is better remembered than neutral material and some suggest this is reflected in different Event Related potentials (ERPs) to affective stimuli by valence. Inconsistent results may be due to individual differences, specifically the behavioral inhibition/behavioral activation (BIS/BAS) motivational system. This study sought to examine the relationship between motivational systems, emotional memory, and psychophysiological response to emotional pictures. While using EEG recording, subjects were shown 150 affective pictures and given a recall and yes/no recognition task after a 20 and 30-minute delay, respectively. Overall, differences were found by valence, but not consistently based on individual trait. Controlling for arousal and mood, results did not support previous research that suggested high BIS was more responsive to negative pictures while higher BAS was more responsive to positive images. The role of ERP methodology and arousal are discussed, along with future directions.
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Chandran, Pravin Chander. "Design of ALU and Cache memory for an 8 bit microprocessor." Connect to this title online, 2007. http://etd.lib.clemson.edu/documents/1202498822/.

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Sumransub, Parisuth. "Cultural and linguistic adaptation of the BIRT Memory and Information Processing Battery and the Prospective and Retrospective Memory Questionnaire for Thailand." Thesis, University of Glasgow, 2018. http://theses.gla.ac.uk/30623/.

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Pimentel, Sobrinho Alvaro Caetano. "A contribuição do conceito do bit quântico(q-bit) para os fundamentos teóricos da ciência da informação." Universidade Federal do Rio de Janeiro / Instituto Brasileiro de Informação em Ciência e Tecnologia, 2013. http://ridi.ibict.br/handle/123456789/670.

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Made available in DSpace on 2015-10-19T11:49:43Z (GMT). No. of bitstreams: 1 pimentelsobrinho2013.pdf: 2616020 bytes, checksum: abbcfacc53dbab0dc8ddca2f8ac2b67b (MD5) Previous issue date: 2013-03-27
Study about contributions of the concept of quantum bit (q-bit) and analyze the possibilities in quantum computers processing and increase the data storage capacity for devices memory. From the analysis of the q-bit is possible to notice changing in mental and social structures beyond their direct interference in the process of memory as a way of preserving information in different formats. Observations in the contributions from Quantum Mechanics, by measuring process, for Information Science and theoretical-epistemic confluence between the two sciences complemented by some opinions around the issues that still needing answer. Insertion of terms entanglement and superposition that were identified as fundamental to understanding the concept of q-bit is the basis to accept the updates in the concepts, formulations and descriptions established in Information Science
Estudo das contribuições do conceito do bit quântico (q-bit) e suas possibilidades de processamento nos computadores quânticos e de aumento da capacidade de armazenamento dos dados em dispositivos de memória. A partir da análise do q-bit, é possível a percepção das alterações de estruturas mentais e sociais, além de sua interferência direta no processo de memória como meio de preservação de informações sob diversos formatos. Observações das contribuições a Mecânica Quântica para a Ciência da Informação e a confluência teórico epistêmica entre as duas ciências, complementadas por algumas ponderações em torno das questões que ainda necessitam de respostas. Inserção dos termos emaranhamento e superposição de estados identificados como fundamentais para o entendimento do conceito de q-bit. Tais termos são a base para dimensionar as alterações em conceitos, formulações e descrições consagrados na Ciência da Informação. Palavras-chave: Bit quântico
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LI, HANG. "DESIGN OF A 32 BY 32 BIT READ HEAD DEVICE FOR PAGE-ORIENTED OPTICAL MEMORY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037304111.

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Ho, Chi Ming. "Neuropharmacological and neurochemical characterization of memory enhancing effects of bis(12)-huperin, a novel dimeric acetylcholinesterase inhibitor /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?BICH%202002%20HO.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.
Includes bibliographical references (leaves 151-175). Also available in electronic version. Access restricted to campus users.
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Books on the topic "BIST memory"

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Hildon, Karl J. H. The complete Commodore inner space anthology. Milton, Ont: Transactor Pub., 1985.

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Upgrading and repairing PCs. Indianapolis, Indiana: Que Pub., 2010.

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Scott, Mueller. Upgrading and repairing PCs. Indianapolis, Ind: Que, 2006.

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Upgrading and Repairing PCs. 2nd ed. Carmel, IN: Que, 1992.

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Upgrading and repairing PCs. Indianapolis, Ind: Que, 1999.

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Upgrading and repairing PCs. 8th ed. Indianapolis, IN: Que, 1997.

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Scott, Mueller. Upgrading and repairing PCs. Carmel, Ind: Que Corp., 1988.

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Scott, Mueller. Upgrading and repairing PCs. Indianapolis, Ind: Que, 2000.

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Upgrading and repairing PCs. Indianapolis, Ind: Que, 2003.

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Upgrading and repairing PCs. 3rd ed. Carmel, IN: Que Corp., 1993.

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Book chapters on the topic "BIST memory"

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Navabi, Zainalabedin. "Memory Testing by Means of Memory BIST." In Digital System Test and Testable Design, 375–91. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_11.

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Yarmolik, V. N., I. V. Bykov, S. Hellebrand, and H. J. Wunderlich. "Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms." In Lecture Notes in Computer Science, 339–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48254-7_23.

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Ghoshal, Bibhas, Subhadip Kundu, Indranil Sengupta, and Santanu Chattopadhyay. "Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip." In Progress in VLSI Design and Test, 343–49. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31494-0_39.

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Veendrick, Harry. "Memory Circuits and IP." In Bits on Chips, 99–123. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-76096-4_6.

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Philipp, Klaus Jan. "Das Grabmal des Porsenna: Rekonstruktionen eines Mythos vom 16. bis 19. Jahrhundert." In Memory & Oblivion, 335–46. Dordrecht: Springer Netherlands, 1999. http://dx.doi.org/10.1007/978-94-011-4006-5_38.

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Dang, Dung, Daniel J. Pack, and Steven F. Barrett. "MSP432 Memory System." In Embedded Systems Design with the Texas Instruments MSP432 32-bit Processor, 191–223. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-031-79889-4_4.

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Masuda, H., H. Pimingstorfer, H. Sato, K. Tsuneno, K. Ichikawa, H. Tobe, H. Miyazawa, et al. "Applied TCAD in Mega-Bits Memory Design." In Simulation of Semiconductor Devices and Processes, 21–24. Vienna: Springer Vienna, 1993. http://dx.doi.org/10.1007/978-3-7091-6657-4_4.

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Alam, Irina, Lara Dolecek, and Puneet Gupta. "Lightweight Software-Defined Error Correction for Memories." In Dependable Embedded Systems, 207–32. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_9.

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AbstractReliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.
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Akavia, Adi, Shafi Goldwasser, and Vinod Vaikuntanathan. "Simultaneous Hardcore Bits and Cryptography against Memory Attacks." In Theory of Cryptography, 474–95. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00457-5_28.

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Song, Yong, Woomin Hwang, Ki-Woong Park, and Kyu Ho Park. "Microscopic Bit-Level Wear-Leveling for NAND Flash Memory." In Lecture Notes in Electrical Engineering, 315–20. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-40675-1_48.

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Conference papers on the topic "BIST memory"

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WonGi Hong, JungDai Choi, and Hoon Chang. "A programmable memory BIST for embedded memory." In 2008 International SoC Design Conference (ISOCC). IEEE, 2008. http://dx.doi.org/10.1109/socdc.2008.4815717.

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Lotfi, Atieh, Parisa Kabiri, and Zainalabedin Navabi. "Configurable architecture for memory BIST." In Test Symposium (EWDTS). IEEE, 2011. http://dx.doi.org/10.1109/ewdts.2011.6116571.

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Wu, Yuejian, and Andre Ivanov. "Low Power SoC Memory BIST." In 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE, 2006. http://dx.doi.org/10.1109/dft.2006.39.

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Fradi, Aymen, Michael Nicolaidis, and Lorena Anghel. "Memory BIST with address programmability." In 2011 IEEE 17th International On-Line Testing Symposium (IOLTS 2011). IEEE, 2011. http://dx.doi.org/10.1109/iolts.2011.5993815.

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Oehler, Philipp, Alberto Bosio, Giorgio di Natale, and Sybille Hellebrand. "A Modular Memory BIST for Optimized Memory Repair." In 2008 14th IEEE International On-Line Testing Symposium (IOLTS). IEEE, 2008. http://dx.doi.org/10.1109/iolts.2008.30.

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Miyazaki, Masahide, Tomokazu Yoneda, and Hideo Fujiwara. "A memory grouping method for sharing memory BIST logic." In the 2006 conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1118299.1118457.

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Sargsyan, D. "Firmware Generation Architecture for Memory BIST." In 2018 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2018. http://dx.doi.org/10.1109/ewdts.2018.8524853.

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van de Goor, Ad J., Halil Kukner, and Said Hamdioui. "Optimizing memory BIST Address Generator implementations." In Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2011. http://dx.doi.org/10.1109/dtis.2011.5941430.

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Singh, Abhas, Gurram Mahanth Kumar, and Abhijit Aasti. "Controller Architecture for Memory BIST Algorithms." In 2020 IEEE International Students' Conference on Electrical,Electronics and Computer Science (SCEECS). IEEE, 2020. http://dx.doi.org/10.1109/sceecs48394.2020.43.

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Arai, M., K. Iwasaki, M. Nakao, and I. Suzuki. "Hardware Overhead Reduction for Memory BIST." In 2008 IEEE International Test Conference. IEEE, 2008. http://dx.doi.org/10.1109/test.2008.4700690.

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