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Journal articles on the topic 'Binary multiplier'

Author: Grafiati

Published: 28 June 2021

Last updated: 29 July 2025

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1

Padmanabhan, Khamalesh Kumar, Umadevi Seerengasamy, and Abraham Sudharson Ponraj. "High-Speed Grouping and Decomposition Multiplier for Binary Multiplication." Electronics 11, no. 24 (2022): 4202. http://dx.doi.org/10.3390/electronics11244202.

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In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The

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2

Madenda, Sarifuddin, Suryadi Harmanto, and Astie Darmayantie. "New Concept of Universal Binary Multiplication and Its Implementation on FPGA." Journal of Southwest Jiaotong University 56, no. 3 (2021): 124–39. http://dx.doi.org/10.35741/issn.0258-2724.56.3.11.

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This paper proposes the new improvements of signed binary multiplication equation, signed multiplier, and universal multiplier. The proposed multipliers have low complexity algorithms and are easy to implement into software and hardware. Both signed, and universal multipliers are embedded into FPGA by optimizing the use of LUTs (6-LUT and 5-LUT), carry chain Carry4, and fast carry logics: MUXCYs and XORCYs.Each one is implemented as a serial-parallel multiplier and parallel multiplier. The signed multiplier executes four types of multiplication, i.e., between two operands that each one can be

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3

Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quart

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4

Etiemble, Daniel, and Ramzi A. Jaber. "Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers." Asian Journal of Research in Computer Science 16, no. 3 (2023): 103–18. http://dx.doi.org/10.9734/ajrcos/2023/v16i3349.

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The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multipli

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5

Alkurwy, Salah. "A novel approach of multiplier design based on BCD decoder." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (2019): 38–43. https://doi.org/10.11591/ijeecs.v14.i1.pp38-43.

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A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3×3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3×3-bits multiplier circuit is used to implement the 6×6- and 12×12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in ter

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6

Sharma, Virat, and Manju K. Chattopadhyay. "Implementation of Novel 2x2 Vedic Multiplier using QCA Technology." Journal of Physics: Conference Series 2603, no. 1 (2023): 012045. http://dx.doi.org/10.1088/1742-6596/2603/1/012045.

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Abstract Advantages like working at high speed, scalability, and lower power consumption make QCA technology more feasible than modern CMOS technology. QCA Technology uses electrons’ Coulombic interaction and polarization to represent binary information 0 and 1. The present paper proposes a novel XOR Gate and a Half Adder design and uses them to implement a new 2x2 Vedic Multiplier on QCA technology. A 2x2 Vedic Multiplier multiplies two inputs, of two bits each, using Urdhva-Tiryakbhyam Vedic Sutra. The proposed circuit has a reduced cell count and Quantum cost compared Co-planar Vedic Multip

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7

Rajkumar, K. "Design and optimization of MSI-enabled multi-precision binary multiplier architecture." i-manager's Journal on Circuits and Systems 11, no. 2 (2023): 27. http://dx.doi.org/10.26634/jcir.11.2.20397.

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Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113-bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of float

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8

Al-Nounou, Abd Al-Rahman, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel. "FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells." JUCS - Journal of Universal Computer Science 28, no. (10) (2022): 1030–57. https://doi.org/10.3897/jucs.86282.

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes c

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9

Kalimoldayev, M., S. Tynymbayev, M. Ibraimov, M. Magzom, Y. Kozhagulov, and T. Namazbayev. "PIPELINE MULTIPLIER OF POLYNOMIALS MODULO WITH ANALYSIS OF HIGH-ORDER BITS OF THE MULTIPLIER." BULLETIN 386, no. 4 (2020): 13–20. http://dx.doi.org/10.32014/2020.2518-1467.98.

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Among public-key cryptosystems, cryptosystems built on the basis of a polynomial system of residual classes are special. Because in these systems, arithmetic operations are performed at high speed. There are many algorithms for encrypting and decrypting data presented in the form of polynomials. The paper considers data encryption based on the multiplication of polynomials modulo irreducible polynomials. In such a multiplier, the binary image of a multiply polynomial can serve as a fragment of encrypted text. The binary image of the multiplier polynomial is the secret key and the binary repres

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10

Al-Nounou, Abd Al-Rahman, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel. "FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells." JUCS - Journal of Universal Computer Science 28, no. 10 (2022): 1030–57. http://dx.doi.org/10.3897/jucs.86282.

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes c

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11

Kogut, Ihor, Volodymyr Hryha, Bohdan Dzundza, Liudmyla Hryha, and Iryna Hatala. "Research and design of a matrix multiplier on FPGA." Advances in Cyber-Physical Systems 10, no. 1 (2025): 10–15. https://doi.org/10.23939/acps2025.01.010.

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This paper presents a comprehensive investi- gation and hardware implementation of a multi-bit Brawn matrix multiplier architecture. The research focuses on analyzing the system characteristics of binary multipliers realized with both conventional and optimized full and half adders. Particular attention has been given to the applicability of such multipliers within arithmetic logic units (ALUs) for vector and scalar processing architectures. Analytical models have been formulated to quantify hardware resource utilization and computational latency across various logic base configurations. The p

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12

Kumar, Harish, Muhammad Rashid, Ahmed Alhomoud, Sikandar Zulqarnain Khan, Ismail Bahkali, and Saud S. Alotaibi. "A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves." Applied Sciences 12, no. 9 (2022): 4312. http://dx.doi.org/10.3390/app12094312.

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This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most

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13

Kumar, Harish, Muhammad Rashid, Ahmed Alhomoud, Sikandar Zulqarnain Khan, Ismail Bahkali, and Saud S. Alotaibi. "A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves." Applied Sciences 12, no. 9 (2022): 4312. http://dx.doi.org/10.3390/app12094312.

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This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most

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14

Shetty, P. Akshatha, and Dr Kiran V. "Area Efficient Modified Array Multiplier." Journal of University of Shanghai for Science and Technology 23, no. 09 (2021): 288–91. http://dx.doi.org/10.51201/jusst/21/09531.

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Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

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15

Choubey, Abhishek, and Shruti Bhargava Choubey. "An area-delay efficient Radix-8 12x12 Booth multiplier in CMOS for ML accelerator." ITM Web of Conferences 74 (2025): 02007. https://doi.org/10.1051/itmconf/20257402007.

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The multiplier is a significant module of graphics processing units (GPUs) and digital signal processing (DSP). These applications need low power consumption. This paper proposes a low-power radix-8 12-by-12 Booth multiplier. The proposed radix-8 Booth multiplier is implemented using an optimized Binary to 2-’s complement (B2C), convertor, and optimized multiplexer at each stage of the Booth multiplier architecture. The proposed architecture uses 23% less power and 12% less delay compared to existing architecture. To validate the results, all designs are synthesized using Cadence CMOS technolo

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16

Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of parti

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17

Chukkaluru, Ravi Shankar Reddy, Venkata Gopi Kumar Padavala, Manikandan Radhakrishnan, and Bhavana Kuruva. "A high speed and power efficient multiplier based on counterbased stacking." A high speed and power efficient multiplier based on counterbased stacking 32, no. 1 (2023): 98–106. https://doi.org/10.11591/ijeecs.v32.i1.pp98-106.

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High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These pa

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18

Arechabala, J., E. I. Boemo, J. Meneses, F. Moreno, and C. Lopez Barrio. "Full systolic binary multiplier." IEE Proceedings G Circuits, Devices and Systems 139, no. 2 (1992): 188. http://dx.doi.org/10.1049/ip-g-2.1992.0032.

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19

Alkurwy, Salah. "A novel approach of multiplier design based on BCD decoder." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (2019): 38. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp38-43.

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<p><span>A novel approach of multiplier design is presented in this paper. The design </span>idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A<sub>5: </sub>A<sub>0</sub>]<sub>, </sub>using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. C

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20

Faraji, S. Rasoul, Pierre Abillama, and Kia Bazargan. "Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (2022): 1–25. http://dx.doi.org/10.1145/3494570.

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Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in th

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21

Shankar Reddy, Chukkaluru Ravi, Padavala Venkata Gopi Kumar, Radhakrishnan Manikandan, and Kuruva Bhavana. "A high speed and power efficient multiplier based on counter-based stacking." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 1 (2023): 98. http://dx.doi.org/10.11591/ijeecs.v32.i1.pp98-106.

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<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products

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22

Shaik, Maznu. "Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 825–30. https://doi.org/10.22214/ijraset.2024.65922.

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Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably comp

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23

Umer, Usama, Muhammad Rashid, Adel R. Alharbi, Ahmed Alhomoud, Harish Kumar, and Atif Raza Jafri. "An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA." Electronics 11, no. 7 (2022): 1131. http://dx.doi.org/10.3390/electronics11071131.

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This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all

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24

Kumar, P. Sai, R. Swapna, and A. M. Siddhartha. "Design Analysis of Approximate Redundant Binary Multipliers." International Journal of Computer Science and Mobile Computing 11, no. 1 (2022): 74–94. http://dx.doi.org/10.47760/ijcsmc.2022.v11i01.010.

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As innovation scaling is arriving at its cutoff points, new methodologies have been proposed for computational effectiveness. Inexact processing is a promising method for elite execution and low power circuits as utilized in blunder lenient applications. Among surmised circuits, rough number juggling plans have drawn in huge exploration interest. In this paper, the plan of rough excess twofold (RB) multipliers is contemplated. Two inexact Booth encoders and two RB 4:2 blowers dependent on RB (full and half) adders are proposed for the RB multipliers. The inexact plan of the RB-Normal Binary (N

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25

Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault tolerant design for 8-bit Dadda multiplier for neural network applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 3 (2025): 2697. https://doi.org/10.11591/ijece.v15i3.pp2697-2705.

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As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications.

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S, Chaitanya CV, Sundaresan C, P. R. Venkateswaran, and Keerthana Prasad. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 845–52. https://doi.org/10.11591/ijeecs.v13.i2.pp845-852.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multi

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Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.

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Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and developme

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28

Etiemble, Daniel, and Ramzi Jaber. "Comparing Unbalanced and Balanced CNTFET Ternary Adders and Multipliers with the Corresponding Binary Ones." Asian Journal of Research in Computer Science 16, no. 4 (2023): 396–417. http://dx.doi.org/10.9734/ajrcos/2023/v16i4400.

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This paper compares the performance of the ternary adders and multipliers using balanced and unbalanced set of values. We use the 1-trit adders to evaluate the two versions of a 4-trit propagate adder, which are comparedwith a 6-bit corresponding propagate adder. Similarly, we compare the two types of 2*2 trit multipliers with a3*3 bit multiplier. The simulations with a 32-nm Carbon Nanotuble Field-Effect Transistor (CNTFET) technology show that the binary adders and multipliers are more efficient than the ternary ones that compute the same amount of information

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29

Gao, Shuli, Dhamin Al-Khalili, J. M. Pierre Langlois, and Noureddine Chabini. "Efficient Realization of BCD Multipliers Using FPGAs." International Journal of Reconfigurable Computing 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/2410408.

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In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduc

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30

Chaitanya, CVS, C. Sundaresan, R. Venkateswaran P, and Prasad Keerthana. "Design of modified booth based multiplier with carry pre-computation." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 3 (2019): 1048–55. https://doi.org/10.11591/ijeecs.v13.i3.pp1048-1055.

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Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixedpoint arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial

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31

Rashidi, Bahram, and Mohammad Abedini. "Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems." Journal of Circuits, Systems and Computers 28, no. 09 (2019): 1950149. http://dx.doi.org/10.1142/s0218126619501494.

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This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is impleme

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32

Shikha, Singh, and B. Shukla Yagnesh. "Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder." TELKOMNIKA 21, no. 05 (2023): 1139–46. https://doi.org/10.12928/telkomnika.v21i5.24304.

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Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumpti

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Joe, Hounghun, and Youngmin Kim. "Novel Stochastic Computing for Energy-Efficient Image Processors." Electronics 8, no. 6 (2019): 720. http://dx.doi.org/10.3390/electronics8060720.

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Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, we propose an efficient yet simple stochastic computation technique for multipliers and adders by exchanging the wires used for their operation. The results demonstrate that the proposed design reduces the relative error in computation compared with the conventional designs and has smal

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34

Gnanasekaran. "A Fast Serial-Parallel Binary Multiplier." IEEE Transactions on Computers C-34, no. 8 (1985): 741–44. http://dx.doi.org/10.1109/tc.1985.1676620.

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35

Lin, Rong. "A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits." VLSI Design 12, no. 3 (2001): 377–90. http://dx.doi.org/10.1155/2001/97598.

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A highly regular parallel multiplier architecture along with the novel low-power, high-performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8-b

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Abdul-Hadi, Alaa Mohammed, Yousraa Abdul-sahib Saif-aldeen, and Firas Ghanim Tawfeeq. "Performance Evaluation of Scalar Multiplication in Elliptic Curve Cryptography Implementation using Different Multipliers Over Binary Field GF (2233)." Journal of Engineering 26, no. 9 (2020): 45–64. http://dx.doi.org/10.31026/j.eng.2020.09.04.

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This paper presents a point multiplication processor over the binary field GF (2233) with internal registers integrated within the point-addition architecture to enhance the Performance Index (PI) of scalar multiplication. The proposed design uses one of two types of finite field multipliers, either the Montgomery multiplier or the interleaved multiplier supported by the additional layer of internal registers. Lopez Dahab coordinates are used for the computation of point multiplication on Koblitz Curve (K-233bit). In contrast, the metric used for comparison of the implementations of the design

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Rahul Pal. "Novel low PDP CMOS Double-Base Multiplier." Journal of Electrical Systems 20, no. 3 (2024): 6207–15. https://doi.org/10.52783/jes.6683.

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Multipliers play a vital role on digital low power communication system. This present study introduced a new novel strategy of multiplication that can improve speed-power efficiency with a double-based number system multiplier. Designing with a Double base number system multiplier is a suitable alternation due to its two important properties redundancy & sharpness. Extensive simulations has been done to examine the competency of proposed designs under three different test conditions to test . It then compares some of the critical parameters with excising single base number system (i.e. Bin

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Al-Khaleel, Osama, Zakaria Al-Qudah, Mohammad Al-Khaleel, Raed Bani-Hani, Christos Papachristou, and Francis Wolff. "Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication." Journal of Circuits, Systems and Computers 24, no. 02 (2014): 1550019. http://dx.doi.org/10.1142/s021812661550019x.

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This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing

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Vozna, Natalia, Yaroslav Nykolaychuk, and Alina Davletova. "Multi-bit structure improvement methods for multiplier devices of matrix type." Physico-mathematical modelling and informational technologies, no. 32 (July 7, 2021): 80–85. http://dx.doi.org/10.15407/fmmit2021.32.080.

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The article proposes methods for improving the structures of matrix multipliers of multi-digit numbers. Advanced single-bit total adders with paraphrase switched inputs and paraphrase outputs are used, intended as components of high-speed matrix multipliers. Based on the use of such single-bit adders, the structures of matrix multipliers are proposed, characterized by 2 times increased speed, 5 times reduced structural complexity compared to known multipliers based on classical single-bit adders. Optimization of structures of multi-bit matrix multipliers is offered. Comparative estimates of st

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Hänninen, Ismo, and Jarmo Takala. "Binary multipliers on quantum-dot cellular automata." Facta universitatis - series: Electronics and Energetics 20, no. 3 (2007): 541–60. http://dx.doi.org/10.2298/fuee0703541h.

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This article describes the design of ultra-low-power multipliers on quantum dot cellular automata (QCA) nanotechnology, promising very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct structures without the earlier noise problems, verified by the QCA Designer coherence vector simulation. Our results show that the wiring overhead of the arithmetic circuits grows quadratically with the operand word length, and our pipelined array multiplier has linearly better performance-area efficiency than the previously proposed serial-parallel

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Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Digital Image Blending by Inexact Multiplication." Electronics 11, no. 18 (2022): 2868. http://dx.doi.org/10.3390/electronics11182868.

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Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and produc

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Xiao, Shuying. "Enhancing ASIC chip performance through integrated algorithm optimization." Applied and Computational Engineering 38, no. 1 (2024): 274–79. http://dx.doi.org/10.54254/2755-2721/38/20230563.

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As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achie

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Saha, Aloke, Rahul Pal, and Jayanta Ghosh. "Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication." Micro and Nanosystems 12, no. 3 (2020): 149–58. http://dx.doi.org/10.2174/1876402911666190916155445.

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Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simu

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Saundatti, Yasmeen. "Design and Implementation of Four Bit Binary Array Multiplier." International Journal of Scientific Engineering and Research 4, no. 11 (2016): 25–27. https://doi.org/10.70729/ijser151038.

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M, A. Sayyad, and S. Agarkar B. "Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier." Indian Journal of Science and Technology 16, no. 42 (2023): 3727–34. https://doi.org/10.17485/IJST/v16i42.733.

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Abstract <strong>Objectives:</strong> Speed of multiplication in Digital Signal Processing (DSP) applications plays an important role in generating the result quickly. There is scope for reducing the propagation delay in multiplication by designing the multiplier circuit based on the Vedic mathematics (formulas) sutras. This study aims to design the multiplier circuit based on Nikhilam Navatshcaramam Dashath (NND) of Vedic mathematics for improvement in speed, power, and area. <strong>Methods:</strong> The multiplier circuit based on NND method is designed for the multiplier and

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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so

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Baesler, Malte, Sven-Ole Voigt, and Thomas Teufel. "A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA." International Journal of Reconfigurable Computing 2010 (2010): 1–13. http://dx.doi.org/10.1155/2010/357839.

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Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754

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Reddy, K. Swetha, Surabhi Seethai, Akanksha, Meenakshi, and V. Sagar Reddy. "ASIC Implementation of Bit Matrix Multiplier." E3S Web of Conferences 391 (2023): 01028. http://dx.doi.org/10.1051/e3sconf/202339101028.

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In computer science and digital electronics, a bit matrix multiplier (BMM) is a mathematical operation that is used to quickly multiply binary matrices. BMM is a basic component of many computer algorithms and is utilized in fields including machine learning, image processing, and cryptography. BMM creates a new matrix that represents the product of the two input matrices by performing logical AND and XOR operations on each matrix element’s binary value. BMM is a crucial method for large-scale matrix operations since it has a lower computational complexity than conventional matrix multiplicati

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Abdulbaqia, Alaa Ghazi, and Yasir Hashim. "Design and Implementation of General Hardware Binary Multiplier (2ⁿ x 2ⁿ) Bits." Journal of Physics: Conference Series 2312, no. 1 (2022): 012084. http://dx.doi.org/10.1088/1742-6596/2312/1/012084.

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Abstract In this paper, a new general 2n x 2n bits hardware multiplier based on combinatorial has been designed, implemented and analysed. First, a new design for circuit to multiply two binary numbers with 2n bits length, this new design starts with basic 2x2 bits circuit multiplier, n here equal to 1. Then based on this circuit, the 4x4 bits circuit multiplier has been designed. And based on 4x4, the 8x8 bits multiplier has been designed and continually the 16x16 bits multiplier. The final design for general 2nx2n bits multiplier has been presented. All these circuits have been mathematicall

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Utsav, Kumar Malviya. "High-speed radix-10 multiplication using partial shifter adder tree-based convertor." TELKOMNIKA Telecommunication, Computing, Electronics and Control 19, no. 2 (2021): pp. 556~563. https://doi.org/10.12928/TELKOMNIKA.v19i2.14991.

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A radix-10 multiplication is the foremost frequent operations employed by several monetary business and user-oriented applications, decimal multiplier using in state of art digital systems are significantly good but can be upgraded with time delay and area optimization. This work is proposed a more area and time delay optimized new design of overloaded decimal digit set (ODDS) architecture-based radix-10 multiplier for signed numbers. Binary coded decimal (BCD) to binary followed by binary multiplication and finally binary to BCD conversion are 3 major modules employed in radix-10 multiplicati

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