Journal articles on the topic 'Beyond CMOS technologie'
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Mohamed, Khaled Salah. "Work around Moore’s Law: Current and next Generation Technologies." Applied Mechanics and Materials 110-116 (October 2011): 3278–83. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3278.
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Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Materials (High-K, Metal Gate, Strained-Si) ,”More than Moore”:New Interconnects Schemes (3D, NoC, Optical, Wireless), and ”Beyond CMOS” :New Devices (Molecular Computer, Biological computer, Quantum Computer) .
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Thomas, S. G., P. Tomasini, M. Bauer, B. Vyne, Y. Zhang, M. Givens, J. Devrajan, S. Koester, and I. Lauer. "Enabling Moore's Law beyond CMOS technologies through heteroepitaxy." Thin Solid Films 518, no. 6 (January 2010): S53—S56. http://dx.doi.org/10.1016/j.tsf.2009.10.054.
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Ma, T. P. "(Plenary) Beyond-Si CMOS Technologies Based on High-Mobility Channels." ECS Transactions 54, no. 1 (June 28, 2013): 15–24. http://dx.doi.org/10.1149/05401.0015ecst.
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Chen, An, Supriyo Datta, X. Sharon Hu, Michael T. Niemier, Tajana Simunic Rosing, and J. Joshua Yang. "A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies." IEEE Design & Test 36, no. 3 (June 2019): 46–68. http://dx.doi.org/10.1109/mdat.2019.2902359.
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Bourianoff, George, and Dmitri Nikonov. "(Keynote) Progress, Opportunities and Challenges for Beyond CMOS Information Processing Technologies." ECS Transactions 35, no. 2 (December 16, 2019): 43–53. http://dx.doi.org/10.1149/1.3568847.
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LI, QILIANG. "HYBRID SILICON-MOLECULAR ELECTRONICS." Modern Physics Letters B 22, no. 12 (May 20, 2008): 1183–202. http://dx.doi.org/10.1142/s0217984908016054.
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As CMOS technology extends beyond the current technology node, many challenges to conventional MOSFET were raised. Non-classical CMOS to extend and fundamentally new technologies to replace current CMOS technology are under intensive investigation to meet these challenges. The approach of hybrid silicon/molecular electronics is to provide a smooth transition technology by integrating molecular intrinsic scalability and diverse properties with the vast infrastructure of traditional MOS technology. Here we discuss: (1) the integration of redox-active molecules into Si -based structures, (2) characterization and modeling of the properties of these Si /molecular systems, (3) single and multiple states of Si /molecular memory, and (4) applications based on hybrid Si /molecular electronic system.
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De Gendt, Stefan. "(Dielectric Science & Technology Thomas Callinan Award) Materials and Processes As Enablers for Moore Moore and Beyond Moore Technologies." ECS Meeting Abstracts MA2022-01, no. 18 (July 7, 2022): 1036. http://dx.doi.org/10.1149/ma2022-01181036mtgabs.
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In this presentation, an overview will be presented of historic and recent developments achieved w.r.t. materials and processes that enabled continued performance scaling of CMOS and beyond CMOS applications. Starting from early high-k work. For decades, thermal oxidation of crystalline Silicon into SiO2 has been the gate oxide material in CMOS technology. Miniaturization for performance improvement, required the gate dielectric to decrease in thickness to support the required increase in capacitance (per unit area) and drive current (per device width). Early 2000, the thickness scaled below 1.5 nm, causing drastically increased leakage currents, high power consumption and reduced device reliability. Replacing the SiO2 gate dielectric with a high-κ (dielectric constant) material allows increased gate capacitance without the associated leakage effects. Activities involved the unit process step development of dielectric and metal deposition processes, advanced interface preparation, electrical and physical characterization and wet and dry etch process development. In a second section, emphasis will be on emerging nanomaterials. Nanotechnology is defined as the manipulation of matter with at least one dimension sized from below 100nm, thus all CMOS activities are functional nanotechnology. The latter concentrated initially on Graphene, but extended further towards Transition Metal Dicalchogenide Materials. Emphasis of the work will be on growth, functionalization, dielectric passivation and doping of these materials. Lastly, expanding on the nanomaterial know-how also progress with regard to low-k dielectrics, area selective deposition processes (for bottom-up lithography) and application of nanochemistry research for photoresist material screening, where chemical interactions at the nanoscale, related to the EUV lithography (radiation chemistry) are hampering the pattern scaling. Throughout the presentation, recognition will be given to people (PhD students) that contributed to this work and the presentation is also in honor of Prof Dolf Landheer and Professor Samares Kar with whom I organized my first ECS symposium.
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Pan, Chenyun, Qiuwen Lou, Michael Niemier, Sharon Hu, and Azad Naeemi. "Energy-Efficient Convolutional Neural Network Based on Cellular Neural Network Using Beyond-CMOS Technologies." IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5, no. 2 (December 2019): 85–93. http://dx.doi.org/10.1109/jxcdc.2019.2960307.
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Li, Cheng, Zijin Pan, Xunyu Li, Weiquan Hao, Runyu Miao, and Albert Wang. "Selective Overview of 3D Heterogeneity in CMOS." Nanomaterials 12, no. 14 (July 8, 2022): 2340. http://dx.doi.org/10.3390/nano12142340.
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As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human–world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.
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Grella, K., S. Dreiner, H. Vogt, and U. Paschen. "Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology." Journal of Microelectronics and Electronic Packaging 10, no. 4 (October 1, 2013): 150–54. http://dx.doi.org/10.4071/imaps.391.
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It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.
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Grella, K., S. Dreiner, H. Vogt, and U. Paschen. "High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000116–21. http://dx.doi.org/10.4071/hiten-ta13.
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Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.
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Shaheen, Saleh, Gady Golan, Moshe Azoulay, and Joseph Bernstein. "A comparative study of reliability for finfet." Facta universitatis - series: Electronics and Energetics 31, no. 3 (2018): 343–66. http://dx.doi.org/10.2298/fuee1803343s.
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The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integrated Circuit (IC) density and performance. The emergence of FinFET technology has brought with it the same reliability issues as standard CMOS with the addition of a new prominent degradation mechanism. The same mechanisms still exist as for previous CMOS devices, including Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Electro-migration (EM), and Body Effects. A new and equally important reliability issue for FinFET is the Self -heating, which is a crucial complication since thermal time-constant is generally much longer than the transistor switching times. FinFET technology is the newest technological paradigm that has emerged in the past decade, as downscaling reached beyond 20 nm, which happens also to be the estimated mean free path of electrons at room temperature in silicon. As such, the reliability physics of FinFET was modified in order to fit the newly developed transistor technology. This paper highlights the roles and impacts of these various effects and aging mechanisms on FinFET transistors compared to planar transistors on the basic approach of the physics of failure mechanisms to fit to a comprehensive aging model.
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Fiorelli, Rafaella, Eduardo Peralías, Roberto Méndez-Romero, Mona Rajabali, Akash Kumar, Mohammad Zahedinejad, Johan Åkerman, Farshad Moradi, Teresa Serrano-Gotarredona, and Bernabé Linares-Barranco. "CMOS Front End for Interfacing Spin-Hall Nano-Oscillators for Neuromorphic Computing in the GHz Range." Electronics 12, no. 1 (January 3, 2023): 230. http://dx.doi.org/10.3390/electronics12010230.
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Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 µV even for an impedance as large as 300 Ω and a noise figure of 5.3 dB300 Ω. A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.
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Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (June 22, 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.
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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.
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Chen, An. "(Invited, Digital Presentation) Emerging Materials and Devices for Energy-Efficient Computing." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1073. http://dx.doi.org/10.1149/ma2022-01191073mtgabs.
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As the CMOS scaling driven by the Moore’s Law approaching the fundamental limits, high energy consumption and heat dissipation have been recognized as the most critical device challenges. Novel switching devices with significantly lower power based on unconventional mechanisms have been explored to replace CMOS in various research programs, e.g., Nanoelectronics Research Initiative (NRI). The major categories of these devices include steep-slope transistors, spintronic devices, ferroelectric devices, and van der Waals devices [1]. These devices are often implemented on emerging materials with unique properties. As the foundation of nanoelectronic devices and systems, novel materials (including dielectrics) present both great challenges and promising opportunities. For example, dielectric layers for gating and electrical insulation are critical for low-dimension devices; magnetic insulators are promising for low-power high-efficiency spintronic devices; ferroelectric materials have been utilized to realize “negative-capacitance” transistors with steep subthreshold slope. Despite abundant scientific breakthroughs achieved on these emerging devices, comprehensive benchmarking has revealed that most of them do not outperform CMOS for Boolean logic and von Neumann architectures [2]. Therefore, the focus of emerging materials and devices has increasingly shifted toward novel computing paradigms. Novel computing paradigms beyond Boolean logic and von Neumann architectures may provide solutions for energy-efficient computing. For example, in-memory computing reduces data movement between computing and memory units, and exploits the intrinsic parallelism in memory arrays. Neural-inspired computing implements cognitive and intelligent functions through a wide range of approaches, e.g., deep neural network, spiking neural network, hyperdimensional computing, probabilistic network, dynamic systems, etc. Although many of these approaches can be implemented in CMOS technologies, more efficient solutions may originate from the engineering and optimization of materials and devices that could enable native implementations of novel computing paradigms. For example, ferroelectric materials, binary and complex oxides, and chalcogenides have been utilized in a wide range of nonvolatile memories and analog devices, which may enable highly efficient in-memory computing and analog computing solutions. At the same time, stringent requirements exist for emerging devices to significantly outperform CMOS in novel computing paradigms, e.g., high density, fast speed, low power, high endurance, long retention, wide analog tunability, asymmetry, etc. [3] Specific requirements vary from application to application. Therefore, device-architecture co-design and co-optimization are important to address these requirements. A holistic approach from basic material exploration to device engineering and further up to architecture co-design has been adopted in more recent research programs, e.g., Energy-Efficient Computing from Devices to Architectures (E2CDA) [4]. This presentation will review the opportunities and challenges of emerging materials and devices for energy-efficient nanoelectronics, and highlight the approaches and perspectives of the E2CDA program. References: K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” IEEE Proc. 98(12), 2169-2184 (2010). C. Pan and A. Naeemi, “Non-Boolean computing benchmarking for beyond-CMOS devices based on cellular neural network,” IEEE J. Explor. Solid-State Comp. Dev. & Circ 2, 36-43 (2016). G.W. Burr, et al, “Neuromorphic computing using non-volatile memory,” Advances in Physics: X, 2(1), 89-124 (2017). A. Chen, “New directions of nanoelectronics research for computing,” 14th IEEE ICSICT (2018).
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Kerber, Andreas. "Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling." MRS Advances 2, no. 52 (2017): 2973–82. http://dx.doi.org/10.1557/adv.2017.504.
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ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.
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Lallas, Efthymios. "Key Roles of Plasmonics in Wireless THz Nanocommunications—A Survey." Applied Sciences 9, no. 24 (December 13, 2019): 5488. http://dx.doi.org/10.3390/app9245488.
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Wireless data traffic has experienced an unprecedented boost in past years, and according to data traffic forecasts, within a decade, it is expected to compete sufficiently with wired broadband infrastructure. Therefore, the use of even higher carrier frequency bands in the THz range, via adoption of new technologies to equip future THz band wireless communication systems at the nanoscale is required, in order to accommodate a variety of applications, that would satisfy the ever increasing user demands of higher data rates. Certain wireless applications such as 5G and beyond communications, network on chip system architectures, and nanosensor networks, will no longer satisfy speed and latency demands with existing technologies and system architectures. Apart from conventional CMOS technology, and the already tested, still promising though, photonic technology, other technologies and materials such as plasmonics with graphene respectively, may offer a viable infrastructure solution on existing THz technology challenges. This survey paper is a thorough investigation on the current and beyond state of the art plasmonic system implementation for THz communications, by providing in-depth reference material, highlighting the fundamental aspects of plasmonic technology roles in future THz band wireless communication and THz wireless applications, that will define future demands coping with users’ needs.
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Wiehe, Moritz. "Silicon Detectors for the LHC Phase-II Upgrade and Beyond – RD50 Status Report." Journal of Physics: Conference Series 2374, no. 1 (November 1, 2022): 012167. http://dx.doi.org/10.1088/1742-6596/2374/1/012167.
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A large R&D program has been underway to develop silicon sensors with sufficient radiation tolerance for LHC-Phase-II trackers and the next generation of collision experiments. Key areas of recent RD50 research include new technologies such as CMOS and Low Gain Avalanche Detectors (LGADs), where a dedicated multiplication layer to create a high field region is built into the sensor. We also seek for a deeper understanding of the connection between macroscopic sensor properties such as radiation-induced increase of leakage current, effective doping concentration and trapping, and the microscopic properties at the defect level. Another strong activity is the development of advanced sensor types, like 3D silicon detectors. We will present the state of the art in silicon detectors at radiation levels corresponding to LHC-Phase-II fluences and beyond. Based on our results, we will give an outlook towards the silicon detectors to be used for particle detectors at future colliders like the FCC.
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Singh, Inderjit, Balwinder Raj, Mamta Khosla, and Brajesh Kumar Kaushik. "Comparative Analysis of Spintronic Memories for Low Power on-chip Caches." SPIN 10, no. 04 (November 16, 2020): 2050027. http://dx.doi.org/10.1142/s2010324720500277.
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The continuous downscaling in CMOS devices has increased leakage power and limited the performance to a few GHz. The research goal has diverted from operating at high frequencies to deliver higher performance in essence with lower power. CMOS based on-chip memories consumes significant fraction of power in modern processors. This paper aims to explore the suitability of beyond CMOS, emerging magnetic memories for the use in memory hierarchy, attributing to their remarkable features like nonvolatility, high-density, ultra-low leakage and scalability. NVSim, a circuit-level tool, is used to explore different design layouts and memory organizations and then estimate the energy, area and latency performance numbers. A detailed system-level performance analysis of STT-MRAM and SOT-MRAM technologies and comparison with 22[Formula: see text]nm SRAM technology are presented. Analysis infers that in comparison to the existing 22[Formula: see text]nm SRAM technology, SOT-MRAM is more efficient in area for memory size [Formula: see text][Formula: see text]KB, speed and energy consumption for cache size [Formula: see text][Formula: see text]KB. A typical 256[Formula: see text]KB SOT-MRAM cache design is 27.74% area efficient, 2.97 times faster and consumes 76.05% lesser leakage than SRAM counterpart and these numbers improve for larger cache sizes. The article deduces that SOT-MRAM technology has a promising potential to replace SRAM in lower levels of computer memory hierarchy.
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Kumaresan, Raja Sekar, Marshal Raj, and Lakshminarayanan Gopalakrishnan. "Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology." Journal of Electrical Engineering 73, no. 1 (February 1, 2022): 1–10. http://dx.doi.org/10.2478/jee-2022-0001.
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Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.
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Wong, H. S. Philip. "(Digital Presentation) Low Dimensional Channel Materials for Logic Transistors." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1182. http://dx.doi.org/10.1149/ma2022-02321182mtgabs.
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A key technology future direction is CMOS + X, where X can be memory, photonics, spintronics, power electronics, nanomechanics, sensors and actuators, RF/mm-wave, and even quantum computing. Nanosystems of 3D integrated “X” technology (N3XT) is a key concept at the chip level. We must also go beyond a single chip from a wafer and focus on integrating chips into systems using MOSAIC (MOnolithic Stacked Assembled IC). I will give an overview of the new materials and device technologies that may need to be developed to realize this vision. In particular, low-dimensional materials are suitable for logic transistors in this 3D MOSAIC of N3XT chips vision because of the low temperature for device fabrication as well as the thin device layers.
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Guendouz, Djeber, Chhandak Mukherjee, Marina Deng, Magali De Matos, Christophe Caillaud, Hervé Bertin, Antoine Bobin, et al. "Multiscale Compact Modelling of UTC-Photodiodes Enabling Monolithic Terahertz Communication Systems Design." Applied Sciences 11, no. 23 (November 23, 2021): 11088. http://dx.doi.org/10.3390/app112311088.
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Due to the continuous increase in data traffic, it is becoming imperative to develop communication systems capable of meeting the throughput requirements. Monolithic Opto-Electronic Integrated Circuits (OEICs) are ideal candidates to meet these demands. With that in mind, we propose a compact and computationally efficient model for Uni-Traveling Carrier Photodiodes (UTC-PDs) which are a key component of OEICs because of their high bandwidth and RF output power. The developed compact model is compatible with existing SPICE design software, enabling the design of beyond 5G and terahertz (THz) communication circuits and systems. By introducing detailed physical equations describing, in particular, the dark current, the intrinsic series resistance, and the junction capacitance, the model accurately captures the physical characteristics of the UTC-PD. The model parameter extraction follows a scalable extraction methodology derived from that of the bipolar and CMOS technologies. A detailed description of the de-embedding process is presented. Excellent agreement between the compact model and measurements has been achieved, showing model versatility across various technologies and scalability over several geometries.
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Kim, Heewoo, Aporva Amarnath, Javad Bagherzadeh, Nishil Talati, and Ronald G. Dreslinski. "A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (June 25, 2021): 1–44. http://dx.doi.org/10.1145/3453143.
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The advancement of Silicon CMOS technology has led information technology innovation for decades. However, scaling transistors down according to Moore’s law is almost reaching its limitations. To improve system performance, cost, and energy efficiency, vertical-optimization in multiple layers of the computing stack is required. Technological awareness in terms of devices and circuits could enable informed system-level decisions. For example, graphene is a promising material for extremely scaled high-speed transistors because of its remarkably high mobility, but it can not be used in integrated circuits as a result of the high leakage current from its zero bandgap. In this article, we discuss the fundamental physics of transistors and their ramifications on system design to assist device-level technology consideration during system design. Additionally, various emerging devices and their utilization on a vertically-optimized computing stack are introduced. This article serves as a survey of emerging device technologies that may be relevant in these areas, with an emphasis on making the descriptions approachable by system and software designers to understand the potential solutions. A basic vocabulary will be built to understand how to digest technical content, followed by a survey of devices, and finally a discussion of the implications for future processing systems.
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Takenaka, Mitsuru, and Shinichi Takagi. "III-V/Ge Device Engineering for CMOS Photonics." Materials Science Forum 783-786 (May 2014): 2028–33. http://dx.doi.org/10.4028/www.scientific.net/msf.783-786.2028.
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Heterogeneous integration of III-V compound semiconductors and Ge on the Si platform is one of the promising technologies for enhancing the performance of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 10-nm technology node because of their high carrier mobilities. In addition, the III-Vs and Ge are also promising materials for photonic devices. Thus, we have investigated III-V/Ge device engineering for CMOS photonics, enabling monolithic integration of high-performance III-V/Ge CMOS transistors and III-V/Ge photonics on Si. The direct wafer bonding of III-V on Si has been investigated to form III-V on Insulator for III-V CMOS photonics. Extremely-thin-body InGaAs MOSFETs with the gate length of approximately 55 nm have successfully been demonstrated by using the wafer bonding. InP-based photonic-wire waveguide devices including micro bends, arrayed waveguide gratings, grating couplers, optical switches, and InGaAs photodetectors have also been demonstrated on the III-V-OI wafer. The gate stack formation on Ge is one of the critical issues for Ge MOSFETs. Recently, we have successfully demonstrated high-quality GeOx/Ge MOS interfaces formed by thermal oxidation and plasma oxidation. High-performance Ge pMOSFET and nMOSFET with thin EOT have been obtained using the GeOx/Ge MOS interfaces. We have also demonstrated that GeOx surface passivation is effective to reduce the dark current of Ge photodetectors in conjunction with gas-phase doped junction. We have also investigated strained SiGe optical modulators. We expect that compressive strain in SiGe enhances modulation efficiency, and an extremely small VπL of 0.033 V-cm is predicted. III-V/Ge heterogeneous integration is one of the promising ways for achieving ultrahigh performance electronic-photonic integrated circuits.
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Zhou, Chongwu. "(Invited) Nanoelectronics Based on Assembled High-Density and High-Semiconducting-Purity Carbon Nanotube Films." ECS Meeting Abstracts MA2022-01, no. 9 (July 7, 2022): 751. http://dx.doi.org/10.1149/ma2022-019751mtgabs.
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Carbon nanotubes hold great promise for high-performance electronics but also face significant challenges in terms of assembly and integration. On one hand, aligned carbon nanotubes are proposed as an alternative to III-V semiconductor technologies in radio frequency (RF) applications because of their high linearity as amplifiers and compatibility with CMOS electronics. We will first report high-performance RF transistors with operation frequencies beyond 100 GHz. These devices are built upon high-density (~50 nanotubes / micron) and high semiconducting purity (> 99.99%) aligned single-wall carbon nanotube films assembled at wafer scale. With gate length ~110 nm and T-shaped gate to reduce the gate charging resistance, the devices showed an extrinsic cutoff frequency and maximum oscillation frequency of over 100 GHz. The performance surpasses the 90 GHz cutoff frequency of radio-frequency CMOS transistors with gate length of 100 nm and is close to the performance of GaAs technology. [1] On the other hand, Carbon nanotubes are ideal candidates for beyond-silicon nanoelectronics because of their high mobility and low-cost processing; however, n-type transistors based on assembled aligned nanotubes has not been reported yet. Fabrication of n-type behavior field effect transistors (FETs) based on assembled aligned CNT arrays is needed for advanced CNT electronics. We will report a scalable process to make n-type transistors based on assembled aligned CNT arrays. Air-stable and high-performance n-type CNT FETs are achieved with high yield by combining atomic layer deposition dielectric and Ti contacts with gold overcoating, which are stable in air and widely used for III-V semiconductors. We also systematically studied the contribution of metal contacts and atomic layer deposition passivation in determining the transistor polarity. [2] Based on these experimental results, we report the successful demonstration of complementary metal-oxide-semiconductor inverters with good performance, which paves the way to realizing the promising future of carbon nanotube nanoelectronics. [1] “Wafer-scalable, aligned carbon nanotube transistors operating at frequencies of over 100 GHz”, C. Rutherglen, A. A. Kane, P. F. Marsh, T. A. Cain, B. I. Hassan, M. R. AlShareef, C. Zhou and K. Galatsis, Nature Electronics, volume 2, pages 530–539, 2019. [2] “Air-Stable n-Type Transistors based on Assembled Aligned Carbon Nanotube Arrays and Their Application in CMOS Electronics”, Z. Li, K. R. Jinkins, D. Cui, M. Chen, Z. Zhao, M. S. Arnold and C. Zhou, Nano Res. (2021). https://doi.org/10.1007/s12274-021-3567-9.
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Fuhrer, Michael S., Chun Ning Lau, and Allan H. MacDonald. "Graphene: Materially Better Carbon." MRS Bulletin 35, no. 4 (April 2010): 289–95. http://dx.doi.org/10.1557/mrs2010.551.
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AbstractGraphene, a single atom–thick plane of carbon atoms arranged in a honeycomb lattice, has captivated the attention of physicists, materials scientists, and engineers alike over the five years following its experimental isolation. Graphene is a fundamentally new type of electronic material whose electrons are strictly confined to a two-dimensional plane and exhibit properties akin to those of ultrarelativistic particles. Graphene's two-dimensional form suggests compatibility with conventional wafer processing technology. Extraordinary physical properties, including exceedingly high charge carrier mobility, current-carrying capacity, mechanical strength, and thermal conductivity, make it an enticing candidate for new electronic technologies both within and beyond complementary metal oxide semiconductors (CMOS). Immediate graphene applications include high-speed analog electronics and highly conductive, flexible, transparent thin films for displays and optoelectronics. Currently, much graphene research is focused on generating and tuning a bandgap and on novel device structures that exploit graphene's extraordinary electrical, optical, and mechanical properties.
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Manipatruni, Sasikanth, Dmitri E. Nikonov, Chia-Ching Lin, Bhagwati Prasad, Yen-Lin Huang, Anoop R. Damodaran, Zuhuang Chen, Ramamoorthy Ramesh, and Ian A. Young. "Voltage control of unidirectional anisotropy in ferromagnet-multiferroic system." Science Advances 4, no. 11 (November 2018): eaat4229. http://dx.doi.org/10.1126/sciadv.aat4229.
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Demonstration of ultralow energy switching mechanisms is imperative for continued improvements in computing devices. Ferroelectric (FE) and multiferroic (MF) order and their manipulation promise an ideal combination of state variables to reach attojoule range for logic and memory (i.e., ~30× lower switching energy than nanoelectronics). In BiFeO3(BFO), the coupling between the antiferromagnetic (AFM) and FE order is robust at room temperature, scalable in voltage, stabilized by the FE order, and can be integrated into a fabrication process for a beyond-CMOS (complementary metal-oxide semiconductor) era. The presence of the AFM order and a canted magnetic moment in this system causes exchange interaction with a ferromagnet such as Co0.9Fe0.1or La0.7Sr0.3MnO3. Previous research has shown that exchange coupling (uniaxial anisotropy) can be controlled with an electric field. However, voltage modulation of unidirectional anisotropy, which is preferred for logic and memory technologies, has not yet been demonstrated. Here, we present evidence for electric field control of exchange bias of laterally scaled spin valves that is exchange coupled to BFO at room temperature. We show that the exchange bias in this bilayer is robust, electrically controlled, and reversible. We anticipate that magnetoelectricity at these scaled dimensions provides a powerful pathway for computing beyond modern nanoelectronics by enabling a new class of nonvolatile, ultralow energy computing elements.
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Kotus, Katarzyna A., Mathieu Moalic, Matusz Zelent, Maciej Krawczyk, and Pawel Gruszecki. "Scattering of spin waves in a multimode waveguide under the influence of confined magnetic skyrmion." APL Materials 10, no. 9 (September 1, 2022): 091101. http://dx.doi.org/10.1063/5.0100594.
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Nontrivial magnetization textures, such as skyrmions, have become a driving force in the physics of magnetism. Furthermore, the utilization of magnetization textures is fueling the development of magnon-based technologies that could provide beyond-CMOS solutions. Here, using a self-developed spin wave (SW) excitation scheme, we selectively excite specific modes and investigate the scattering of SWs on nanodot hosting a Néel-type skyrmion and placed above a multimode waveguide. In particular, at low frequencies, we observe significant reflections from the imprint induced by the skyrmion upon the waveguide. As the frequency increases, the transmission increases as well; however, it is accompanied by scattering to other types of modes. Here, we observe a direct contribution of the skyrmion to the scattering process and various types of conversions of the incident SW modes into other modes quantized by width for both reflected and transmitted SWs. The utilization of imprinted magnetization textures in nonplanar systems to control SW flow can open new possibilities for developing SW-based circuits for ultralow-power signal processing.
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Yadav, Sachin, Pieter Cardinael, Ming Zhao, Komal Vondkar, Uthayasankaran Peralagu, Alireza Alian, Raul Rodriguez, et al. "(Digital Presentation) Substrate Effects in GaN-on-Si Hemt Technology for RF FEM Applications." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1208. http://dx.doi.org/10.1149/ma2022-02321208mtgabs.
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Abstract : GaN-on-Si HEMTs are emerging as a viable candidate for front-end-of-module (FEM) implementation in 5G and beyond user equipment and small-cell applications [1][2]. This is because GaN HEMTs based power amplifiers and switches have high power handling capability as well as excellent switch figure-of-merit (Ron × Coff). The cost-effective integration of GaN HEMTs on silicon substrates not only benefit from standard CMOS back-end-of-the-line processing but also wafer-level integration with Si-CMOS [1][3], enabling complex functionality and better performance than the standalone counterparts. An example can be a hybrid beamformer where GaN HEMTs can enable much smaller antenna array and therefore a smaller system form factor. For 5G wireless applications, standalone or co-integrated GaN HEMT based FEMs can lead to a more energy efficient and compact system as compared to standalone Si-CMOS technologies. However, for both amplifiers and switches, GaN-on-Si HEMTs present thermal management and substrate loss related issues. In this work, we study and model the impact of GaN HEMT integration on Si substrate on RF substrate losses and non-linearities. The growth of III-N buffer is the most significant factor in determining RF losses and harmonic distortion contribution from the substrate. High temperature annealing and ion implantation steps encountered during HEMT processing can also degrade the substrate performance. In addition, we demonstrate a direct co-relation between substrate losses and harmonic distortion analogous to silicon-on-insulator technologies (Figure 1). However, the bias dependence of RF losses and harmonics show a strong time dependence (memory effects) which is more complex to model [11]. We discuss the approaches to understand and model these effects. References: [1] H. W. Then et al, IEEE IEDM Tech. Dig., 2021, pp. 230-234. [2] B. Parvais et al, IEEE IEDM Tech. Dig., 2020, pp. 155-158. [3] W. E. Hoke et al, J. Vac. Sci. Technol. B 30, 02B101 (2012). [4] Drillet F et al, IJMWT 13, 517–522, 2021. [5] L. Cao et al, CSMANTECH conference Tech. Dig., 2020. [6] Roda Neve et al, IEEE TED, Vol. 59, NO. 4, pp. 924-932, 2012. [7] S. Yadav et al., in IEEE IEDM Tech. Dig., 2020, pp. 159-162. [8] Rack et al, ECS Trans., 92 (4), pp. 79-94, 2019. [9] Zhu et al, IEEE Microw. Wireless Compon. Lett., vol. 28, no. 8, pp. 377–379, 2018. [10] Raskin et al, IEEE SiRFIC, 2015. [11] P. Cardinael et al, IEEE ESSDERC 2021, pp. 303-306. Figure 1
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Gupta, Prateek, Dr Avnish Kumar Upadhyay, Dr Chandan Kumar Jha, Anuj Gupta, and Lakshay Gupta. "Performance Analysis and Comparison of Different High-K Materials Used as Gate Dielectrics in DH-TMSG MOSFET." International Journal for Research in Applied Science and Engineering Technology 10, no. 12 (December 31, 2022): 1870–89. http://dx.doi.org/10.22214/ijraset.2022.48089.
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Abstract: To overcome SCEs and provide better packing density and performance a device called Double Halo Triple Material Surround Gate MOSFET is introduced. The device is designed by the combination of gate engineering and channel engineering. The device uses a surround gate MOSFET with triple material gate employing gate material engineering which improves the gate transport efficiency by modifying electric field pattern and surface potential along channel, resulting in higher carrier transport efficiency and SCEs. To extend the use of CMOS technology beyond 14 nm node technology, new device materials are required that can enhance the performance of MOSFETs. The use of high-k materials in double gate (DG) MOSFET can triumph over the problem of power dissipation and leakage current. The further mitigation in device dimension becomes a challenging task due to the existence of unavoidable short channel effects. The introduction of gate stack and channel engineering in MOSFET devices open a new window for future generation devices. The gate dielectric materials have played a significant role in the design of novel and high performances at nanoscale of electrical devices. It can be observed that when approaching a higher value of dielectric constant, the on current increases while the subthreshold slope (SS) threshold voltage (Vth) and leakaga current reduced. The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large.
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Bez, Roberto, Emilio Camerlenghi, and Agostino Pirovano. "Materials and Processes for Non-Volatile Memories." Materials Science Forum 608 (December 2008): 111–32. http://dx.doi.org/10.4028/www.scientific.net/msf.608.111.
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The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials. NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect, thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um2 at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate. In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.
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Gnoli, Luca, and Fabrizio Riente. "A skyrmion content-addressable cell for skyrmion magnetic memories." Nanotechnology 33, no. 20 (February 21, 2022): 205203. http://dx.doi.org/10.1088/1361-6528/ac4dc2.
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Abstract Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 μm2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations.
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Linder, Barry, Vamsi Paruchuri, Vijay Narayanan, Eduard Cartier, Nestor Bojarczuk, Supratik Guha, Stephen Brown, and Y. Wang. "Recent Advances in Search for Suitable High-k/Metal Gate Solutions to Replace SiON/Poly-Silicon Gate Stacks in CMOS Devices for 45nm and Beyond Technologies." ECS Transactions 6, no. 1 (December 19, 2019): 287–94. http://dx.doi.org/10.1149/1.2727412.
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Satyanarayana, B. V. V., and M. Durga Prakash. "Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell." International Journal of Engineering & Technology 7, no. 3.29 (August 24, 2018): 8. http://dx.doi.org/10.14419/ijet.v7i3.29.18450.
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Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.
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Weikle, Robert M., N. Scott Barker, Arthur W. Lichtenberger, Matthew F. Bauwens, and Naser Alijabbari. "Heterogeneous Integration and Micromachining Technologies for Terahertz Devices and Components." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 002041–81. http://dx.doi.org/10.4071/2015dpc-tha31.
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Terahertz electronics has been a topic of research and development for many years, motivated largely by the technological needs of the radio astronomy and remote sensing scientific communities. Over the past decade, however, this field has experienced dramatic growth and intense, renewed interest from academic researchers and federal agencies, as well as from industry. This interest has arisen, in part, from recent funding initiatives from the federal government (such as DARPA's Terahertz Electronics Program), but is also largely due to the establishment of a commercial infrastructure that has made test and measurement instrumentation available to the engineers and scientists working at these frequencies. Moreover, the emergence of CMOS as a potential submillimeter-wave device technology has greatly expanded access to this spectral region by providing circuit designers with a platform for realizing terahertz circuits without need for specialized fabrication facilities or processes. The recent and rapid progress in terahertz electronics has created a demand for improved approaches to packaging and integration, as well as a need for new measurement instrumentation for characterizing emerging terahertz devices. This paper focuses on two recent research developments aimed at addressing these needs and broadening the technology base for both terahertz system implementation and terahertz metrology. These developments include (1) the development of a direct-contact probe technology that permits on-wafer scattering-parameter characterization and measurement of planar integrated devices at frequencies to 1 THz and beyond, and (2) the establishment of processing technologies that permit fabrication of highly-integrated submillimeter-wave diode-based circuits, such as heterodyne receivers and frequency multipliers, that are based on heterogeneous integration of III-V semiconductor devices with thin silicon membranes as a support and integration substrate. The technical foundation for each of these efforts is micromachining of silicon that allow the formation of mechanically-robust and low-loss membrane carriers to support terahertz devices and circuitry. Two examples of heterogeneous integration with silicon as an approach to packaging terahertz components are detailed in this paper. These include development of micromachined probes for on-wafer measurements of devices and circuits in the WR-1.0 waveguide band (0.75 – 1.1 THz). The probe design concept will be presented and methods for characterizing the probe described. Measurements demonstrate that the probes exhibit an insertion loss of less than 7 dB and return loss of greater than 15 dB over 750—1100 GHz band, yielding the first demonstration of on-wafer probe operating above 1 THz. In addition, an example of heterogeneous integration/packaging of a submillimeter-wave frequency quadrupler operating at 160 GHz with efficiency of 30% and corresponding output power of 70 mW will be discussed. The quadrupler design includes two frequency doubler stages in cascade and is based on a balanced circuit architecture that addresses degradation issues often arising from impedance mismatches between multiplier stages. A unique quasi-vertical diode fabrication process consisting of transfer of GaAs epitaxy to the thin silicon support substrate is used to implement the quadrupler, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting.
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Prewett, Philip D., Cornelis W. Hagen, Claudia Lenk, Steve Lenk, Marcus Kaestner, Tzvetan Ivanov, Ahmad Ahmad, et al. "Charged particle single nanometre manufacturing." Beilstein Journal of Nanotechnology 9 (November 14, 2018): 2855–82. http://dx.doi.org/10.3762/bjnano.9.266.
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Following a brief historical summary of the way in which electron beam lithography developed out of the scanning electron microscope, three state-of-the-art charged-particle beam nanopatterning technologies are considered. All three have been the subject of a recently completed European Union Project entitled “Single Nanometre Manufacturing: Beyond CMOS”. Scanning helium ion beam lithography has the advantages of virtually zero proximity effect, nanoscale patterning capability and high sensitivity in combination with a novel fullerene resist based on the sub-nanometre C60 molecule. The shot noise-limited minimum linewidth achieved to date is 6 nm. The second technology, focused electron induced processing (FEBIP), uses a nozzle-dispensed precursor gas either to etch or to deposit patterns on the nanometre scale without the need for resist. The process has potential for high throughput enhancement using multiple electron beams and a system employing up to 196 beams is under development based on a commercial SEM platform. Among its potential applications is the manufacture of templates for nanoimprint lithography, NIL. This is also a target application for the third and final charged particle technology, viz. field emission electron scanning probe lithography, FE-eSPL. This has been developed out of scanning tunneling microscopy using lower-energy electrons (tens of electronvolts rather than the tens of kiloelectronvolts of the other techniques). It has the considerable advantage of being employed without the need for a vacuum system, in ambient air and is capable of sub-10 nm patterning using either developable resists or a self-developing mode applicable for many polymeric resists, which is preferred. Like FEBIP it is potentially capable of massive parallelization for applications requiring high throughput.
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Mochizuki, Shogo, Juntao Li, Erin Stuckert, Huimei Zhou, and Nicolas Loubet. "Compressive Strained Si1-XGex Channel for High Performance Gate-All-Around Nanosheet Transistors." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1192. http://dx.doi.org/10.1149/ma2022-02321192mtgabs.
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As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing. To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa. Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel. The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1
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Gilewski, Marian. "The ripple-curry amplifier in photonic applications." Photonics Letters of Poland 14, no. 4 (December 31, 2022): 86–88. http://dx.doi.org/10.4302/plp.v14i4.1187.
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This paper discusses the new design of a amplifier for the miniature MEMS-type spectrometer. The application problem of the new amplifier was the correct conditioning of the sensor's photoelectric pulses. The processed signal was a sequence of pulses that had variable both frequency and amplitude value. Thus, such a broadband amplifier should have the functionality of automatic gain control. This paper describes the concept of the new circuit, develops its detailed application, and then performs validation tests. Measurement results of the new circuit are discussed in the final section of the paper. Full Text: PDF ReferencesC. Ortolani, Flow Cytometry Today. Detectors and Electronics, (Springer 2022). pp. 97-119, CrossRef D. Maes, L. Reis, S. Poelman, E. Vissers, V. Avramovic, M. Zaknoune, G. Roelkens, S. Lemey, E. Peytavit, B. Kuyken, "High-Speed Photodiodes on Silicon Nitride with a Bandwidth beyond 100 GHz", Conference on Lasers and Electro-Optics, Optica Publishing Group, (2022). CrossRef R. Das, Y. Xie, A.P. Knights, "All-Silicon Low Noise Photonic Frontend For LIDAR Applications", 2022 IEEE Photonics Conference (IPC), IEEE Xplore (2022). CrossRef FEMTO Messtechnik GmbH, Variable Gain Photoreceiver - Fast Optical Power Meter Series OE-200, DirectLink M. Nehir, C. Frank, S. Aßmann, E.P. Achterberg, "Improving Optical Measurements: Non-Linearity Compensation of Compact Charge-Coupled Device (CCD) Spectrometers", Sensors 19(12), 2833 (2019). CrossRef F. Thomas,; R. Petzold, C. Becker, U. Werban, "Application of Low-Cost MEMS Spectrometers for Forest Topsoil Properties Prediction", Sensors 21(11), 3927 (2021). CrossRef M. Muhiyudin, D. Hutson, D. Gibson, E. Waddell, S. Song, S. Ahmadzadeh, "Miniaturised Infrared Spectrophotometer for Low Power Consumption Multi-Gas Sensing", Sensors 20(14), 3843 (2020). CrossRef S. Maruyama, T Hizawa, K. Takahashi, K. Sawada, "Optical-Interferometry-Based CMOS-MEMS Sensor Transduced by Stress-Induced Nanomechanical Deflection", Sensors 18(1), 138 (2018). CrossRef S. Merlo, P. Poma, E. Crisà, D. Faralli, M. Soldo, "Testing of Piezo-Actuated Glass Micro-Membranes by Optical Low-Coherence Reflectometry", Sensors 17(3), 8 (2017). CrossRef M.S. Wei, F. Xing, B. Li, Z. You, "Investigation of Digital Sun Sensor Technology with an N-Shaped Slit Mask", Sensors 11(10), 9764 (2011). CrossRef Z. Yang, T. Albrow-Owen, W. Cai, T. Hasan, "Miniaturization of optical spectrometers", Science 371, 6528 (2021). CrossRef Hamamatsu Photonics K.K. Fingertip size, ultra-compact spectrometer head integrating MEMS and image sensor technologies. DirectLink Microchip Technology Inc, MCP6291/1R/2/3/4/5 1.0 mA 10 MHz Rail-to-Rail Op Amp, CrossRef Microchip Technology Inc. MCP6021/1R/2/3/4 Rail-to-Rail Input/Output 10 MHz Op Amps, CrossRef
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Veloso, Anabela, Geert Eneman, Eddy Simoen, Bogdan Cretu, An De Keersgieter, Anne Jourdain, and Naoto Horiguchi. "(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1059. http://dx.doi.org/10.1149/ma2022-01191059mtgabs.
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CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option to replace finFETs. Reduced gate lengths should be feasible thanks to their improved electrostatics, thus allowing further scaling of the contacted-gate-pitch and of the cell height via a reduced number of metal tracks. Other key characteristics include high design flexibility, with various NS widths possible on a given wafer, and larger drivability per layout footprint by increasing the number of vertically stacked NS per device and/or using wider NS [1,2] (Fig.1). An extension of this technology could in principle be envisioned by strongly reducing the p-n separation in the so-called forksheet configuration [3]. Beyond that, the concept of stacking devices with different polarity on top of each other is also being looked at [4,5]. Other future technology candidates include FETs with vertical transport [6] and non-silicon channels [7]. Each new architecture will have its own specific challenges such as the internal routeability for stacked structures in functional logic blocks (e.g., standard cell or SRAM) but, in general, many elements can be shared by the various branches of the NS family of devices. Overall, a careful balance between drive strength and capacitance is required in NS FETs engineering. In particular, the presence of dielectric inner spacers in-between vertically stacked nanosheets is a critical element, also as it leads to a different growth regime for the source/drain (S/D) epi as compared to the situation in finFETs [8]. This is an important differentiator as channel strain induced by S/D has been traditionally used to boost device performance. The feasibility of continuing using process-induced stress techniques for mobility enhancement is in fact a key challenge for several new architectures, namely for the top device in stacked structures or when S/D are placed in different vertical levels. Moreover, faced with power scaling stagnation, cold computing is also becoming an attractive option to consider for enabling high performance boosting in an energy efficient way. Our results confirm improved DC properties for NS FETs (e.g., subthreshold swing (SS), mobility), with similar mechanisms responsible for their noise behavior at room and low temperatures (300K (RT), 78K) [9]. In addition to the need for the introduction of new transistor technologies, given the increased complexity and cost in back-end-of-line processing, it has also become ever more pressing to address both wiring and power delivery network (PDN) bottlenecks to take full advantage of the scaling performance benefits at transistor level. The concept of moving the PDN to the wafer’s backside (BS) such that it can alleviate routing congestion on its frontside (FS) has been recently gaining traction [10,11]. This is illustrated in Fig.2 wherein, by combining logic and 3D technologies, both wafer sides are used. In our work, after frontside processing, device and carrier wafers are bonded at RT, including a 523K post-bond anneal. Extreme wafer thinning is then implemented prior to nano-through-silicon-vias (n-TSV) definition (landing on the metal-1 level (M1) in the frontside) and backside metallization. Evaluating the impact on scaled transistors from BS processing, our results show similar p/n threshold voltages (VTs) can be obtained with an extra sinter at the end of fabrication. Inclusion of an additional high-pressure H2-anneal prior to the final sinter is also seen to help lower the SS values for pmos without significant IOFF effect. Reliability-wise, constant ramped voltage stress measurements also show no BTI degradation for p/nmos, with additional indication of potential benefits by the final anneal(s) treatment selection. These findings are further corroborated by LF-noise analysis. References [1] N. Loubet et al., VLSI Tech. Dig., 2017, p.230. [2] A. Veloso et al., SSDM Tech. Dig., 2019, p.559. [3] P. Weckx et al., IEDM Tech. Dig., 2019, p.871. [4] W. Rachmady et al., IEDM Tech. Dig., 2019, p.697. [5] C.-Y. Huang et al., IEDM Tech. Dig., 2020, p.425. [6] A. Veloso et al., IEDM Tech. Dig., 2019, p.230. [7] P.-C. Shen et al., Nature, 2021, Vol.593, p.211. [8] G. Eneman et al., ECS Trans., 2020, Vol.98(5), p.253. [9] B. Cretu et al., EuroSOI-ULIS Tech. Dig., 2021. [10] A. Veloso et al., VLSI Tech. Dig., 2021, TFS2-6. [11] https://www.intel.com/content/www/us/en/events/accelerated.html. Figure 1
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Kikkawa, Takamaro, and Isami Sakai. "0.35 μm Technologies in Japan." MRS Proceedings 402 (1995). http://dx.doi.org/10.1557/proc-402-199.
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AbstractThis paper describes silicide and salicide technologies in Japan for 0.35 μm CMOS ULSIs and beyond. Polycide gate electrodes have been developed for CMOS devices from 1.0 μm to 0.35 μm design rule regime, in which Wsi2 has been used dominantly as a silicide gate material. On the other hand, silicide films are formed selectively on source/drain diffusion layers by salicide techniques, in which TiSi2 is used as a salicide material. TiSi2 is also used as a salicide material of both gate electrodes and source/drain diffusion layers for dual gate (n+/p+) CMOS. The TiSi2 thin film is formed by Ti sputtering and subsequent rapid thermal annealing. A preamorphization technique before Ti sputtering has been developed to obtain equal silicide properties on p+ and n+ diffusion layers. A high-temperature Ti sputtering technique has been developed in conjunction with pre-amorphization. CoSi2 and NiSi have also been developed as salicide materials for quartermicron CMOS and beyond.
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Chen, An. "Beyond-CMOS roadmap - from Boolean logic to neuro-inspired computing." Japanese Journal of Applied Physics, March 14, 2022. http://dx.doi.org/10.35848/1347-4065/ac5d86.
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Abstract As one of the chapters in the International Roadmap of Device and Systems (IRDS), the “Beyond CMOS (BC)” roadmap surveys and catalogs emerging devices and materials, and evaluate their potential and challenges gating their acceptance by the industry. While CMOS is expected to continue to dominate as the platform technology, beyond-CMOS devices may enable novel computing paradigms and efficient hardware accelerators to augment the CMOS platform. Emerging device-architecture co-design and co-optimization are important for achieving the efficiency and functionalities beyond the limit of CMOS technologies. This paper provides a brief overview of the IRDS BC chapter, with the emphasis on the opportunities of beyond-CMOS devices and architectures for neuro-inspired computing paradigms.
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"Progress, Opportunities and Challenges for beyond CMOS Information Processing Technologies." ECS Meeting Abstracts, 2011. http://dx.doi.org/10.1149/ma2011-01/16/1123.
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Borland, John O. "Applications of MeV Ion Implantation in Semiconductor Device Manufacturing." MRS Proceedings 354 (1994). http://dx.doi.org/10.1557/proc-354-123.
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AbstractUse of MeV ion implantation for mass production of CMOS devices at 0.5um design rule and beyond is now being accepted around the world for 16Mb DRAM, 16Mb Flash memory and CMOS logic/microprocessor technologies. Incorporating MeV well formation for twin well and triple well results in a reduction of up to 3 masking layers corresponding to process simplification and manufacturing cost reduction of 10% to 16%. For CMOS logic application, a new structure called BILLI (Buriedjmplanted Layer for Lateral Isolation) is showing great promise for latch-up free CMOS and when combined with hydrogen denuded bulk Czochraliski (CZ) grown silicon wafers, has the potential to replace epitaxial wafers with improved device performance. This paper will review MeV ion implantation use for these various CMOS applications.
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Moslehi, Mehrdad M. "Rapid Thermal Processing Requirements for 0.35-µm IC Technologies and Beyond." MRS Proceedings 342 (1994). http://dx.doi.org/10.1557/proc-342-273.
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ABSTRACTThis paper will present an overview of rapid thermal processing (RTP) technologies for fastcycle-time IC production. RTP has experienced significant advances in equipment design, process control capabilities, and unit process applications over the past eight years. The Microelectronics Manufacturing Science and Technology (MMST) program at TI successfully demonstrated CMOS IC production in a single-wafer factory with all-RTP thermal fabrication for various anneals, oxidations, and chemical-vapor depositions. The use of RTP in conjunction with other single-wafer processes enabled 0.35 µm IC fabrication with a 3-day cycle time. Selected RTP equipment, sensor, and process control developments will be reviewed. The RTP applications and requirements for state-of-the-art and future IC technologies will be described.
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Kaul, Anupama B. "Carbon Nanomaterials for Energy Efficient Green Electronics." MRS Proceedings 1478 (2012). http://dx.doi.org/10.1557/opl.2013.195.
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AbstractDeveloping energy efficient electronics or green electronics is an area that is largely driven by the performance limitations of scaled Si-based CMOS due to the exceptionally high power dissipation and high leakage currents arising in such devices at nanoscale dimensions. It is clear now that Si-based CMOS has been stretched over the past several decades to the point that further miniaturization will make such simple size scaling non-sustainable in the future. New materials and technologies are thus vigorously being explored beyond Si, in order to overcome performance limitations from ultra-miniaturized Si-CMOS. Among these materials, carbon-based nanostructures such as graphene and carbon nanotubes are being considered as viable alternatives to Si-CMOS to enable energy efficient green electronics. Novel architectures for enabling low-power, energy-efficient computation are currently being explored, which include tunneling field-effect-transistors (TFETs), as well as nano-electro-mechanical-systems (NEMS) due to their abrupt ON/OFF transitions, low OFF state currents and high speed operation. In this paper, an overview of carbon nanomaterials is presented and the role they play in enabling energy efficient TFETs and NEMS is also highlighted. Finally, the emergence of a new class of 2D systems beyond graphene is discussed such as MoS2, which may open up new avenues for exploration and enabling applications in electronics.
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Liu, Jing, Hongxiang Mo, and Mehmet C. Ötürk. "A Study on Solid Phase Reactions of Ni and Pt on Si-Ge Alloys as Contacts to Ultra-Shallow P+N Junctions for CMOS Technology Nodes Beyond 70nm." MRS Proceedings 670 (2001). http://dx.doi.org/10.1557/proc-670-k7.2.
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ABSTRACTRecently, selectively deposited SiGeB alloys have been proposed to form ultra-shallow source/drain junctions for 35-70 nm CMOS. The technology provides super-abrupt junctions with above equilibrium dopant activation at temperatures lower than 800°C. In addition to their low resistivities, the lower bandgap of SiGeB provides the potential advantage of reducing the Schottky barrier height and therefore, the junction contact resistance. This is a critical concern for future CMOS technology nodes since the contact resistance will dominate the MOSFET series resistance unless new technologies yielding contact resistivities near 10−8 ω−cm2 are developed. This paper examines the solid phase reactions of Ni and Pt with SiGeB alloys in order to form self-aligned low resistivity contacts. The results show that both Ni and Pt can form germanosilicides with low sheet resistances. Furthermore, both metals can form self-aligned contacts with a contact resistivity near 10−8 ω−cm2.
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Kittl, J. A., Q. Z. Hong, H. Yang, N. Yu, M. Rodder, P. P. Apte, W. T. Shiau, C. P. Chao, T. Breedijk, and M. F. Pas. "Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos." MRS Proceedings 525 (1998). http://dx.doi.org/10.1557/proc-525-331.
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ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.
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Kittl, J. A., Q. Z. Hong, H. Yang, N. Yu, M. Rodder, P. P. Apte, W. T. Shiau, C. P. Chao, T. Breedijk, and M. F. Pas. "Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm CMOS." MRS Proceedings 514 (1998). http://dx.doi.org/10.1557/proc-514-255.
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ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.
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Zhang, Yihan, Prashant Muthuraman, Victoria Andino-Pavlovsky, Ilke Uguz, Jeffrey Elloian, and Kenneth L. Shepard. "Augmented ultrasonography with implanted CMOS electronic motes." Nature Communications 13, no. 1 (June 20, 2022). http://dx.doi.org/10.1038/s41467-022-31166-x.
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AbstractModern clinical practice benefits significantly from imaging technologies and much effort is directed toward making this imaging more informative through the addition of contrast agents or reporters. Here, we report the design of a battery-less integrated circuit mote acting as an electronic reporter during medical ultrasound imaging. When implanted within the field-of-view of a brightness-mode (B-mode) ultrasound imager, this mote transmits information from its location through backscattered acoustic energy which is captured within the ultrasound image itself. We prototype and characterize the operation of such motes in vitro and in vivo. Performing with a static power consumption of less than 57 pW, the motes operate at duty cycles for receiving acoustic energy as low as 50 ppm. Motes within the same field-of-view during imaging have demonstrated signal-to-noise ratios of more than 19.1 dB at depths of up to 40 mm in lossy phantom. Physiological information acquired through such motes, which is beyond what is measurable with endogenous ultrasound backscatter and which is biogeographically located within an image, has the potential to provide an augmented ultrasonography.
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Bhat, Navakanta. "Nanotechnology and the Future of Computation, Storage and Perception." Advanced Computing and Communications, June 30, 2019. http://dx.doi.org/10.34048/2019.2.f1.
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The continued miniaturization of devices in the nanoscale regime, and the capability to manipulate the matter at these dimensions is expected to revolutionize the future systems for computation, storage and perception in the next few decades. Nanotechnology is not just a natural evolution of the miniaturization trend from sub-100 micrometer scale to sub-100 nanometer scale. The emergence of quantum effects at nanoscale, with a significant departure from the continuum approximation of physical, chemical and biological processes, brings in exciting new possibilities with nanotechnology. In the next few decades, we will go beyond the conventional charge based, digital Silicon CMOS technology, and incorporate several emerging technologies that exploit nanoscale phenomena, to realize extremely powerful machines for high performance computation with augmented perception, mimicking the human brain and sensory organs.