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Journal articles on the topic 'ATM switch architecture'

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Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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1

Imagawa, Hitoshi, Shigeo Urushidani, and Koichi Hagishima. "An ATM self-routeing switch architecture." International Journal of Digital & Analog Cabled Systems 1, no. 4 (October 1988): 229–35. http://dx.doi.org/10.1002/dac.4520010409.

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2

Sung Hyuk Byun and Dan Keun Sung. "The UniMIN switch architecture for large-scale ATM switches." IEEE/ACM Transactions on Networking 8, no. 1 (2000): 109–20. http://dx.doi.org/10.1109/90.836482.

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3

Amin, Amani, and Hanaa Ibrahim. "AN ARCHITECTURE FOR SCALABLE MULTICAST ATM SWITCH." International Conference on Electrical Engineering 1, no. 1 (March 1, 1998): 512–27. http://dx.doi.org/10.21608/iceeng.1998.61109.

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4

Chitizadeh, J., and A. Varghani. "ATM switch with dual transceiver ring architecture." IEE Proceedings - Communications 150, no. 3 (2003): 184. http://dx.doi.org/10.1049/ip-com:20030219.

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5

Alaiwan, Haissam. "IBM 8265 ATM Backbone Switch hardware architecture." Computer Networks 31, no. 6 (March 1999): 527–39. http://dx.doi.org/10.1016/s0169-7552(98)00280-3.

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6

Alaiwan, Haissam. "IBM 8265 ATM Backbone Switch software architecture." Computer Networks 31, no. 6 (March 1999): 541–58. http://dx.doi.org/10.1016/s0169-7552(98)00281-5.

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7

Shobatake, Yasuro. "The barrel switch: An ATM switch architecture for high-speed switching." Electronics and Communications in Japan (Part I: Communications) 77, no. 10 (October 1994): 11–20. http://dx.doi.org/10.1002/ecja.4410771002.

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8

Chimaru, T., S. Shimizu, M. Omotani, M. Uga, and K. Shiomoto. "Scalable multi-QoS IP+ATM switch router architecture." IEEE Communications Magazine 38, no. 12 (2000): 86–92. http://dx.doi.org/10.1109/35.888262.

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9

Et. al., Vishal Chandra ,. "VLSI Design of A Chip With High Speed Atm Switch-A Review." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (April 10, 2021): 1655–59. http://dx.doi.org/10.17762/turcomat.v12i2.1451.

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Abstract:

In current computer communication network, it is overwhelmed by two technologies, in particular Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Association situated ATM is the awesome constant administrations which require ensured nature of-administration like video conferencing. Be that as it may, connectionless IP is more proficient than ATM for non-ongoing administrations like email. Right now, the significant exploration challenge is on the most proficient method to coordinate ATM and IP into a solitary network effectively. It is shown by the acknowledgment of the highlight of the A/I Net architecture: the A/I Switch. In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. In view of a piece cut architecture, the whole 16x16 switch is acknowledged utilizing four indistinguishable chips. It accomplishes elite by using dispersed control and accelerate with the input-output buffering technique. A need structure, which upholds four-level, permits the postponement delicate ATM cells to be switched with the briefest inertness. It likewise empowers the non-interleaving directing plan of IP cells.

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10

de Vries, R. J. F. "Gauss: a simple high performance switch architecture for ATM." ACM SIGCOMM Computer Communication Review 20, no. 4 (August 1990): 126–34. http://dx.doi.org/10.1145/99517.99544.

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11

Sheu, T. L., and G. J. Lin. "Multiple-path ATM switch architecture for dynamic VC establishment." IEE Proceedings - Computers and Digital Techniques 148, no. 3 (May 1, 2001): 119–27. http://dx.doi.org/10.1049/ip-cdt:20010400.

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12

Yamamoto, M., H. Tode, H. Okada, and Y. Tezuka. "A control-ahead ATM switch architecture and its performance." IEEE Journal on Selected Areas in Communications 9, no. 9 (1991): 1549–59. http://dx.doi.org/10.1109/49.108690.

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13

Shiann-Tsong Sheu, Yang-Han Lee, and Chih-Chiang Wu. "A smart photonic ATM switch architecture with compression strategy." Journal of Lightwave Technology 19, no. 1 (2001): 1–10. http://dx.doi.org/10.1109/50.914479.

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14

Al-Mouhamed, Mayez, Habib Youssef, and Wasif Hasan. "A fast parallel-tree switch architecture for ATM networks." International Journal of Communication Systems 11, no. 1 (January 1998): 59–77. http://dx.doi.org/10.1002/(sici)1099-1131(199801/02)11:1<59::aid-dac344>3.0.co;2-w.

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15

Abd-El-Barr, Mostafa, Khalid Al-Tawil, Habib Youssef, and Talha Al-Jarad. "RAZAN: a high-performance switch architecture for ATM networks." International Journal of Communication Systems 11, no. 4 (July 1998): 275–85. http://dx.doi.org/10.1002/(sici)1099-1131(199807/08)11:4<275::aid-dac367>3.0.co;2-9.

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16

Genda, Kouichi, Naoaki Yamanaka, Yukihiro Doi, and Kenichi Endo. "A 160 GB/s ATM switch using internal speed-up crossbar switch architecture." Electronics and Communications in Japan (Part I: Communications) 80, no. 9 (September 1997): 68–79. http://dx.doi.org/10.1002/(sici)1520-6424(199709)80:9<68::aid-ecja8>3.0.co;2-#.

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17

Eng, K. Y., M. J. Karol, and Y. S. Yeh. "A growable packet (ATM) switch architecture: design principles and application." IEEE Transactions on Communications 40, no. 2 (1992): 423–30. http://dx.doi.org/10.1109/26.129204.

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18

Pattavina, A. "An ATM switch architecture for provision of integrated broadband services." IEEE Journal on Selected Areas in Communications 9, no. 9 (1991): 1537–48. http://dx.doi.org/10.1109/49.108689.

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19

Kumar, S., and D. P. Agrawal. "On multicast support for shared-memory-based ATM switch architecture." IEEE Network 10, no. 1 (1996): 34–39. http://dx.doi.org/10.1109/65.484230.

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20

Yamada, Y., K. Sasayama, K. Habara, A. Misawa, M. Tsukada, T. Matsunaga, and K. Yukimatsu. "Optical output buffered ATM switch prototype based on FRONTIERNET architecture." IEEE Journal on Selected Areas in Communications 16, no. 7 (1998): 1298–308. http://dx.doi.org/10.1109/49.725197.

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21

Segkhoonthod, S., and M. C. Sinclair. "Design of fault-tolerant ATM switch based on parallel architecture." Electronics Letters 33, no. 15 (1997): 1289. http://dx.doi.org/10.1049/el:19970865.

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22

Genda, K., and N. Yamanaka. "TORUS-switch: A scalable internal speed-up ATM switch architecture and its 5 Gbit/s switch LSI." Electronics Letters 31, no. 11 (May 25, 1995): 906–8. http://dx.doi.org/10.1049/el:19950578.

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23

Kim, H. S. "Design and performance of Multinet switch: a multistage ATM switch architecture with partially shared buffers." IEEE/ACM Transactions on Networking 2, no. 6 (1994): 571–80. http://dx.doi.org/10.1109/90.365416.

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24

Simcoe, Robert J., and Tong-Bi Pei. "Perspectives on ATM switch architecture and the influence of traffic pattern assumptions on switch design." ACM SIGCOMM Computer Communication Review 25, no. 2 (April 1995): 93–105. http://dx.doi.org/10.1145/210613.210626.

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25

Jain, Vijay K., Lei Lin, and Susumu Horiguchi. "Architecture, defect tolerance, and buffer design for a new ATM switch." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 21, no. 4 (November 1998): 338–45. http://dx.doi.org/10.1109/96.730417.

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26

Bianchini, R. P., and H. S. Kim. "The Tera project: a hybrid queueing ATM switch architecture for LAN." IEEE Journal on Selected Areas in Communications 13, no. 4 (May 1995): 673–85. http://dx.doi.org/10.1109/49.382158.

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27

Genda, K., and N. Yamanaka. "TORUS: terabit-per-second ATM switching system architecture based on distributed internal speed-up ATM switch." IEEE Journal on Selected Areas in Communications 15, no. 5 (June 1997): 817–29. http://dx.doi.org/10.1109/49.594844.

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28

Toh, Chai-Keong. "Crossover switch discovery for wireless ATM LANs." Mobile Networks and Applications 1, no. 2 (June 1996): 141–65. http://dx.doi.org/10.1007/bf01193334.

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29

Wang, Ying, Zhi Yi Fang, Hao Zhang, and Ang Liu. "Designing a Parallel Switch Simulator Based on OpenMP." Applied Mechanics and Materials 644-650 (September 2014): 3834–39. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3834.

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‘SIM’ is the abstraction of ATM Switching Architecture Simulator which is developed by Stanford University based on time-slot. It’s produced to simulate ATM network. With the SIM, users can simulate the ATM switchboard in accordance with their needs on Linux platform. Multi-core CPU programming technology enable programs parallelized and achieve high improvement on performance. Therefore we bring this idea to develop a parallelized switch simulator called PSIM in this paper.

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30

Al-Wakeel, Sami S. "Architecture Design of an ATM Switch Based on a High Speed Network." Journal of King Saud University - Computer and Information Sciences 9 (1997): 125–48. http://dx.doi.org/10.1016/s1319-1578(97)80007-9.

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31

Weil, D., A. Botta, A. Chemarin, P. Gallay, J. Majos, and M. Servel. "A 16×622 Mb/s ATM switch: PRELUDE switch architecture integrated into a 6-million transistor monochip." IEEE Journal of Solid-State Circuits 32, no. 7 (July 1997): 1108–14. http://dx.doi.org/10.1109/4.597301.

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32

Wen De Zhong, M. Tsukada, K. Yukimatsu, and Y. Shimazu. "Terahipas: a modular and expandable terabit/second hierarchically multiplexing photonic ATM switch architecture." Journal of Lightwave Technology 12, no. 7 (July 1994): 1307–15. http://dx.doi.org/10.1109/50.301823.

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33

Shobatake, Y., M. Motoyama, E. Shobatake, T. Kamitake, S. Shimizu, M. Noda, and K. Sakaue. "A one-chip scalable 8*8 ATM switch LSI employing shared buffer architecture." IEEE Journal on Selected Areas in Communications 9, no. 8 (1991): 1248–54. http://dx.doi.org/10.1109/49.105171.

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34

Vishnu, M., and J. W. Mark. "A novel implementation approach for an ATM switch with a per-VC architecture." Canadian Journal of Electrical and Computer Engineering 22, no. 4 (October 1997): 177–83. http://dx.doi.org/10.1109/cjece.1997.7101941.

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35

Lin, Arthur Y. M., and John A. Silvester. "Queueing analysis of an ATM switch with multichannel transmission groups." ACM SIGMETRICS Performance Evaluation Review 18, no. 1 (April 1990): 96–105. http://dx.doi.org/10.1145/98460.98514.

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36

Kondoh, H., H. Notani, H. Yamanaka, K. Higashitani, H. Saito, I. Hayashi, S. Kohama, Y. Matsuda, K. Oshima, and M. Nakaya. "A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture." IEEE Journal of Solid-State Circuits 28, no. 7 (July 1993): 808–15. http://dx.doi.org/10.1109/4.222180.

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37

Obara, H., S. Okamoto, and Y. Hamazumi. "Input and output queueing ATM switch architecture with spatial and temporal slot reservation control." Electronics Letters 28, no. 1 (January 2, 1992): 22–24. http://dx.doi.org/10.1049/el:19920014.

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38

Chiueh, Tzi-cker, and Srinidhi Varadarajan. "Design and evaluation of a DRAM-based shared memory ATM switch." ACM SIGMETRICS Performance Evaluation Review 25, no. 1 (June 1997): 248–59. http://dx.doi.org/10.1145/258623.258693.

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39

Rathgeb, E. P., W. Fischer, C. Hinterberger, E. Wallmeier, and R. Wille-Fier. "The MainStreetXpress core services node-a versatile ATM switch architecture for the full service network." IEEE Journal on Selected Areas in Communications 15, no. 5 (June 1997): 795–806. http://dx.doi.org/10.1109/49.594842.

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40

Kouvatsos, Demetres D., and Spiros G. Denazis. "A universal building block for the approximate analysis of a shared buffer ATM switch architecture." Annals of Operations Research 49, no. 1 (December 1994): 241–78. http://dx.doi.org/10.1007/bf02031600.

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41

Eng, K. Y., M. A. Pashan, R. A. Spanke, M. J. Karoll, G. D. Martin, H. Obara, and H. Ueda. "A Prototype Growable 2.5 Gb/s ATM Switch for Broadband Applications." Journal of High Speed Networks 1, no. 3 (1992): 237–53. http://dx.doi.org/10.3233/jhs-1992-1303.

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42

Choudhury, Abhijit K., and Ellen L. Hahne. "A Simulation Study of Space Priorities in a Shared Memory ATM Switch." Journal of High Speed Networks 3, no. 4 (1994): 491–512. http://dx.doi.org/10.3233/jhs-1994-3409.

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43

Takahashi, Masahiro, Yoshinori Ohkura, and Takuji Hamada. "An Experimental Loop-type ATM-LAN System using Onboard Distributed Switch Architecture and Evaluation of Transmission Delay." IEEJ Transactions on Electronics, Information and Systems 120, no. 10 (2000): 1452–57. http://dx.doi.org/10.1541/ieejeiss1987.120.10_1452.

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44

Ahn, David S., Sang Lee, and Myung J. Lee. "Effective cell loss analysis of a nonblocking ATM switch with nonuniform traffic." Journal of Network and Systems Management 4, no. 1 (March 1996): 7–29. http://dx.doi.org/10.1007/bf02139045.

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45

McKinnon, Martin W., George N. Rouskas, and Harry G. Perros. "Performance analysis of a photonic single-hop ATM switch architecture, with tunable transmitters and fixed frequency receivers." Performance Evaluation 33, no. 2 (July 1998): 113–36. http://dx.doi.org/10.1016/s0166-5316(98)00003-0.

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46

Jung, Y. C. "Analysis of out-of-sequence problem and preventative schemes in parallel switch architecture for high-speed ATM network." IEE Proceedings - Communications 141, no. 1 (1994): 29. http://dx.doi.org/10.1049/ip-com:19949804.

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47

Zaghloul, Atef O., and Harry G. Perros. "Approximate analysis of a shared-medium ATM switch under bursty arrivals and nonuniform destinations." Performance Evaluation 21, no. 1-2 (November 1994): 111–29. http://dx.doi.org/10.1016/0166-5316(94)90030-2.

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48

Choi, Jin Seek, Kye Sang Lee, and Chong Kwan Un. "Performance comparison of nonpreemptive and preemptive priority queueing strategies in ATM packet switch with input buffers." Performance Evaluation 29, no. 3 (April 1997): 177–94. http://dx.doi.org/10.1016/s0166-5316(96)00004-1.

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49

Nilsson, Arne A., Harry G. Perros, and Fuyung Lai. "A Queueing Model of a Bufferless Synchronous Clos ATM Switch with Head-of-Line Priority and Push-Out." Journal of High Speed Networks 1, no. 3 (1992): 255–79. http://dx.doi.org/10.3233/jhs-1992-1304.

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50

Awdeh, Ra'ed Y., and H. T. Mouftah. "Survey of ATM switch architectures." Computer Networks and ISDN Systems 27, no. 12 (November 1995): 1567–613. http://dx.doi.org/10.1016/0169-7552(94)00081-4.

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