Relevant bibliographies by topics / ATM switch architecture

Academic literature on the topic 'ATM switch architecture'

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Published: 4 June 2021
Last updated: 7 February 2022

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Journal articles on the topic "ATM switch architecture"

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Imagawa, Hitoshi, Shigeo Urushidani, and Koichi Hagishima. "An ATM self-routeing switch architecture." International Journal of Digital & Analog Cabled Systems 1, no. 4 (October 1988): 229–35. http://dx.doi.org/10.1002/dac.4520010409.

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Sung Hyuk Byun and Dan Keun Sung. "The UniMIN switch architecture for large-scale ATM switches." IEEE/ACM Transactions on Networking 8, no. 1 (2000): 109–20. http://dx.doi.org/10.1109/90.836482.

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Amin, Amani, and Hanaa Ibrahim. "AN ARCHITECTURE FOR SCALABLE MULTICAST ATM SWITCH." International Conference on Electrical Engineering 1, no. 1 (March 1, 1998): 512–27. http://dx.doi.org/10.21608/iceeng.1998.61109.

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Chitizadeh, J., and A. Varghani. "ATM switch with dual transceiver ring architecture." IEE Proceedings - Communications 150, no. 3 (2003): 184. http://dx.doi.org/10.1049/ip-com:20030219.

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Alaiwan, Haissam. "IBM 8265 ATM Backbone Switch hardware architecture." Computer Networks 31, no. 6 (March 1999): 527–39. http://dx.doi.org/10.1016/s0169-7552(98)00280-3.

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Alaiwan, Haissam. "IBM 8265 ATM Backbone Switch software architecture." Computer Networks 31, no. 6 (March 1999): 541–58. http://dx.doi.org/10.1016/s0169-7552(98)00281-5.

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Shobatake, Yasuro. "The barrel switch: An ATM switch architecture for high-speed switching." Electronics and Communications in Japan (Part I: Communications) 77, no. 10 (October 1994): 11–20. http://dx.doi.org/10.1002/ecja.4410771002.

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Chimaru, T., S. Shimizu, M. Omotani, M. Uga, and K. Shiomoto. "Scalable multi-QoS IP+ATM switch router architecture." IEEE Communications Magazine 38, no. 12 (2000): 86–92. http://dx.doi.org/10.1109/35.888262.

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Et. al., Vishal Chandra ,. "VLSI Design of A Chip With High Speed Atm Switch-A Review." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (April 10, 2021): 1655–59. http://dx.doi.org/10.17762/turcomat.v12i2.1451.

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In current computer communication network, it is overwhelmed by two technologies, in particular Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Association situated ATM is the awesome constant administrations which require ensured nature of-administration like video conferencing. Be that as it may, connectionless IP is more proficient than ATM for non-ongoing administrations like email. Right now, the significant exploration challenge is on the most proficient method to coordinate ATM and IP into a solitary network effectively. It is shown by the acknowledgment of the highlight of the A/I Net architecture: the A/I Switch. In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. In view of a piece cut architecture, the whole 16x16 switch is acknowledged utilizing four indistinguishable chips. It accomplishes elite by using dispersed control and accelerate with the input-output buffering technique. A need structure, which upholds four-level, permits the postponement delicate ATM cells to be switched with the briefest inertness. It likewise empowers the non-interleaving directing plan of IP cells.
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de Vries, R. J. F. "Gauss: a simple high performance switch architecture for ATM." ACM SIGCOMM Computer Communication Review 20, no. 4 (August 1990): 126–34. http://dx.doi.org/10.1145/99517.99544.

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Dissertations / Theses on the topic "ATM switch architecture"

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Chen, Hong Xu, and n/a. "A high performance ATM switch architecture." Swinburne University of Technology, 2006. http://adt.lib.swin.edu.au./public/adt-VSWT20070405.172354.

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ATM is based on the efforts of the ITU-T Broadband Integrated Services Digital Network (B-ISDN) standard. It was originally conceived as a high-speed transfer technology for voice, video, and data over public networks. The ATM Forum has broadened the ITU-T�s vision of ATM for extended use over public and private networks, multi-protocol support and mobile ATM. There are also some ATM applications in High Performance Computing (HPC). ATM is a packet switching technique based on a virtual circuit mechanism. Data flows are statistically multiplexed and communication resources are dynamically shared. Therefore the high performance ATM switch is essential for quality of services (QoS). This thesis introduces typical ATM switch architecture design and analyses design problems. The research objective is to propose a switch architecture design that can solve or improve those existing problems to achieve a superior performance. The research goal is an integrated ATM switch architecture that will handle both unicast and multicast packets. Unlike the usual design for the multicast ATM switch which concentrates on a cell copy network with a unicast switching network, the proposed switch architecture processes the network packets in a single switching block, and allows unicast and multicast packets to co-exist without competing. The switch design has a simple topology and operation principle and is easy to implement. Furthermore, no copy network is required. Three major components are proposed to form the core of the new switch architecture: the parallel buffering strategy for improved buffer performance, the fast table lookup algorithm for packet duplication and routing, and the relay ring controller for solving the contention problem associated with multiple packets destined for the same output port. A mathematical model is presented and its numerical results are analysed. In addition, the simulation algorithms for the proposed switching design are presented and compared against the switching design with input and output buffering strategies. The simulation results are also compared and analysed against the numerical results. A multicast traffic model is also presented. Its performance calculation for the proposed switch is achieved through simulation. Performance analysis is compared against the output buffering switch under the same multicast traffic model. The performance analysis shows that the proposed switch architecture achieves high throughput with low cell loss rate and low time delay. Its performance can be as good as the output buffering strategy or better. Therefore the proposed switch design has solved the problems associated with input and output buffering. This thesis also analyses the complexity of the proposed switch architecture and suggests a topology to build a large scale ATM switch. The suitability and feasibility for production implementation are also addressed.
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Chen, Hong Xu. "A high performance ATM switch architecture." Australasian Digital Thesis Program, 2007. http://adt.lib.swin.edu.au/public/adt-VSWT20070405.172354/index.html.

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Thesis (Ph.D) - Swinburne University of Technology, Faculty of Information & Communication Technologies, 2006.
A thesis submitted for the degree of Doctor of Philosophy, Faculty of Information and Communication Technologies, Swinburne University of Technology, 2006. Typescript. Bibliography p. ?? Includes bibliographical references (p. 135-142).
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Segkhoonthod, Sak. "Design, analysis and simulation of a fault-tolerant ATM switch based on a parallel architecture." Thesis, University of Essex, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246190.

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Sezer, Sakir. "An investigation into novel ATM switch architectures." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.314143.

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Podaima, Jason Edward. "A content addressable FIFO for shared memory ATM switch architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0001/MQ40944.pdf.

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Zarour, Rachid. "A class of ATM switch architectures based on bridged shuffle exchange networks." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1996. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq20599.pdf.

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DeBenedetto, Louis J. "A Survey of Scalable Real-Time Architectures for Data Acquisition Systems." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/606834.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada
Today’s large-scale signal processing systems impose massive bandwidth requirements on both internal and external communication systems. Most often, these bandwidth requirements are met by scalable input/output architectures built around high-performance, standards-based technology. Several such technologies are available and are in common use as internal and/or external communication mechanisms. This paper provides an overview of some of the more common scalable technologies used for internal and external communications in real-time data acquisition systems. With respect to internal communications mechanisms this paper focuses on three ANSI-standard switched fabric technologies: RACEway (ANSI/VITA 5-1994), SKYchannel (ANSI/VITA 10-1995) and Myrinet (ANSI/VITA 26-1998). The discussion then turns to how Fibre Channel, HiPPI, and ATM are used to provide scalable external communications in real-time systems. Finally, glimpse of how these technologies are evolving to meet tomorrow’s requirements is provided.
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Lin, Gwo-Jou, and 林國洲. "An ATM Switch Architecture with Multipath VC Establishment." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/06338483727610914365.

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碩士
國立中山大學
電機工程學系研究所
86
In this thesis, we present a novel a novel ATM switch with Multi-Path Virtual-Channel (MPVC) architecture. Base on the traffic load or a predefined cell loss ratio. the switch can change its internal structure from a single-path VC to a nulti-path VC. In other words. when cell loss ratio is low, a single-path VC will bechosen. On the other hand, multi-path VC will be used to reduce the cell loss ratio and increase the overall system throughput. 　　Three significant innovations in this thesis are 　　(1)Switch-cell header design to allow the switch to support both single-path VC and multi -path VC; 　　(2)Cell resequencing algorithm to reorder the cell sequence with minimum cost when multi-path VC is used;and 　　(3)Balanced Bandwidth Alloction (BBA) Algorithm to reserve bandwidth evenly for a call request with multi-path VC. 　　We analyze the MPVC switch architecture using both mathematical. model and simulation model. In mathematical model, we mainly focus on the evaluation of a call-reject probability of the proposed MPVC architecture based on a Gaussian distribution function. In simulation model, first we verify the call-reject probability derived from the mathematical model. Then, we compare the performance of single-path VC and multi-path VC in terms of end -to-end cell transfer delay, cell loss ratio, and system throughput under different traffic loads and buffer sizes.
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Fang, Hsin-Hsiung, and 方信雄. "A Novel Multicast Architecture gor Shared Buffer Type ATM Switch." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/73603311628249746588.

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碩士
國立交通大學
電子研究所
84
B-ISDN is expected to provide versatile communication service based on ATMtechnology. The capability of multicast is important to support many servicessuch as VOD (video-on-demand), video conference, LAN emulation, etc. In thisthesis, we present a new architecture to support multicast virtual connectionin an ATM switch. This architecture is designed to achieve high throughput,efficiency and flexibility. By queuing input multicast cells in multicastqueues, each multicast cell occupies only one-cell buffer space, this archi-tecture can achieve very low cell loss probability. These multicast queues also share the same buffer memory with all other unicast queues, the utili- zation of buffer memory is very efficient. And the structure of buffer memory is the same with that for unicast, no special design is needed. The multicast table is also shared by all ports to improve table utilization. Modular designenables the flexibility of table size, multiple table chipscan be cascaded to construct a larger multicast table to meet system requirement. Because the multicast table is shared by all ports, short translation delay is critical inthe improvement of throughput. We also present a PLL clock generator with on-chip RC filter, which can generate an internal clock of quad frequency, that will be integrated to raise the processing speed.
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"Designing a large scale switch interconnection architecture and a study of ATM scheduling algorithms." 1997. http://library.cuhk.edu.hk/record=b5889253.

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by Yee Ka Chi.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.
Includes bibliographical references (leaves 101-[106]).
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Background --- p.1
Chapter 1.1.1 --- Large Scale Switch Interconnections --- p.2
Chapter 1.1.2 --- Multichannel Switching and Resequencing --- p.6
Chapter 1.1.3 --- Scheduling --- p.7
Chapter 2 --- Hierarchical Banyan Switch Interconnection --- p.12
Chapter 2.1 --- Introduction --- p.12
Chapter 2.2 --- Switch Architecture --- p.13
Chapter 2.3 --- Switch Operation --- p.19
Chapter 2.3.1 --- Call Setup --- p.19
Chapter 2.3.2 --- Cell Routing --- p.21
Chapter 2.3.3 --- Fault Tolerance --- p.27
Chapter 2.4 --- Call Blocking Analysis --- p.28
Chapter 2.4.1 --- Dilated Banyan --- p.29
Chapter 2.4.2 --- Dilated Benes Network --- p.30
Chapter 2.4.3 --- HBSI --- p.30
Chapter 2.5 --- Results and Discussions --- p.31
Chapter 2.6 --- Summary --- p.37
Chapter 3 --- Multichannel Switching and Resequencing --- p.40
Chapter 3.1 --- Introduction --- p.40
Chapter 3.2 --- Channel Assignment --- p.41
Chapter 3.2.1 --- VC-Based Channel Allocation Mechanism --- p.41
Chapter 3.2.2 --- Port-Based Channel Allocation Mechanism --- p.45
Chapter 3.2.3 --- Trunk-Based Channel Allocation Mechanism --- p.46
Chapter 3.3 --- Resequencer --- p.50
Chapter 3.3.1 --- Resequencing Algorithm --- p.50
Chapter 3.4 --- Results and Discussion --- p.55
Chapter 3.5 --- Summary --- p.60
Chapter 4 --- Scheduling --- p.62
Chapter 4.1 --- Introduction --- p.62
Chapter 4.2 --- Virtual Clock Scheduling (VCS) --- p.62
Chapter 4.3 --- Gated Virtual Clock Scheduling (GVCS) --- p.70
Chapter 4.4 --- Time-Priority Model --- p.75
Chapter 4.5 --- Programmable Rate-based Scheduler (PRS) --- p.80
Chapter 4.6 --- Integration with Resequencer --- p.83
Chapter 4.7 --- Results and Discussions --- p.86
Chapter 4.8 --- Summary --- p.96
Chapter 5 --- Conclusion --- p.99
Bibliography --- p.101
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Books on the topic "ATM switch architecture"

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Podaima, Jason Edward. A content addressable FIFO for shared memory ATM switch architectures. Ottawa: National Library of Canada, 1998.

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Book chapters on the topic "ATM switch architecture"

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Yamashita, H., H. G. Perros, and S. W. Hong. "An Approximation Analysis of a Shared Buffer ATM Switch Architecture under Bursty Arrivals." In High-Capacity Local and Metropolitan Area Networks, 345–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76484-4_19.

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Kouvatsos, D., J. Wilkinson, P. Harrison, and M. Bhabuta. "Performance Analysis of Buffered Banyan ATM Switch Architectures." In ATM Networks, 287–323. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-0-387-35068-4_16.

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Katevenis, Manolis G. H., Dimitrios Serpanos, Panagiota Vatsolaki, and Evangelos Markatos. "ATLAS I: A single-chip ATM switch for NOWs." In Communication and Architectural Support for Network-Based Parallel Computing, 88–101. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-62573-9_7.

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Tsang, Rose P., Jenwei Hsieh, and David H. C. Du. "The Effect of Various ATM Switch Architectures on VBR Video Performance." In High Performance Networking VII, 87–100. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35279-4_6.

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Brumme, Thomas, Rafael Gutiérrez, and Gianaurelio Cuniberti. "Vibrational Heating in Single-Molecule Switches." In Architecture and Design of Molecule Logic Gates and Atom Circuits, 87–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-33137-4_7.

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González-Sánchez, José Luis, Jordi Domingo-Pascual, and João Chambel Vieira. "AcTMs (Active ATM Switches) with TAP (Trusted and Active PDU Transfers) in a Multiagent Architecture to Better the Chaotic Nature of TCP Congestion Control." In Networking - ICN 2005, 266–74. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/978-3-540-31957-3_33.

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Thompson, Brian J. "Atm Switch Architecture and Systems." In High-Performance Backbone Network Technology, 241–366. CRC Press, 2020. http://dx.doi.org/10.1201/9781315214672-3.

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Rana, Vincenzo, Marco Domenico Santambrogio, and Simone Corbetta. "Dynamic Reconfigurable NoCs." In Dynamic Reconfigurable Network-on-Chip Design, 158–85. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch007.

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The aim of this chapter is the definition of the main issues that arise when dealing with the design of a NoC-based reconfigurable system. In particular, after the definition of the target architecture, several factors, requirements and constraints that have to be taken into account during the design of reconfigurable NoCs will be described and analyzed. The second part of this chapter will focus on the main issues in dynamic reconfigurable NoCs design, such as the definition of a layered approach, of a packet-switched communication infrastructure, of a proper routing mechanism and of a communication protocol support. Finally, the last part of this chapter will deal with the description of the most relevant implementation details, such as the placement of the bus-macros, the design of the network switches and the physical implementation of the routing mechanism.
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Conference papers on the topic "ATM switch architecture"

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Albertengo, G. "An optimal packet switch architecture for ATM." In IEEE INFCOM '91. The conference on Computer Communications. Tenth Annual Joint Comference of the IEEE Computer and Communications Societies Proceedings. IEEE, 1991. http://dx.doi.org/10.1109/infcom.1991.147537.

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Munter, Ernst A. "High-capacity ATM switch: architecture and technologies." In Photonics West '96, edited by Thomas J. Cloonan. SPIE, 1996. http://dx.doi.org/10.1117/12.235850.

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Ruck, Herbert M. "ATM-based SMDS switch architecture and performance." In OE Fiber - DL tentative, edited by Kadiresan Annamalai. SPIE, 1992. http://dx.doi.org/10.1117/12.134905.

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de Vries, R. J. F. "Gauss: a simple high performance switch architecture for ATM." In the ACM symposium. New York, New York, USA: ACM Press, 1990. http://dx.doi.org/10.1145/99508.99544.

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Ushadevi, M. B., H. M. Mahesh, and H. M. Ravikumar. "Low-latency scalable switch architecture for ATM/WDM high-speed networks." In 2007 International Conference on Intelligent and Advanced Systems (ICIAS). IEEE, 2007. http://dx.doi.org/10.1109/icias.2007.4658430.

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Segkhoonthod, S. "Analysis of a fault-tolerant ATM switch based on a parallel architecture." In IEE Colloquium: Twelfth UK Teletraffic Symposium Performance Engineering in Telecommunications Networks. IEE, 1995. http://dx.doi.org/10.1049/ic:19950370.

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Charleston, Giles C., Thomas Christofili, Armand M. Makowski, Prakash Narayan, Sandeep Rao, Jangkyung Kim, Jong-Hee Lee, and Man-Geun Ryu. "ALAX—A P1355-based architecture for an ATM LAN access switch, with application to ATM onboard switching." In Space technology and applications international forum: 1st conference on commercial development of space; 1st conference on next generation launch systems; 2nd spacecraft thermal control symposium; 13th symposium on space nuclear power and propulsion. AIP, 1996. http://dx.doi.org/10.1063/1.50030.

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Kondoh, H., H. Notani, H. Yamanaka, K. Higashitani, H. Saito, I. Hayashi, S. Kohama, Y. Matsuda, K. Oshima, and M. Nakaya. "A 622Mbps 8×8 ATM Switch Chip Set with Shared Multi-Buffer Architecture." In Eighteenth European Solid-State Circuits Conference (ESSCIRC '92). IEEE, 1992. http://dx.doi.org/10.1109/esscirc.1992.5468236.

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Kim, Jangkyung, Il-Young Chong, Giles Charleston, Thomas Christofili, Armand Makowski, Prakash Narayan, Sandeep Rao, Man-Geun Ryu, and Jong-Hee Lee. "IEEE 1355-based architecture for an ATM switch - A case for onboard switching and processing." In 16th International Communications Satellite Systems Conference. Reston, Virigina: American Institute of Aeronautics and Astronautics, 1996. http://dx.doi.org/10.2514/6.1996-1041.

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Hunter, D. K. "ATM switch and crossconnect architectures." In IEE Colloquium on Optics and ATM. IEE, 1995. http://dx.doi.org/10.1049/ic:19950164.

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