Dissertations / Theses on the topic 'Asynchronous'
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Manbo, Olof. "Asynchronous Wrapper for Globally Asynchronous Locally Synchronous Systems." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1214.
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This thesis is investigating the new globally asynchronous locally synchronous (GALS) technology for integrated circuits. Different types of asynchronous wrappers are tested and a new wrapper design is presented. It also investigates the possibility to use VHDL for asynchronous simulation and synthesis. The conclusions are that the GALS technology is possible to use but that it needs new synthesis tools, because todays tools are designed for synchronous technology.
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Gajland, Phillip. "On Asynchronous Group Key Agreement : Tripartite Asynchronous Ratchet Trees." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-281322.
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The subject of secure messaging has gained notable attention lately in the cryptographic community. For communications between two parties, paradigms such as the double ratchet, used in the Signal protocol, provide provably strong security guarantees such as forward secrecy and post-compromise security. Variations of the Signal protocol have enjoyed widespread adoption and are embedded in several well known messaging services, including Signal, WhatsApp and Facebook Secret Conversations. However, providing equally strong guarantees that scale well in group settings remains somewhat less well studied and is often neglected in practice. This motivated the need for the IETF Messaging Layer Security (MLS) working group. The first continuous group key agreement (CGKA) protocol to be proposed was Asynchronous Ratcheting Trees (ART) [Cohn-Gordon et al., 2018] and formed the basis of TreeKEM [Barnes et al., 2019], the CGKA protocol currently suggested for MLS. In this thesis we propose a new asynchronous group key agreement protocol based on a one-round Tripartite Diffie-Hellman [Joux, 2000]. Furthermore, we show that our protocol can be generalised for an n-ary asynchronous ratchet tree, assuming the existence of a one-round (n + 1)-way Diffie-Hellman key exchange, based on a n-multilinear map [Boneh and Silverberg, 2003]. We analyse ART, TreeKEM, and our proposals from a complexity theoretic perspective and show that our proposals improve the cost of update operations. Finally we present some discussion and improvements to the IETF MLS standard.Ämnet om säkra meddelanden har på senare tid skapat uppmärksamhet inom kryptografiska samfundet. För kommunikationer mellan två parter ger paradigmer såsom Double Ratchet, som används i Signal-protokollet, starka bevisbara säkerhetsgarantier som forward secrecy och post-compromise security. Variationer av Signal-protokollet används mycket i praktiken och är inbäddade i flera välkända meddelandetjänster såsom Signal, WhatsApp och Facebook Secret Conversations. Däremot är protokoll som erbjuder lika starka garantier och som skalar väl i gruppsituationer något mindre studerade och ofta eftersatta i praktiken. Detta motiverade behovet av arbetsgruppen IETF Messaging Layer Security (MLS). Det första kontinuerliga gruppnyckelprotokollet (CGKA) som föreslogs var Asynchronous Ratcheting Trees (ART) [Cohn-Gordon et al., 2018] och lade grunden för TreeKEM [Barnes et al., 2019], det CGKA-protokoll som för närvarande föreslagits för MLS. I detta examensarbete föreslår vi ett nytt asynkront gruppnyckelprotokoll baserat på en en-rundad Tripartite Diffie{Hellman [Joux, 2000]. Vidare visar vi att vårt protokoll kan generaliseras för n-ary träd med hjälp av ett en-rundat (n + 1)-väg Diffie-Hellman nyckelutbyte, baserat på en multilinjär mappning [Boneh and Silverberg, 2003]. Vi analyserar ART, TreeKEM och våra förslag ur ett teoretiskt perspektiv samt visar att våra förslag förbättrar kostnaden för uppdateringsoperationer. Slutligen presenterar vi några diskussioner och förbättringar av IETF MLS-standarden.
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Prosser, Patrick. "Distributed asynchronous scheduling." Thesis, University of Strathclyde, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.296921.
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Dalrymple, David Allen. "Asynchronous logic automata." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/44914.
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Thesis (S.M.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2008.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 89-92).
Numerous applications, from high-performance scientific computing to large, high-resolution multi-touch interfaces to strong artificial intelligence, push the practical physical limits of modern computers. Typical computers attempt to hide the physics as much as possible, running software composed of a series of instructions drawn from an arbitrary set to be executed upon data that can be accessed uniformly. However, we submit that by exposing, rather than hiding, the density and velocity of information and the spatially concurrent, asynchronous nature of logic, scaling down in size and up in complexity becomes significantly easier. In particular, we introduce "asynchronous logic automata", which are a specialization of both asynchronous cellular automata and Petri nets, and include Boolean logic primitives in each cell. We also show some example algorithms, means to create circuits, potential hardware implementations, and comparisons to similar models in past practice.
by David Allen Dalrymple.
S.M.
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Chatterjee, Sandeep. "Asynchronous event handing." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/28177.
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Lieber, Thomas (Thomas Alan). "Understanding asynchronous code." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82411.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 61-64).
JavaScript on the web is difficult to debug due to its asynchronous and dynamic nature. Traditional debuggers are often little help because the language's idioms rely heavily on non-linear control flow via function pointers. The aim of this work is to create a debugging interface that helps users understand complicated control flow in languages like JavaScript. This thesis presents a programming editor extension called Theseus that uses program tracing to provide real-time in-editor feedback so that programmers can answer questions quickly as they write new code and interact with their application. Theseus augments the call graph with semantic edges that allow users to make intuitive leaps through program traces, such as from the start of an asynchronous network request to its response. Participants in lab and classroom studies found Theseus to be a usable replacement for traditional breakpoint and logging tools, though no significant difference was found in their ability to complete programming tasks.
by Thomas Lieber.
S.M.
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Nedelchev, Ivailo Marinov. "Asynchronous VLSI design." Thesis, University of Surrey, 1995. http://epubs.surrey.ac.uk/844150/.
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This thesis describes the background and implementation of a novel silicon compiler from a high-level programming language, OCCAM(async), to asynchronous CMOS circuits. The compilation scheme is based on a process algebra description of a concurrent system. This Algebra is called Delay-Insensitive Algebra and is based on CSP but allows the user more freedom in communication protocols. The thesis reviews and compares various, existing, design styles and their practical aspects for asynchronous design are also discussed. The syntax and the operational semantics of OCCAM(async) are defined and, on this basis, the new compilation technique is described with its underlying CMOS circuitry. The implementations of various, novel, library cells are also discussed. The compilation technique is illustrated throughout the thesis with practical examples. It is also compared to an existing synthesis tool, Tangram, which has been developed at Phillips Research Laboratories. The thesis concludes with the place and the role of OCCAM(async) in the contemporary CMOS design, and the future aspects in continuing this research into the full, design-process automation.
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Jones, Philip William Carleton University Dissertation Engineering Electrical. "Asynchronous sampling wattmeter." Ottawa, 1992.
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Heath, Michael Adam. "Asynchronous Database Drivers." BYU ScholarsArchive, 2010. https://scholarsarchive.byu.edu/etd/2387.
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Existing database drivers use blocking socket I/O to exchange data with relational database management systems (RDBMS). To concurrently send multiple requests to a RDBMS with blocking database drivers, a separate thread must be used for each request. This approach has been used successfully for many years. However, we propose that using non-blocking socket I/O is faster and scales better under load. In this paper we introduce the Asynchronous Database Connectivity in Java (ADBCJ) framework. ADBCJ provides a common API for asynchronous RDBMS interaction. Various implementations of the ADBCJ API are used to show how utilizing non-blocking socket I/O is faster and scales better than using conventional database drivers and multiple threads for concurrency. Our experiments show a significant performance increase when using non- blocking socket I/O for asynchronous RDBMS access while using a minimal number of OS threads. Non-blocking socket I/O enables the ability to pipeline RDBMS requests which can improve performance significantly, especially over high latency networks. We also show the benefits of asynchronous database drivers on different web server architectures.
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Kwan, Terry Tai-Wing. "Corridor asynchronous delta modulation." Thesis, University of Ottawa (Canada), 1989. http://hdl.handle.net/10393/5932.
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Chevrou, Florent. "Formalisation of asynchronous interactions." Phd thesis, Toulouse, INPT, 2017. http://oatao.univ-toulouse.fr/19493/1/CHEVROU_Florent.pdf.
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Large computing systems are generally built by connecting several distributed subsystems. The way these entities communicate is crucial to the proper functioning of the overall composed system. An in-depth study of these interactions makes sense in the context of the formal development and verification of such systems. The interactions fall in two categories: synchronous and asynchronous communication. In synchronous communication, the transmission of a piece of information - the message - is instantaneous. Asynchronous communication, on the other hand, splits the transmission in a send operation and a receive operation. This make the interleaving of other events possible and lead to new behaviours that may or may not be desirable. The asynchronous world is often viewed as a monolithic counterpart of the synchronous world. It actually comes in multiple models that provide a wide range of properties that can be studied and compared. This thesis focuses on communication models that order the delivery of messages: for instance, the "FIFO" models ensure that some messages are received in the order of their emission. We consider classic communication models from the literature as well as a few variations. We highlight the differences that are sometimes overlooked. First, we propose an abstract, logical, and homogeneous formalisation of the communication models and we establish a hierarchy that extends existing results. Second, we provide an operational approach with a tool that verifies the compatibility of compositions of peers. We mechanise this tool with the TLA+ specification language and its model checker TLC. The tool is designed in a modular fashion: the commmunicating peers, the temporal compatibility properties, and the communication models are specified independently. We rely on a set of uniform operational specifications of the communication models that are based on the concept of message history. We identify and prove the conditions under which they conform to the logical definitions and thus show the tool is trustworthy. Third, we consider concrete specifications of the communication models that are often found in the literature. Thus, the models are classified in terms of ordering properties and according to the level of abstraction of the different specifications. The concept of refinement covers these two aspects. Thus, we model asynchronous point-to-point communication along several levels of refinement and then, with the Event-B method, we establish and prove all the refinements between the communication models and the alternative specifications of each given model. This work results in a detailed map one can use to develop a new model or find the one that best fits given needs. Eventually we explore ways to extend our work to multicast communication that consists in sending messages to several recipients at once. In particular, we highlight the differences in the hierarchy of the models and how we modify our verification tool to handle this communication paradigm.
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Shankaran, Rajan, University of Western Sydney, and School of Computing and Information Technology. "Asynchronous transfer mode security." THESIS_XXX_CIT_Shankaran_R.xml, 1999. http://handle.uws.edu.au:8081/1959.7/252.
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There is a growing interest in the development of broadband services and networks for commercial use in both local area and wide area networks. The primary reasons for this is a pressing need to meet the demand for increased bandwidth for remote sites interconnection, and in high speed data transfer of bulk data such as images etc. There has also been a significant change in the characteristics of network traffic. It is increasingly taking the form of bursty traffic characterized by an unpredictable demand for bandwidth of several megabytes. A new generation of networking technologies have emerged to meet the demand of growing and uncertain bandwidth requirements. One such technology is called Asynchronous Transfer Mode (ATM) for use on broadband networks under the banner of broadband ISDN. ATM enables interconnection at high speeds in the range of Mbit/s or Gbit/s over wide areas, which effectively moves the bottleneck from networks to end systems. Furthermore, the user is able to access bandwidth on demand and the user is only charged for the bandwidth actually used. As more and more information (audio, image and data) is transferred over ATM networks, security issues are becoming increasingly critical. The rapidly growing use of the Internet to transfer confidential and sensitive information only enhances the importance of security services. One may even argue that the success of ATM will be determined not by its cost effectiveness but also to the level of trust that can be placed on its performance, security and availability. The objective of this dissertation is to address the issues involved in the design of security services for ATM networks.Master of Science (Hons)
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Aghdasi, Farhad. "Self-clocked asynchronous controllers." Thesis, University of Bristol, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.484279.
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Cunningham, P. A. "Verification of asynchronous circuits." Thesis, University of Cambridge, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598222.
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The purpose of this thesis is to introduce proposition-oriented behaviours and apply them to the verification of asynchronous circuits. The major contribution of proposition-oriented behaviours is their ability to extend existing formal notations to permit the explicit use of both signal levels and transitions. This thesis begins with the formalisation of proposition-oriented behaviours in the context of gate networks, and with the set-theoretic extension of both regular-expressions and trace-expressions to reason over proposition-oriented behaviours. A new trace-expression construct, referred to as biased composition, is also introduced. Algorithmic realisation of these set-theoretic extensions is documented using a special form of finite automata called proposition automata. A verification procedure for conformance of gate networks to a set of proposition automata is described in which each proposition automaton may be viewed either as a constraint or a specification. The implementation of this procedure as an automated verification program called Veraci is summarised, and a number of example Veraci programs are used to demonstrate contributions of proposition-oriented behaviour to asynchronous circuit design. These contributions include level-event unification, event abstraction, and relative timing assumptions using biased composition. The performance of Veraci is also compared to an existing event-oriented verification program called Versify, the result of this comparison being a consistent performance gain using Veraci over Versify. This thesis concludes with the design and implementation of a 2048 bit dual-rail asynchronous Montgomery exponentiator, MOD_EXP, in a 0.18μm standard-cell process. The application of Veraci to the design of MOD_EXP is summarised, and the practical benefits of proposition-oriented verification are discussed.
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Wilcox, Stephen Paul. "Synthesis of asynchronous circuits." Thesis, University of Cambridge, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.624217.
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Bednarczyk, M. A. "Categories of asynchronous systems." Thesis, University of Sussex, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381623.
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Fawaz, Khodor Ahmad. "Dynamically reconfigurable asynchronous processor." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/9442.
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The main design requirements for today's mobile applications are: · high throughput performance. · high energy efficiency. · high programmability. Until now, the choice of platform has often been limited to Application-Specific Integrated Circuits (ASICs), due to their best-of-breed performance and power consumption. The economies of scale possible with these high-volume markets have traditionally been able to hide the high Non-Recurring Engineering (NRE) costs required for designing and fabricating new ASICs. However, with the NREs and design time escalating with each generation of mobile applications, this practice may be reaching its limit. Designers today are looking at programmable solutions, so that they can respond more rapidly to changes in the market and spread costs over several generations of mobile applications. However, there have been few feasible alternatives to ASICs: Digital Signals Processors (DSPs) and microprocessors cannot meet the throughput requirements, whereas Field-Programmable Gate Arrays (FPGAs) require too much area and power. Coarse-grained dynamically reconfigurable architectures offer better solutions for high throughput applications, when power and area considerations are taken into account. One promising example is the Reconfigurable Instruction Cell Array (RICA). RICA consists of an array of cells with an interconnect that can be dynamically reconfigured on every cycle. This allows quite complex datapaths to be rendered onto the fabric and executed in a single configuration - making these architectures particularly suitable to stream processing. Furthermore, RICA can be programmed from C, making it a good fit with existing design methodologies. However the RICA architecture has a drawback: poor scalability in terms of area and power. As the core gets bigger, the number of sequential elements in the array must be increased significantly to maintain the ability to achieve high throughputs through pipelining. As a result, a larger clock tree is required to synchronise the increased number of sequential elements. The clock tree therefore takes up a larger percentage of the area and power consumption of the core. This thesis presents a novel Dynamically Reconfigurable Asynchronous Processor (DRAP), aimed at high-throughput mobile applications. DRAP is based on the RICA architecture, but uses asynchronous design techniques - methods of designing digital systems without clocks. The absence of a global clock signal makes DRAP more scalable in terms of power and area overhead than its synchronous counterpart. The DRAP architecture maintains most of the benefits of custom asynchronous design, whilst also providing programmability via conventional high-level languages. Results show that the DRAP processor delivers considerably lower power consumption when compared to a market-leading Very Long Instruction Word (VLIW) processor and a low-power ARM processor. For example, DRAP resulted in a reduction in power consumption of 20 times compared to the ARM7 processor, and 29 times compared to the TIC64x VLIW, when running the same benchmark capped to the same throughput and for the same process technology (0.13μm). When compared to an equivalent RICA design, DRAP was up to 22% larger than RICA but resulted in a power reduction of up to 1.9 times. It was also capable of achieving up to 2.8 times higher throughputs than RICA for the same benchmarks.
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Shankaran, Rajan. "Asynchronous transfer mode security." Thesis, View thesis, 1999. http://handle.uws.edu.au:8081/1959.7/252.
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There is a growing interest in the development of broadband services and networks for commercial use in both local area and wide area networks. The primary reasons for this is a pressing need to meet the demand for increased bandwidth for remote sites interconnection, and in high speed data transfer of bulk data such as images etc. There has also been a significant change in the characteristics of network traffic. It is increasingly taking the form of bursty traffic characterized by an unpredictable demand for bandwidth of several megabytes. A new generation of networking technologies have emerged to meet the demand of growing and uncertain bandwidth requirements. One such technology is called Asynchronous Transfer Mode (ATM) for use on broadband networks under the banner of broadband ISDN. ATM enables interconnection at high speeds in the range of Mbit/s or Gbit/s over wide areas, which effectively moves the bottleneck from networks to end systems. Furthermore, the user is able to access bandwidth on demand and the user is only charged for the bandwidth actually used. As more and more information (audio, image and data) is transferred over ATM networks, security issues are becoming increasingly critical. The rapidly growing use of the Internet to transfer confidential and sensitive information only enhances the importance of security services. One may even argue that the success of ATM will be determined not by its cost effectiveness but also to the level of trust that can be placed on its performance, security and availability. The objective of this dissertation is to address the issues involved in the design of security services for ATM networks.
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Shankaran, Rajan. "Asynchronous transfer mode security /." View thesis, 1999. http://library.uws.edu.au/adt-NUWS/public/adt-NUWS20030616.142410/index.html.
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Thesis (M. Sc.) (Hons.) -- University of Western Sydney, Nepean, 1999.Thesis submitted in fulfilment of the requirements for the award of the degree Master of Science (Honors) from the University of Western Sydney, Nepean, School of Computing and Information Technology. Bibliography : p. 87-88.
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Brockington, Mark Gordon. "Asynchronous parallel game-tree search." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ29023.pdf.
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Ahmed, Jamil. "Asynchronous design in dynamic CMOS." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0011/MQ34126.pdf.
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Berks, Robert. "Performance analysis of asynchronous networks." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ32813.pdf.
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Chatall, Kim, and Niklas Johansson. "An Analysis of Asynchronous Data." Thesis, KTH, Matematisk statistik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-122307.
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Risk analysis and financial decision making requires true and appropriate estimates of correlations today and how they are expected to evolve in the future. If a portfolio consists of assets traded in markets with different trading hours, there could potentially occur an underestimation of the right correlation. This is due the asynchronous data - there exist an asynchronicity within the assets time series in the portfolio. The purpose of this paper is twofold. First, we suggest a modified synchronization model of Burns, Engle and Mezrich (1998) which replaces the first-order vector moving average with an first-order vector autoregressive process. Second, we study the time-varying dynamics along with forecasting the conditional variance-covariance and correlation through a DCC model. The performance of the DCC model is compared to the industrial standard RiskMetrics Exponentially Weighted Moving Averages (EWMA) model. The analysis shows that the covariance of the DCC model is slightly lower than of the RiskmMetrics EWMA model. Our conclusion is that the DCC model is simple and powerful and therefore a promising tool. It provides good insight into how correlations are likely to evolve in the short-run time horizon.När man mäter risk och vid finansiellt beslutfattande är det viktigt att det finns skattningar på dagens korrelation samt dess förväntade utveckling. Om en portfölj består av tillgångar som handlas på olika finansiella marknader finns det risk att korrelationen är underskattad. Detta beror på att det existerar en assynkronitet mellan tidsserierna i portföljen, det vill säga att dem handlas under olika tider på dygnet. Syftet med denna uppsats är tvåfaldig. Först anges en modifierad synkroniseringsmodell som antar en AR(1) process istället för en MA(1) som föreslogs av Burns, Engle och Mezrich (1998). Sedan studerar vi den dagliga betingande korrelations- samt varians-kovariansmatrisen med hjälp av en DCC modell. Utförandet av DCC modellen jämförs sedan med RiskMetrics EMWA. Analysen visar i ett konkret exempel att varians-kovariansmatrisen för DCC modellen är längre än för RiskMetrics EMWA modellen. Vår slutsats är att DCC modellen ger sken av att vara ett enkelt och kraftfullt verktyg för att mäta och få en god inblick i hur korrelationer sannolikt kommer att utvecklas på kort sikt.
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Joty, Shafiq Rayhan. "Discourse analysis of asynchronous conversations." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/45674.
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A well-written text is not merely a sequence of independent and isolated sentences, but instead a sequence of structured and related sentences. It addresses a particular topic, often covering multiple subtopics, and is organized in a coherent way that enables the reader to process the information. Discourse analysis seeks to uncover such underlying structures, which can support many applications including text summarization and information extraction.
This thesis focuses on building novel computational models of different discourse analysis tasks in asynchronous conversations; i.e., conversations where participants communicate with each other at different times (e.g., emails, blogs). Effective processing of these conversations can be of great strategic value for both organizations and individuals. We propose novel computational models for topic segmentation and labeling, rhetorical parsing and dialog act recognition in asynchronous conversation. Our approaches rely on two related computational methodologies: graph theory and probabilistic graphical models.
The topic segmentation and labeling models find the high-level discourse structure; i.e., the global topical structure of an asynchronous conversation. Our graph-based approach extends state-of-the-art methods by integrating a fine-grained conversational structure with other conversational features.
On the other hand, the rhetorical parser captures the coherence structure, a finer discourse structure, by identifying coherence relations between the discourse units within each comment of the conversation. Our parser applies an optimal parsing algorithm to probabilities inferred from a discriminative graphical model which allows us to represent the structure and the label of a discourse tree constituent jointly, and to capture the sequential and hierarchical dependencies between the constituents.
Finally, the dialog act model allows us to uncover the underlying dialog structure of the conversation. We present unsupervised probabilistic graphical models that capture the sequential dependencies between the acts, and show how these models can be trained more effectively based on the fine-grained conversational structure.
Together, these structures provide a deep understanding of an asynchronous conversation that can be exploited in the above-mentioned applications. For each discourse processing task, we evaluate our approach on different datasets, and show that our models consistently outperform the state-of-the-art by a wide margin. Often our results are highly correlated with human annotations.
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Lloyd, David W. "Design methods for asynchronous circuits." Thesis, University of Nottingham, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282817.
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Elston, Corrie John. "Hades - an asynchronous superscalar processor." Thesis, University of Hertfordshire, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.361188.
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Rose, Kyle R. (Kyle Robert) 1976. "Asynchronous generic key/value database." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86633.
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Price, Michael Ph D. (Michael R. ). Massachusetts Institute of Technology. "Asynchronous data-dependent jitter compensation." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52771.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 95-96).
Data-dependent jitter (DDJ) caused by lossy channels is a limiting factor in the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture for DDJ compensation. The compensation circuit alters the transition times of a digital signal to cancel the expected channel-induced delays. It is designed for a 0.35 [mu]m BiCMOS process with a 240 x 140 ¹m footprint and typically consumes 3.4 mA, a small fraction of the current used in a typical transmitter. Extensive simulations demonstrate that the circuit has the potential to reduce channel-induced DDJ by at least 50% at bit rates of 6.25 Gb/s and 10 Gb/s.
by Michael Price.
M.Eng.
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Yoneki, Eiko. "ECCO : data centric asynchronous communication." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612757.
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Sotiriou, Christos Panagiotis. "Design of an asynchronous processor." Thesis, University of Edinburgh, 2001. http://hdl.handle.net/1842/14458.
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This thesis investigates the implementation of asynchronous circuits and asynchronous computer architectures. In the area of asynchronous circuits, it proposes the direct-mapped approach to control circuit design, originally devised by Hollaar, mapped to CMOS technology. In the area of asynchronous computer architecture, it investigates scalable, concurrent computer architectures, with the aim of solving the problems of scaling performance and utilising the increasing device count. The design and implementation of two hardware structures, Shared Register Files and mnet (micronet) architectures is detailed, together with their incorporation into the design of an asynchonous prototype processor, the A1 chip. The Shared Register File approach provides a scalable and segmented datapath by partitioning the conventional monolithic register file into multiple register files which physically share registers. Communication and synchronisation between the shared register files takes place via the shared register. This approach can be used to implement a clustered uniprocessor or a single-chip multiprocessor system. The shared register file approach allows for the exploitation of program level concurrency, where different parts of the same program or different programs can run on the different shared register file datapaths. The design and implementation of shared register files is presented. The mnet approach is a methodology for asynchronous processor design, which allows fine-grain instruction level parallelism to be exploited. It implements a processor architecture as a non-linear pipeline with inputs at every pipeline stage. In this way, a mnet architecture exploits more fine-grain parallelism than a conventional pipelined architecture. The design and implementation of generic, scalable mnet architecture is described and evaluated.
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Li, Yixin. "Asynchronous two-way relay networks." Thesis, University of Reading, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.658033.
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This thesis summarises the work during the four year Ph.D. study at the University of Reading. It focused on the design for emerging two-way relay network (TWRN) strategies respecting various practical and theoretical conditions. Our work concerns four main topics. The first topic is the synchronisation for time-domain (TD) based physical-layer network coding (PLNC) with timing asynchrony under Rayleigh block-flat-fading channels. In such a system, it is essential to estimate the channel coefficients at the relay to perform PLNC mapping and detection. We have proposed a training-sequence-based delay and channel estimation algorithm and presented a low-complexity estimation design based on Alamouticode structure. Among our findings, we revealed that as long as the signals arrives at the relay with symbol alignment and the relative delay information is sent to the destination nodes, timing asynchrony does not affect the system performance. The second topic targets the interference mitigation schemes in practical PLNC systems. In TD-based PLNC systems, signals may arrive at the relay with fractional symbol delay which introduces inter-symbol interference (ISI) Orthogonal frequency-division multiplexing (OFDM) can be combined with PLNC to combat the timing mismatch, however on the other hand it is sensitive to carrier frequency offset which introduces inter-carrier interference (ICI). In these systems, ISI and ICI need to be carefully handled, otherwise it will cause serious performance degradation. The thesis has looked into both cancellation and mitigation in PLNC systems and novel schemes were proposed accordingly. For TD-PLNC systems, the first scheme is a multi-dimensional transmission scheme through pre-coding. lSI can be fully avoided through separate decoding. The second scheme is an iterationbased algorithm, which enables the relay to reconstruct and eliminate the interference to achieve better performance with reduced complexity compared to other existing schemes. The second method is also extended to OFDM-based PLNC systems to mitigate the ICI. The third topic is concentrated on limited feedback (LFB) power control in PLNC, which has been rarely mentioned in the literature. We have proposed a feedback ratio design based on the characteristics of the channels, where each feedback ratio covers a ratio range of equal probability in cumulative distribution function of the ratio between two channels' power gains. The effectiveness of the proposed scheme shows that the proposed LFB power control scheme with 3 bits can approach optimal power control scheme. The last topic examines the relay selection and dynamic power allocation in analogue network coding CANe) system. Three novel power allocation schemes are proposed, which show significantly performance improvement and provide a tradeoff between computational complexity and performance.
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Mathew, Ajit. "Multicore Scalability Through Asynchronous Work." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/104116.
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With the end of Moore's Law, computer architects have turned to multicore architecture to provide high performance. Unfortunately, to achieve higher performance, multicores require programs to be parallelized which is an untamed problem. Amdahl's law tells that the maximum theoretical speedup of a program is dictated by the size of the non-parallelizable section of a program. Hence to achieve higher performance, programmers need to reduce the size of sequential code in the program. This thesis explores asynchronous work as a means to reduce sequential portions of program. Using asynchronous work, a programmer can remove tasks which do not affect data consistency from the critical path and can be performed using background thread. Using this idea, the thesis introduces two systems. First, a synchronization mechanism, Multi-Version Read-Log-Update(MV-RLU), which extends Read-Log-Update (RLU) through multi-versioning. At the core of MV-RLU design is a concurrent garbage collection algorithm which reclaims obsolete versions asynchronously reducing blocking of threads. Second, a concurrent and highly scalable index-structure called Hydralist for multi-core. The key idea behind design of Hydralist is that an index-structure can be divided into two component (search layer and data layer) and updates to data layer can be done synchronously
while updates to search layer can be propagated asynchronously using background threads.Master of Science
Up until mid-2000s, Moore's law predicted that performance CPU doubled every two years. This is because improvement in transistor technology allowed smaller transistor which can switch at higher frequency leading to faster CPU clocks. But faster clock leads to higher heat dissipation and as chips reached their thermal limits, computer architects could no longer increase clock speeds. Hence they moved to multicore architecture, wherein a single die contains multiple CPUs, to allow higher performance. Now programmers are required to parallelize their code to take advangtage of all the CPUs in a chip which is a non trivial problem. The theoretical speedup achieved by a program on multicore architecture is dictated by Amdahl's law which describes the non parallelizable code in a program as the limiting factor for speedup. For example, a program with 99% parallelizable code can achieve speedup of 20 whereas a program with 50% parallelizable code can only achieve speedup of 2. Therefore to achieve high speedup, programmers need to reduce size of serial section in their program. One way to reduce sequential section in a program is to remove non-critical task from the sequential section and perform the tasks asynchronously using background thread. This thesis explores this technique in two systems. First, a synchronization mechanism which is used co-ordinate access to shared resource called Multi-Version Read-Log-Update (MV-RLU). MV-RLU achieves high performance by removing garbage collection from critical path and performing it asynchronously using background thread. Second, an index structure, Hydralist, which based on the insight that an index structure can be decomposed into two components, search layer and data layer, and decouples updates to both the layer which allows higher performance. Updates to search layer is done synchronously while updates to data layer is done asynchronously using background threads. Evaluation shows that both the systems perform better than state-of-the-art competitors in a variety of workloads.
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Amaro, Da Costa Luz Carneiro Joao Paulo. "Asynchronous event-based 3d vision." Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066593/document.
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L’implementation de la vision biologique sur machine est un problème majeur que la recherche actuelle a à peine effleuré la surface. Les organismes vivants sont capables de réaliser des tâches visuelles très complexes et de manière très efficace. La stéréovision fait partie de ces mécanismes complexes que les sci- entifiques tentent de reproduire à l’aide de caméras à haute résolution. Cette thèse aborde le problème de la stéréovision d’une manière neuromorphique par l’intermédiaire d’une nouvelle génération de capteurs de vision appelés ”rétines de silicium”. Ces rétines de silicium imitent les rétines biologiques en capturant l’information visuelle sous forme de flux asynchrones d’événements codant les changements de contraste avec une grande précision temporelle. Ces capteurs sont utilisés pour étudier l’importance de la précision et de la dynamiquetemporelledelascènedansleproblèmedemiseencorrespondance stéréo. Nous proposons une des premières méthodes de reconstruction 3D capable de produire des modèles 3D d’une manière totalement asynchrone, á partir de l’information visuelle. Cette approche, outre son originalité, permet également de préserver la dynamique native de la scène. Cette thèse montre que le temps en tant que medium d’information, joue un rôle primordial dans la stéréovision. Le temps peut compléter, compenser, voire remplacer l’information apportée habituellement par la luminance et la géométrie. Ce travail établit également les fondations solides des futures recherches en vision stéréo á haute vitesse et haute dynamique, basée sur les événements. Il ouvre également de nouvelles perspectives prometteuses pour la résolution de problèmes traditionels de vision artificielle grâce à l’apport du nouveau paradigme de la vision asynchroneReproducing biological vision in a machine is a challenging problem for which scientists have just scratched the surface. Living organisms are able to per- form complex tasks in an awestruckly efficient manner. The stereovision is one of these complex mechanisms that computer scientists try to replicate with high resolution cameras. This thesis takes on the stereovision problem in a neuromorphic way by mean of a new generation of vision sensors also called ”silicon retinas”. These silicon retinas mimic biological retinas by cap- turing the visual information into the form of asynchronous stream of events that encode contrast change at high temporal precision. These sensors are used to study the importance of the precise timing and the scene temporal dynamics in solving the stereo correspondence problem. We propose one of the first 3D reconstruction methods which is able to produce 3Dmodelsinatrulyevent-basedandasynchronousmanner, fromevent-based visual information. Besides the novelty of proposing a truly temporal- based asynchronous event-driven approach of 3D reconstructions, this work is also able to preserve the native dynamic of the scene. Time as information medium is proven to have a critical role in stereovision. Time can supplement, compensate and even replace the usual luminance and spatial information. This work lays strong foundations for future research on high temporal and event-based dynamic stereo vision. It also opens new promisingperspectivesforsolvingtraditionalmachinevisionproblemsthanks to the use of the new asynchronous vision paradigm
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Donaldson, Val. "Asynchronous pipeline analysis and scheduling /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1997. http://wwwlib.umi.com/cr/ucsd/fullcit?p9804026.
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Weld, Henry. "On categories of asynchronous circuits." Thesis, The University of Sydney, 1998. https://hdl.handle.net/2123/27575.
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Two categorical models of asynchronous circuits are presented. The first uses the bicategory of spans of graphs to model particular finite, nondeterministic, asynchronous binary circuits in which state is held in special delay components
and computation by all other circuit components is instantaneous. Behaviour is a sequence of changes of 'total state. This model is closely related to the asynchronous binary circuits of Brzozowski and Seger and comparison to the
behavioural analysis of their model is made.
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Webb, Robert L. "ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/381.
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The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.
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Corfman, Timothy D. "Creativity in Asynchronous Online Discussions." ScholarWorks, 2017. https://scholarworks.waldenu.edu/dissertations/4209.
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It is vital for online educators to know whether the strategies they use help students gain 21st-century skills. One skill that has been identified as important in the 21st century is creativity; however, a gap existed in the literature concerning whether online courses could help students to develop creativity. Thus, the purpose of this study was to determine whether participation in online courses can help students develop creativity using asynchronous online discussions, textbooks, and teacher developed materials. Amabile's componential model of creativity formed the study's conceptual framework. A case-study approach was used to examine the question of whether asynchronous online discussions and other materials used in online courses could help students develop creativity. One professor, recognized by her peers for her expertise in online education, and three of her online graduate students who volunteered for the study, were interviewed using Zoom. Twenty-nine transcripts of asynchronous online discussions were analyzed using a sequential process of building an explanation, checking the explanation against the data, and repeating the process. Key results from the study indicated that project-based prompts, problem-based prompts, and heuristics used in asynchronous online discussions can help promote creativity. Recommendations for future research include conducting a similar case study with a more diverse group of participants and with a course in a different specialty. These findings may promote social change by helping online instructors use appropriate prompts for asynchronous online discussions that will help students refine their creative skills to ultimately use them in the 21st-century workplace.
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Leblond, Rémi. "Asynchronous optimization for machine learning." Thesis, Paris Sciences et Lettres (ComUE), 2018. http://www.theses.fr/2018PSLEE057/document.
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Les explosions combinées de la puissance computationnelle et de la quantité de données disponibles ont fait des algorithmes les nouveaux facteurs limitants en machine learning. L’objectif de cette thèse est donc d’introduire de nouvelles méthodes capables de tirer profit de quantités de données et de ressources computationnelles importantes. Nous présentons deux contributions indépendantes. Premièrement, nous développons des algorithmes d’optimisation rapides, adaptés aux avancées en architecture de calcul parallèle pour traiter des quantités massives de données. Nous introduisons un cadre d’analyse pour les algorithmes parallèles asynchrones, qui nous permet de faire des preuves correctes et simples. Nous démontrons son utilité en analysant les propriétés de convergence et d’accélération de deux nouveaux algorithmes. Asaga est une variante parallèle asynchrone et parcimonieuse de Saga, un algorithme à variance réduite qui a un taux de convergence linéaire rapide dans le cas d’un objectif lisse et fortement convexe. Dans les conditions adéquates, Asaga est linéairement plus rapide que Saga, même en l’absence de parcimonie. ProxAsaga est une extension d’Asaga au cas plus général où le terme de régularisation n’est pas lisse. ProxAsaga obtient aussi une accélération linéaire. Nous avons réalisé des expériences approfondies pour comparer nos algorithms à l’état de l’art. Deuxièmement, nous présentons de nouvelles méthodes adaptées à la prédiction structurée. Nous nous concentrons sur les réseaux de neurones récurrents (RNNs), dont l’algorithme d’entraînement traditionnel – basé sur le principe du maximum de vraisemblance (MLE) – présente plusieurs limitations. La fonction de coût associée ignore l’information contenue dans les métriques structurées ; de plus, elle entraîne des divergences entre l’entraînement et la prédiction. Nous proposons donc SeaRNN, un nouvel algorithme d’entraînement des RNNs inspiré de l’approche dite “learning to search”. SeaRNN repose sur une exploration de l’espace d’états pour définir des fonctions de coût globales-locales, plus proches de la métrique d’évaluation que l’objectif MLE. Les modèles entraînés avec SeaRNN ont de meilleures performances que ceux appris via MLE pour trois tâches difficiles, dont la traduction automatique. Enfin, nous étudions le comportement de ces modèles et effectuons une comparaison détaillée de notre nouvelle approche aux travaux de recherche connexesThe impressive breakthroughs of the last two decades in the field of machine learning can be in large part attributed to the explosion of computing power and available data. These two limiting factors have been replaced by a new bottleneck: algorithms. The focus of this thesis is thus on introducing novel methods that can take advantage of high data quantity and computing power. We present two independent contributions. First, we develop and analyze novel fast optimization algorithms which take advantage of the advances in parallel computing architecture and can handle vast amounts of data. We introduce a new framework of analysis for asynchronous parallel incremental algorithms, which enable correct and simple proofs. We then demonstrate its usefulness by performing the convergence analysis for several methods, including two novel algorithms. Asaga is a sparse asynchronous parallel variant of the variance-reduced algorithm Saga which enjoys fast linear convergence rates on smooth and strongly convex objectives. We prove that it can be linearly faster than its sequential counterpart, even without sparsity assumptions. ProxAsaga is an extension of Asaga to the more general setting where the regularizer can be non-smooth. We prove that it can also achieve a linear speedup. We provide extensive experiments comparing our new algorithms to the current state-of-art. Second, we introduce new methods for complex structured prediction tasks. We focus on recurrent neural networks (RNNs), whose traditional training algorithm for RNNs – based on maximum likelihood estimation (MLE) – suffers from several issues. The associated surrogate training loss notably ignores the information contained in structured losses and introduces discrepancies between train and test times that may hurt performance. To alleviate these problems, we propose SeaRNN, a novel training algorithm for RNNs inspired by the “learning to search” approach to structured prediction. SeaRNN leverages test-alike search space exploration to introduce global-local losses that are closer to the test error than the MLE objective. We demonstrate improved performance over MLE on three challenging tasks, and provide several subsampling strategies to enable SeaRNN to scale to large-scale tasks, such as machine translation. Finally, after contrasting the behavior of SeaRNN models to MLE models, we conduct an in-depth comparison of our new approach to the related work
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Laveau, Marie. "Asynchronous Self-Stabilizing Stable Marriage." Electronic Thesis or Diss., université Paris-Saclay, 2020. http://www.theses.fr/2020UPASG008.
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Le Problème du Mariage Stable (SMP) est un problème d'appariement où les participants ont des préférences à propos de leurs partenaires potentiels.L'objectif est de trouver un appariement optimal (stable dans un sens) au regard des préférences. Ce type d'appariement a de très nombreuses applications comme les affectations d'étudiants à des universités (APB ou ParcourSup), celles des internes en médecine aux hôpitaux, les choix des donneurs pour les patients en attente d'organe, la mise en rapport des taxis et de leurs clients ou encore la diffusion de contenu sur Internet.Certaines de ces applications peuvent être traitées de manière centralisée tandis que d'autres, de par leur nature distribuée et la complexité de leurs données, nécessitent un traitement différent. Par exemple, dans le contexte du Cloud-Computing, des machines virtuelles sont émulées par des machines réelles situées sur la terre entière.Un algorithme centralisé causerait des délais considérables dans les prises de décision tout en étant sensible aux défaillances, ce qui est inconcevable pour un service supposé disponible à tout moment. D'un autre côté, chaque fois que des personnes sont impliquées dans un appariement, elles ont le droit de garder privées leurs données personnelles et en particulier leur liste de préférences, qui peut contenir des informations sensibles.Par conséquent, il est souhaitable que les listes de préférence des personnes ne soient jamais transmises sur Internet, et encore moins rassemblées pour un traitement centralisé.C'est pourquoi la distribution, la tolérance aux défaillances (par auto-stabilisation) et la confidentialité sont les trois principaux mots-clés de cette thèse.Dans ce contexte, nous proposons deux solutions distribuées auto-stabilisantes. De telles solutions tolèrent les défaillances (e.g., corruptions de mémoire ou de messages) transitoires (ou de courte durée) de n'importe quels noeuds.La confidentialité des listes de préférences est garantie par les deux algorithmes que nous proposons : les listes ne sont pas partagées et seules des queries binaires et leurs réponses sont échangés.Une différence entre ces algorithmes est le modèle de communication : le premier algorithme utilise le modèle à état tandis que le second algorithme utilise le modèle à registre plus général.Dans les deux modèles, les exécutions se déroulent par pas atomiques et un démon (démon distribué inéquitable) exprime la notion d'asynchronisme.Avec ce démon, le temps de stabilisation peut être borné en terme de moves (pas locaux).Cette mesure de complexité permet d'évaluer avec précision la puissance de calcul nécessaire ou l'énergie dissipée par les exécutions de l'algorithme.Ce n'est pas le cas quand la complexité est évaluée en rounds, puisque le nombre de moves effectués dans un round n'est pas nécessairement borné.Le premier algorithme, basé sur la méthode centralisée de Ackermann et al. (SICOMP' 2011), résout le SMP en O(n⁴) moves.Il permet également de résoudre certaines variantes du SMP telles que le mariage stable avec indifférence, avec partenaires inacceptables, etc.Le point de départ du deuxième algorithme est le schéma de détection locale/correction globale de Awerbuch et al. (DA' 1994) : un algorithme non auto-stabilisant (devant être initialisé) mais avec la propriété d'être vérifiable localement peut être combiné avec un détecteur et un algorithme de réinitialisation.De cette combinaison résulte un algorithme auto-stabilisant.Malheureusement, la définition de la vérifiabilité locale de DA '1994 ne s'applique pas à notre cas (en particulier en raison du démon inéquitable).Nous proposons donc une nouvelle définition.De plus, nous concevons un algorithme de réinitialisation (reset) asynchrone, distribué et auto-stabilisant.L'algorithme résultant résout le SMP en θ(n)² movesThe Stable Marriage Problem (SMP) is a matching problem where participants have preferences over their potential partners.The objective is to find a matching that is optimal (stable in certain sens) with regard to these preferences.This type of matching has a lot of widely used applications such as the assignment of children to schools, interns to hospitals, kidney transplant patients to donors, as well as taxi scheduling or content delivery on the Internet.Some applications can be solved in a centralized way while others, due to their distributed nature and their complex data, need a different treatment.For example, when applying this problem to the Cloud-Computing context, virtual machines are emulated by real machines located all over the world.A centralized algorithm would cause unbearable delays and be sensible to failures, which is inconceivable for a service meant to be available at any time.On the other hand, when humans are to be matched or involved in a matching, they have the right to keep their personal data private and in particular their list of preferences.Consequently, the preference lists should not be transmitted on the Internet, and even less gathered for a centralized treatment.This is why, distribution, fault-tolerance (by self-stabilization) and privacy are the three main keywords of this thesis.In order to handle these challenges, we provide two distributed self-stabilizing solutions.Such solutions tolerate transient (or short-lived) failures (e.g., memory or message corruptions) of any nodes.The privacy of the preference lists is guaranteed by the two proposed algorithms: lists are not shared, only some binary queries and responses are transmitted.One of the differences between the two algorithms is the communication model: the first algorithm uses the state model while the second algorithm uses the more general register model.In both models, executions proceed in atomic steps and a daemon (distributed unfair daemon) conveys the notion of asynchrony.Under this daemon, the stabilization time can be bounded in term of moves (local computations).This complexity metrics allows to evaluate the necessary computational power or the energy consumption of the algorithm's executions.This is not the case when the stabilization time is measured in rounds since an unbounded number of moves may be executed during a round.The first algorithm, based on the centralized method of Ackermann et al. (SICOMP' 2011), solves the problem in O(n⁴) moves.It also solves some variants of SMP such as the Stable Marriage with indifference, with unacceptable partners, etc.The starting point of the second algorithm is the local detection/global correction scheme of Awerbuch et al. (DA' 1994): a non-self-stabilizing algorithm (with initialization) that satisfies the property of local checkability can be combined with a detector and a reset algorithms.The result of this composition is a self-stabilizing version of the given algorithm.Unfortunately, local checkability definition of DA '1994 does not apply to our case (in particular due to the unfair daemon).Consequently, we propose a new definition.Furthermore, we design a distributed self-stabilizing asynchronous reset algorithm. Using it, the resulting composed algorithm solves SMP in θ(n)² moves in a self-stabilizing way
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Gallaba, Keheliya. "Characterizing and refactoring asynchronous JavaScript callbacks." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/56290.
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Modern web applications make extensive use of JavaScript, which is now estimated to be one of the most widely used languages in the world. Callbacks are a popular language feature in JavaScript. However, they are also a source of comprehension and maintainability issues. We studied several features of callback usage across a large number of JavaScript applications and found out that over 43 of all callback-accepting function call sites are anonymous, the majority of callbacks are nested, and more than half of all callbacks are invoked asynchronously. Promises have been introduced as an alternative to callbacks for composing complex asynchronous execution flow and as a robust mechanism for error checking in JavaScript. We use our observations of callback usage to build a developer tool that refactors asynchronous callbacks into Promises. We show that our technique and tool is broadly applicable to a wide range of JavaScript applications.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Schrader, U. "Convergence of Asynchronous Jacobi-Newton-Iterations." Universitätsbibliothek Chemnitz, 1998. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-199801324.
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Asynchronous iterations often converge under different conditions than their syn- chronous counterparts. In this paper we will study the global convergence of Jacobi- Newton-like methods for nonlinear equationsF x = 0. It is a known fact, that the synchronous algorithm converges monotonically, ifF is a convex M-function and the starting valuesx0 andy0 meet the conditionF x04 04F y0 . In the paper it will be shown, which modifications are necessary to guarantee a similar convergence behavior for an asynchronous computation.
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Yuan, Chengan. "Preference in Asynchronous Presentation of Stimuli." The University of Waikato, 2009. http://hdl.handle.net/10289/2795.
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A self-control procedure that involved a later onset of a stimulus signalling a small reinforcer within the waiting time for a larger reinforcer was investigated to determine a point of shifting preference and a discounting function as the delay varied. The results from Experiment 1 to Experiment 3 showed exclusive impulsive choices regardless of the delay. In order to examine if the results were due to the procedure and the parameters, or the species used, Experiment 4 attempted to obtain shifts in preference using simultaneous onset of stimuli with the same species. The results demonstrated no changes in preference but an increase in proportion of self-control choices was shown. Due to the limited information from the replicated studies, the accounts for the results could not be concluded. The explanations derived from choice models seemed most plausible, but limitations of the choice models were discussed.
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Benko, Igor. "ECF processes and asynchronous circuit design." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0003/NQ44753.pdf.
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Gong, Dah-Chuan. "A metalmodel of asynchronous material transport." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/32868.
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Saadallah, Nisrine. "High-speed low-power asynchronous circuits." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.
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This thesis presents several design experiments for high-performance power-efficient asynchronous circuits.In Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.
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Zhu, Junren 1965. "The design of asynchronous learning environment /." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=31565.
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Asynchronous Learning Environment (ALE) has the capability of providing learning to people anywhere and at any time for both to secure degree and to engage in continuing education throughout their lifetimes. The advance of communications and information technology will make students choose to purchase and enroll in open market, widely available networked courses regardless of institutional affiliation.Research results have found that success factors for asynchronous learning include whether students felt part of the online learning group, immediate feedback from instructors, automatic self-test, and indicating student's performance and progress in the course. These findings present basic requirement for the design of ALE. This paper explores all aspects of Asynchronous Learning Environment, including the architecture of ALE and complete database design. The modules of ALE include multimedia presentation, identity verification, intelligent agent, automatic test marking, computer conference, chat & whiteboard, and learning scheduling assistance. The purpose of this research is to make ALE a better way of education than traditional education. A database is designed to fully support these ALE functions.
Guidelines of designing ALE are provided with implementation examples of intelligent agents that providing automatic reminders and learning progress report. Conclusion and further works are discussed at the end of the paper.
The design described in this paper is intended for use by engineering courses. But it can be used by courses of other disciplines without much modification.
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Beringer, Lennart. "Asynchronous queue machines with explicit forwarding." Thesis, University of Edinburgh, 2002. http://hdl.handle.net/1842/370.
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We consider computational models motivated by processors which exhibit architectural asynchrony and allow operands to bypass the register bank using a forwarding mechanism. We analyse the interaction between asynchrony and forwarding, derive constraints on the usage of forwarding for various models of operation, and study consequences for compilers targeting such processors. Our approach to reasoning about processor behaviour is programming language based. We introduce an assembly language in which forwarding is explicitly visible. Operational models corresponding to processor abstractions are expressed as structural operational semantics for this language. The benefits of this approach for defining program execution and for relating processor models formally are demonstrated. Furthermore, we study the restrictions on the class of admissible programs for each operational model. Under our programming language perspective, these constraints are expressed as static semantics and formalised as type systems. Suitability of forwarding schemes for particular models of operation follows from soundness and completeness results which are established by standard programming language proof techniques. Well-typed programs are structurally correct and cannot experience run-time errors due to ill usage of the forwarding mechanism. Exposing asynchrony and forwarding to the programmer allows a compiler to optimise forwarding behaviour by scheduling operands. We show how program analysis can decide which values to communicate through registers and which ones to forward. The analysis is expressed as a dataflow problem for an intermediate language and is proven sound with respect to a dynamic semantics. Solutions to the dataflow equations yield translations into the assembly language which are functionally faithful to the operational semantics and also structure-preserving as resulting programs are well-typed. The theoretical development of the translation is complemented by a prototypical implementation. Experimental results are included for a symbolic conversion of Java virtual machine code into the intermediate language, indicating that application programs contain sufficient opportunities for forwarding to make our approach viable. In conclusion, we demonstrate the benefits of a programming language based view for reasoning about programs targeting architectures with asynchrony and forwarding.
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Johnston-Carey, Helen K. "Myogenesis Is Perturbed By Asynchronous Regeneration." Thesis, The George Washington University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3631374.
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Duchenne muscular dystrophy (DMD) is a recessive genetic disease resulting from mutation in the dystrophin gene that causes loss of the dystrophin protein, which is known to be found in muscle and brain tissue. In muscle, dystrophin is located in the dystrophin-glycoprotein complex (DGC), which has been shown to aid in force transduction across the sarcolemma (Turrina et al, 2013). DMD patients suffer from a progressive degeneration of muscles leading to loss of ambulation, and a shortened lifespan. Dystrophic muscle is characterized by cycles of degenerating fibers, fibrosis, increased fat deposition, split fibers, and hyaline fibers. Glucocorticoids (GC) are the most effective treatment of DMD, but these drugs only slow the progression of the disease and are known for their severe adverse effects. Skeletal muscle regeneration has been shown to be a spatio-temporally regulated process. Our laboratory has developed the theory that the cause for the failure of regeneration in dystrophic muscle is the result of inappropriate cross-talk between areas that are at different stages of regeneration. Furthermore, we hypothesize that glucocorticoids are effective due to their ability to resynchronize gene expression. In order to test our theory, we have developed a model of asynchronous regeneration in healthy muscle by creating cross-talk using multiple injuries with myotoxins. We found that placing injuries 10 days apart produced muscle histology with many of the features of dystrophic muscle. In the future, we can use this model to test the effectiveness of glucocorticoid treatment in resynchronization. As glucocorticoids are also an endogenous hormone, we sought to determine if their secretion was inherently altered in mdx mice. We found that mdx mice have a significantly dampened circadian endogenous glucocorticoid rhythm of secretion compared to wildtype mice. We also found that administering glucocorticoids in line with circadian rhythm of the endogenous hormone improves muscle histology. In the future, we could use more animals in a longer trial to determine if a chronotherapeutic approach to treatment of dystrophin-deficiency improves efficacy and decreases side effects of glucocorticoids. As dystrophin is expressed in regions of the brain responsible for glucocorticoid regulation, it is possible that lack of dystrophin is directly responsible for the change in endogenous glucocorticoid secretion. This is an important novel hypothesis that should be examined in the future.
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Lohith, Penmetsa Neela. "Monolithic 3D integration of asynchronous systems." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53113.
Full textAbstract:
The goal of this thesis is to study the impact of 3D integration on asynchronous circuits and explore the benefits in power, performance and area compared to traditional two dimensional integration. To enable this study we develop a fully automated asynchronous design methodology and 3D integration flows for asynchronous circuits. This study is also a first one to explore the mutual benefits of asynchronous circuits and 3D integration.
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Woodward, A. T. "The testing of asynchronous sequential machines." Thesis, Cardiff University, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.354749.
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