Dissertations / Theses on the topic 'ASIP'
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Šulek, Jakub. "Verifikace ASIP založena na formálních tvrzeních." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-264941.
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This thesis introduces the concept of assertion-based verifi cation of application-specifi c instruction set processors (ASIPs). The proposed design is implemented in SystemVerilog Assertions language as a part of veri fication environment created using Codasip Framework. The implemented concept is simulated in QuestaSim tool using model of Codix RISC processor. Main outcome of this thesis is the verifi cation concept usable not only on other processors, but as a part of system that automates the processor design as well.
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Karlsson, Andréas. "Design of Energy-Efficient High-Performance ASIP-DSP Platforms." Doctoral thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-130723.
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In the last ten years, limited clock frequency scaling and increasing power density has shifted IC design focus towards parallelism, heterogeneity and energy efficiency. Improving energy efficiency is by no means simple and it calls for a reevaluation of old design choices in processor architecture, and perhaps more importantly, development of new programming methodologies that exploit the features of modern architectures. This thesis discusses the design of energy-efficient digital signal processors with application-specific instructions sets, so-called ASIP-DSPs, and their programming tools. Target applications for such processors include, but are not limited to, communications, multimedia, image processing, intelligent vision and radar. These applications are often implemented by a limited set of kernel algorithms, whose performance and efficiency are critical to the application's success. At the same time, the extreme non-recurring engineering cost of system-on-chip designs means that product life-time must be kept as long as possible. Neither general-purpose processors nor non-programmable ASICs can meet both the flexibility and efficiency requirements, and ASIPs may instead be the best trade-off between all the conflicting goals. Traditional superscalar- and VLIW processor design focus has been to improve the throughput of fine-grained instructions, which results in high flexibility, but also high energy consumption. SIMD architectures, on the other hand, are often restricted by inefficient data access. The result is architectures which spend more energy and/or time on supporting operations rather than actual computing. This thesis defines the performance limit of an architecture with an N-way parallel datapath as consuming 2N elements of compute data per clock cycle. To approach this performance, this work proposes coarse-grained higher-order functional (HOF) instructions, which encode the most frequently executed compute-, data access- and control sequences into single many-cycle instructions, to reduce the overheads of instruction delivery, while at the same time maintaining orthogonality. The work further investigates opportunities for operation fusion to improve computing performance, and proposes a flexible memory subsystem for conflict-free parallel memory access with permutation and lookup-table-based addressing, to ensure that high computing throughput can be sustained even in the presence of irregular data access patterns. These concepts are extensively studied by implementing a large kernel algorithm library with typical DSP kernels, to prove their effectiveness and adequacy. Compared to contemporary VLIW DSP solutions, our solution can practically eliminate instruction fetching energy in many scenarios, significantly reduce control path switching, simplify the implementation of kernels and reduce code size, sometimes by as much as 30 times. The techniques proposed in this thesis have been implemented in the DSP platform ePUMA (embedded Parallel DSP processor with Unique Memory Access), a configurable control-compute heterogeneous platform with distributed memory, optimized for low-power predictable DSP computing. Hardware evaluation has been done with FPGA prototypes. In addition, several VLSI layouts have been created for energy and area estimations. This includes smaller designs, as well as a large design with 73 cores, capable of 1280 integer GOPS or 256 GFLOPS at 500MHz and which measures 45mm2 in 28nm FD-SOI technology. In addition to the hardware design, this thesis also discusses parallel programming flow for distributed memory architectures and ePUMA application implementation. A DSP kernel programming language and its compiler is presented. This effectively demonstrates how kernels written in a high-level language can be translated into HOF instructions for very high processing efficiency.
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Shahabuddin, S. (Shahriar). "MIMO detection and precoding architectures." Doctoral thesis, Oulun yliopisto, 2019. http://urn.fi/urn:isbn:9789526222837.
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Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability. The blessings of MIMO technologies for the baseband transceiver comes with the price of added complexity. Therefore, research on VLSI architectures for MIMO signal processing has generated a lot of interest over the past two decades. The advent of massive MIMO as a key technology for the fifth generation (5G) era also increased the interest in VLSI architectures related to MIMO communication research. In this thesis, we explored different VLSI architectures for MIMO detection and precoding algorithms. The detection and precoding are the most complex parts of a MIMO baseband transceiver. We focused on algorithm and architecture optimization and presented several VLSI architectures for MIMO detection and precoding. The thesis proposed an application specific instruction-set processor (ASIP) for a multimode small-scale MIMO detector. In a single design the detector supports minimum mean-square error (MMSE), selective spanning with fast enumeration (SSFE) and list sphere detection (LSD). In addition, a multiprocessor architecture is proposed in this thesis for a lattice reduction (LR) algorithm. A modified Lenstra-Lenstra-Lovasz (LLL) algorithm is proposed for LR to reduce the complexity of the original LLL algorithm. We also propose a massive MIMO detection algorithm based on alternating direction method of multipliers (ADMM). The algorithm is referred to as ADMM based infinity norm (ADMIN) constrained equalization. The ADMIN detection algorithm is implemented as an application-specific integrated circuit (ASIC) and for field programmable gate array (FPGA). A multimode precoder ASIP is also proposed in this thesis. In a single design, the ASIP supports norm-based scheduling, QR-decomposition, MMSE precoding and dirty paper coding (DPC) based precodingTiivistelmä Moni-tulo moni-lähtö (MIMO) -tekniikoita on sopeutettu kolmannen sukupolven (3G) langattomasta viestintästandardista alkaen spektritehokkuuden, tiedonsiirtonopeuden ja luotettavuuden parantamiseksi. MIMO-teknologioilla on useita hyviä puolia suhteessa peruskaistan vastaanottimeen, mutta samalla monimutkaisuus on lisääntynyt. VLSI-arkkitehtuurien tutkimus MIMO-signaalinkäsittelyssä on sen vuoksi herättänyt paljon kiinnostusta viimeisen kahden vuosikymmenen aikana. Myös MIMO:n saavuttama asema viidennen sukupolven (5G) viestintästandardin pääteknologiana on lisännyt kiinnostusta VLSI-arkkitehtuureihin MIMO-viestinnän tutkimuksessa. Tässä tutkielmassa on tutkittu erilaisia VLSI-arkkitehtuureja MIMO-signaalien tunnistus- ja esikoodausalgoritmeissa. Signaalien tunnistus ja esikoodaus ovat peruskaistaa käyttävän MIMO-vastaanottimen monimutkaisimmat osa-alueet. Tutkielmassa on keskitytty algoritmien ja arkkitehtuurien optimointiin ja esitetty useita VLSI-arkkitehtuureja MIMO-signaalien tunnistusta ja esikoodausta varten. Tutkielmassa on ehdotettu sovelluskohtaisen prosessorin (Application Specific Instruction-set Processor eli ASIP) käyttä pienen mittakaavan monimuotodetektorissa. Detektorin rakenne tukee samanaikaisesti keskineliöpoikkeaman minimointia (MMSE), SSFE (Selective Spanning with Fast Enumeration) -algoritmia ja LSD (List Sphere Detection) -algoritmia. Lisäksi tässä tutkielmassa ehdotetaan monisuoritinarkkitehtuuria hilan redusointialgoritmille (Lattice Reduction eli LR). LR-algoritmia varten ehdotetaan muokattua Lenstra-Lenstra-Lovasz (LLL) -algoritmia vähentämään alkuperäisen LLL-algoritmin monimutkaisuutta. Lisäksi MIMO-signaalien tunnistusalgoritmin perustaksi ehdotetaan vuorottelevaa kertoimien suuntaustapaa Alternating Direction Method of Multipliers eli ADMM). ADMM-perustaisesta taajuusvasteen rajoitetusta ääretön-normi-korjauksesta (infinity norm constrained equalization) käytetään nimitystä ADMIN-algoritmi. ADMIN-tunnistusalgoritmi toteutetaan sovelluskohtaisena integroituna piirinä (Application-Specific Integrated Circuit eli ASIC) ohjelmoitavaa porttimatriisia (Field Programmable Gate Array eli FPGA) varten. Lisäksi ehdotetaan ASIP-monimuotoesikooderin käyttöä. ASIP-esikooderin rakenne tukee normiperustaista aikataulutusta, QR-hajotelmaa, MMSE-esikoodausta ja likaisen paperin koodaukseen (Dirty Paper Coding eli DPC) perustuvaa esikoodausta
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Sydow, Thorsten von [Verfasser]. "Modellbildung und Analyse heterogener ASIP-eFPGA-Architekturen / Thorsten von Sydow." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2011. http://d-nb.info/1018226036/34.
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Murugappa, Velayuthan Purushotham. "Towards Optimized Flexible Multi-ASIP Architectures for LDPC/Turbo Decoding." Télécom Bretagne, 2012. http://www.telecom-bretagne.eu/publications/publication.php?idpublication=13220.
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De nombreuses techniques de codage de canal sont spécifiées dans les nouvelles normes de communications numériques, chacune adaptée à des besoins applicatifs spécifiques (taille de trame, type de canal de transmission, rapport signal-à-bruit, bande-passante, etc. ). Si l'on considère les applications naissantes multi-mode et multi-standard, ainsi que l'intérêt croissant pour la radio logicielle et la radio cognitive, la combinaison de plusieurs techniques de correction d'erreur devient incontournable. Néanmoins, des solutions optimales en termes de performance, de consommation d'énergie et de surface sont encore à inventer et ne doivent pas être négligées au profit de la flexibilité. Dans ce contexte, ce travail de thèse a exploré le modèle d'architecture multi-ASIP dans le but d¿unifier l'approche orientée sur la flexibilité et celle orientée sur l'optimalité dans la conception de décodeurs de canal flexibles. En considérant principalement les applications exigeantes de décodage itératif des turbocodes et des codes LDPC, des architectures multi-ASIP de décodeurs de canal sont proposées ciblant une grande flexibilité combinée à une haute efficacité architecturale en termes de bits/cycle/iteration/mm2. Différentes solutions architecturales et différentes approches de conception sont explorées pour proposer trois contributions originales. La première contribution concerne la conception d'un décodeur LDPC/Turbo multi-ASIP extensible, flexible et haut débit. Plusieurs objectifs de conception sont atteints en termes d'extensibilité, de partage de ressources, et de vitesse de configuration. Le décodeur proposé, nommé DecASIP, supporte le décodage des codes LDPC et turbocodes spécifiés dans les normes WiFi, WiMAX et LTE. L'extensibilité apportée par l'approche multi-ASIP basée sur des réseaux sur puces (NoC) permet d'atteindre les besoins en haut débit des normes actuelles et futures. La deuxième contribution concerne la conception d'un ASIP paramétré pour le turbo-décodage (TDecASIP). L'objectif étant d'étudier l'efficacité maximale atteignable pour un turbo décodeur basé sur le concept ASIP en maximisant l'exploitation du parallélisme de sous-blocs. En outre, avec cette architecture nous avons démontré la possibilité de concevoir des coeurs de traitement paramétrables et dédiés à l'application en utilisant le flot de conception ASIP existant. La troisième contribution correspond à la conception d'un ASIP optimisé pour le décodage des codes LDPC (LDecASIP). Comme pour TDecASIP, l'objectif étant d'étudier l'efficacité maximale atteignable pour un décodeur de codes LDPC basé sur le concept ASIP en augmentant le degré de parallélisme et la bande passante des mémoires. Une quatrième contribution principale de cette thèse porte sur le prototypage matériel. Une plateforme de communication complète intégrant 4-DecASIP pour le décodage de canal a été prototypé sur une carte à base de circuits FPGA. À notre connaissance, c'est le premier prototype FPGA publié de décodeur de canal flexible supportant le décodage des turbocodes et des codes LDPC avec une architecture multi-ASIP intégrant des NoC. De plus, une intégration ASIC de ce décodeur a été réalisée par le CEA-LETI dans la puce MAG3D visant des applications de communications pour la 4G. Ces résultats démontrent le cycle de conception rapide et l'efficacité offerte par l'approche de conception basée sur le concept ASIP dans ce domaine d'application, permettant ainsi d'affiner les compromis de conception par rapport aux divers objectifs ciblésLarge variety of channel coding techniques are specified in existing and emerging digital communication standards, each suitable for specific application needs (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc). Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio (SDR) and Cognitive Radio (CR) applications, flexible implementations combining multiple error correction techniques becomes mandatory. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing too and cannot be neglected against flexibility. In this context, this thesis work has investigated multi-ASIP architecture model towards the target of unifying flexibility-oriented and optimization-oriented approaches in the design of flexible channel decoders. By considering mainly the challenging Turbo and LDPC decoding applications, multi-ASIP channel decoder architectures are proposed targeting high flexibility combined with high architecture efficiency in terms of bits/cycle/iteration/mm2. Different architecture alternatives and design approaches are explored. Three original contributions have been proposed. The first one concerns the design of a scalable and flexible high throughput multi-ASIP LDPC/Turbo decoder. Several design objectives have been attained in this work in terms of scalability, resource sharing, and configurability speed. The proposed DecASIP supports the decoding of LDPC and Turbo codes specified in WiFi, WiMAX, and LTE standards. The achieved scalability through the multi-ASIP NoC based approach enables the accommodation of current and future high throughput requirements. The second contribution concerns the design of a parameterized ASIP for Turbo decoding (TDecASIP). Here the objective was to investigate the maximum attainable architecture efficiency for ASIP-based Turbo decoding when maximizing the usage of sub-block parallelism. Furthermore, with this architecture we demonstrated the possibility to design application-specific parameterized cores using the available ASIP design flow. The third contribution corresponds to the design of an optimized ASIP for LDPC decoding (LDecASIP). As for TDecASIP, the objective was to investigate the maximum attainable architecture efficiency for ASIP-based LDPC decoding by increasing the parallelism degree and the necessary memory bandwidth. A fourth main contribution of this thesis work concerns the hardware prototyping. A complete communication system platform including 4-DecASIP channel decoder has been prototyped on an FPGA-based logic emulation board. To our knowledge, this is the first demonstrated multi-ASIP NoC-based FPGA prototype that is capable of decoding LDPC and Turbo (SBTC and DBTC) codes. Furthermore, an ASIC integration of the 4-DecASIP system decoder has been accomplished by the CEA-LETI on the MAG3D Telecom chip which targets 4G communication applications. These results demonstrate the rapid design cycle and the effectiveness offered by the ASIP based design approach in this application domain to fine tune design trade-offs w. R. T. Diverse design objectives
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Yu, Bin. "Scaffold study of ASIP and AgRP : antagonists of melanocortin system /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2007. http://uclibs.org/PID/11984.
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Santos, Daniela Copetti. "Padrões de variabilidade do gene ASIP (agouti signaling protein) em mamíferos." Pontifícia Universidade Católica do Rio Grande do Sul, 2007. http://hdl.handle.net/10923/1294.
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Previous issue date: 2007O melanismo em mamíferos decorre principalmente da atividade de dois genes: MC1R (Melanocortin-1 Receptor), cujo produto induz a produção de eumelanina (pretomarrom); e ASIP (Agouti Signaling Protein), que codifica um peptídeo antagonista que promove a produção de feomelanina (pigmento claro). A combinação do efeito destes dois locos faz com que o pêlo cresça escuro com bandas subapicais amarelas. No presente estudo investigamos a diversidade nucleotídica e os padrões de variabilidade presentes no gene ASIP, principalmente nas regiões codificadoras dos éxons 2 e 3 e em regiões não codificadoras dos íntrons 2 e 3 em alguns mamíferos, com ênfase em felídeos (Mammalia, Carnivora, Felidae). Através do alinhamento entre as espécies analisadas nesse estudo foi possível construir três bases de dados que foram divididas em diferentes blocos conforme as regiões de alinhamento. A análise comparativa de seqüências permitiu a caracterização de diferentes blocos de seqüência conservada, assim como a identificação de uma inserção SINE presente apenas no gato doméstico, de uma região repetitiva hipervariável em todos os felídeos analisados, e também de variantes moleculares (SNPs) em Felis catus e Leopardus geoffroyi. Nenhum dos polimorfismos identificados nesta espécie estava localizado em regiões exônicas ou apresentou associação a fenótipos de coloração, indicando que as regiões analisadas não estão envolvidas na indução do melanismo nesta espécie.
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Packiaraj, Vivek. "Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task." Thesis, Linköping University, Electronics System, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52314.
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There is a lot of literature already available describing well-structured approach for embeddeddesign and implementation of Application Specific Integrated Processor (ASIP) micro processorcore.
This concept features hardware structured approach for implementation of processor core fromminimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIPprocessor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. Thereport is a well structured approach of design and implementation of an ASIP DSP processor forDSP applications like FIR. This report contains design flow starting from Instruction set design,micro architecture design and RTL implementation of the core. Details of the power simulationsof FPGA are also listed and analyzed.
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Lapinskii, Viktor. "Algorithms for compiler-assisted design space exploration of clustered VLIW ASIP datapaths /." Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008376.
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Chan, Chun-Jung. "Investigation of NoGap : SIMD Datapath Implementation." Thesis, Linköpings universitet, Institutionen för systemteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72131.
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Nowadays, many ASIP systems with high computational capabilities are designed in order to fulfill the increasing demands of technical applications. However, the design of ASIP system usually takes many man hours. Therefore, a number of EDA tools are developed to ease the design effort, but they limit the design freedom due to their predefined design templates. Consequently, designers are forced to use lower level HDLs which offer high design flexibility but require substantial design hours. A novel design automation tool called NoGap was proposed to balance such issues. The NoGap system, which is especially used in ASIPs and accelerator design, effectively provides high design flexibility and saves design effort for designers. The efficiency and design ability of NoGap were investigated in this thesis work. NoGap was used to implement an eight-way SIMD datapath of an ASIP called Sleipnir, which was devised by the Division of Computer Engineering at Linköping University. For contrast, the manually crafted HDL implementation of the Sleipnir was taken. The critical path implementations, done by both design approaches, were synthesized to the Altera Strtix IV FPGA. The synthesize results showed that the NoGap design although used 1.358 times as many hardware units as the original HDL design. Their timing performance is comparable (HDL/NoGap-60.042/58.156Mhz). In this thesis, based on the design experience of SIMD datapath, valuable aspects were suggested to benefit the future users who will use NoGap to implement SIMD structures. In addition, the hidden bugs and insufficient features of NoGap were discovered, and the referable suggestions were provided in order to help the developers to improve the NoGap system.
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Yaochuan, Chen. "Binary Instruction Format Specification for NoGap." Thesis, Linköpings universitet, Datorteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114199.
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Nowadays, hardware designers want to get a powerful and friendly tool to speedup the design flow and design quality. The new development suit NoGap is pro-posed to meet those requirements. NoGap is a design automation tool for ASIP,it helps users to focus on the design stage, free them from module connection andsignal assignment, or integration. Different from the normal ADL tools which limitusers’ design ideas to some template frameworks, NoGap allow designers to im-plement what they want with NoGap Common Language (NoGapCL). However,NoGap is still not perfect, some important functionalities are lacking, but withthe flexible generator component structure, NoGap and NoGapCL can easily beextended.This thesis will firstly investigate the structure of Novel Generator of Acceler-ators and Processors (NoGap) from software prospective view, and then present anew NoGap generator, OpCode Assignment Generator (OpAssignGen), which al-lows users to assign operation code values, exclude operation codes and customizethe operation code size or instruction size.A simple example based on the Microprocessor without Interlocked PipelineStages (MIPS) instructions sets will be mentioned to give users a brief view ofhow to use OpAssignGen. After that, the implementation of the new generatorwill be explained in detail.What’s more, some of NoGap’s flaws will be exposed, but more suggestionsand improvements for NoGap will be given.At last, a successful synthesis result based on the simple MIPS hardware im-plementation will be shown to prove the new generator is well implemented. Moreresults and the final conclusion will be given at the end of the thesis.
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Santos, Daniela Copetti. "Padr?es de variabilidade do gene ASIP (agouti signaling protein) em mam?feros." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2007. http://tede2.pucrs.br/tede2/handle/tede/5527.
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Previous issue date: 2007-08-10O melanismo em mam?feros decorre principalmente da atividade de dois genes: MC1R (Melanocortin-1 Receptor), cujo produto induz a produ??o de eumelanina (pretomarrom); e ASIP (Agouti Signaling Protein), que codifica um pept?deo antagonista que promove a produ??o de feomelanina (pigmento claro). A combina??o do efeito destes dois locos faz com que o p?lo cres?a escuro com bandas subapicais amarelas. No presente estudo investigamos a diversidade nucleot?dica e os padr?es de variabilidade presentes no gene ASIP, principalmente nas regi?es codificadoras dos ?xons 2 e 3 e em regi?es n?o codificadoras dos ?ntrons 2 e 3 em alguns mam?feros, com ?nfase em fel?deos (Mammalia, Carnivora, Felidae). Atrav?s do alinhamento entre as esp?cies analisadas nesse estudo foi poss?vel construir tr?s bases de dados que foram divididas em diferentes blocos conforme as regi?es de alinhamento. A an?lise comparativa de seq??ncias permitiu a caracteriza??o de diferentes blocos de seq??ncia conservada, assim como a identifica??o de uma inser??o SINE presente apenas no gato dom?stico, de uma regi?o repetitiva hipervari?vel em todos os fel?deos analisados, e tamb?m de variantes moleculares (SNPs) em Felis catus e Leopardus geoffroyi. Nenhum dos polimorfismos identificados nesta esp?cie estava localizado em regi?es ex?nicas ou apresentou associa??o a fen?tipos de colora??o, indicando que as regi?es analisadas n?o est?o envolvidas na indu??o do melanismo nesta esp?cie.
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Richtarik, Pavel. "Rychlý a částečně překládaný simulátor pro aplikačně specifické procesory." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385970.
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The major objective of this work is to analyse possibilities of using simulation within the development of application-specific instruction-set processors, to explore and compare some common simulation techniques and to use the collected information to design a new simulation tool suitable for utilization in the processors development and optimization. This thesis presents the main requirements on the new simulator and describes the design and implementation of its key parts with emphasis on the high performance.
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Piscoya, Silva Ulises Abdon. "Diseño y simulación de un microprocesador de propósitos específicos (ASIP) utilizando el lenguaje de programacion VHDL." Universidad Nacional de Ingeniería. Programa Cybertesis PERÚ, 2006. http://cybertesis.uni.edu.pe/uni/2006/piscoya_su/html/index-frames.html.
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En el presente trabajo se muestra el diseño de un microprocesador de propósitos específicos (ASIP) utilizando programación en VHDL y tomando como referencia los dispositivos de la empresa ALTERA . El programador del ASIP podrá utilizar este microprocesador y sus recursos de la manera que estime conveniente. - En el capitulo I se hacen los primeros planteamientos y descripciones del ASIP , se definen las instrucciones que se desean ejecutar y los ciclos de instrucción. - En el capitulo II se diseña el ALU (Unidad Aritmética y Lógica) del ASIP , además de ello se realiza una simulación de cada uno de los subsistemas del ALU. - En el capitulo III se desarrolla el diseño y simulación de los subsistemas de la unidad de control del ASIP. - En el capitulo IV se desarrolla el diseño y simulación de los subsistemas que forman la unidad de procesamiento , se definen los registros del ASIP , se diseña el decoder de instrucciones , se define el bus de datos , el bus de direcciones y el contador de direcciones. - En el capitulo V se hace el desarrollo de la arquitectura del ASIP . - En el capitulo VI se realiza el diseño y la simulación de los subsistemas que producen los saltos e interrupciones con pines externos del ASIP. En el capitulo VII se elabora un programa TEST para poder verificar y simular todas las instrucciones del ASIP. - En el capitulo VIII se realiza un reporte acerca de la grabación del programa TEST dentro del FLEX de altera .
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Skoglund, Björn. "Code profiling as a design tool for application specific instruction sets." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8585.
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As the embedded devices has become more and more generalized and as their product cycles keeps shrinking the field has opened up for the Application Specific Instruction set Processor. A mix between the classic generalized microcontroller and the specialized ASIC the ASIP keeps a set of general processing instructions for executing embedded software but combines that with a set of heavily specialized instructions for speeding up the data intense application core algorithms. One important aspect of the ASIP design flow
research is cutting design time and cost. One way of that is automation of the instruction set design. In order to do so a process is needed where the algorithm to be ASIPed is analyzed and critical operations are found and exposed so that they can be implemented in special hardware. This process is called profiling. This thesis describes an implementation of a fine grained source code profiler for use in an ASIP design flow. The profiler software is based on a static-dynamic workflow where data is assembled from both static
analysis and dynamic execution of the program and then analyzed together in an specially made analysis software.
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Nilsson, Anders. "Design of programmable multi-standard baseband processors." Doctoral thesis, Linköping : Department of Electrical Engineering, Linköping University, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8908.
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Reichel, Peter. "Effizienter Einsatz von Bildsensoren mit integrierter Signalverarbeitung." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-227708.
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Bildsensoren mit integrierter Signalverarbeitung - sog. "Vision Chips" - ermöglichen die Ausführung ansonsten rechenintensiver Verarbeitungsschritte während oder unmittelbar nach der Bildaufnahme. Gegenüber konventionellen CMOS-Bildsensoren, die sich vor allem durch eine gute Bildqualität auszeichnen, werden die auszugebenden Daten bereits auf dem Chip auf relevante Informationen beschränkt und lediglich extrahierte Merkmale anstelle vollständiger Bilder ausgegeben. Vision Chips ermöglichen somit eine sehr hohe Bildwiederholrate bei gleichzeitig deutlich niedrigeren Anforderungen bzgl. der Übertragungsbandbreite und sind insbesondere für die Beobachtung sehr schneller Prozesse attraktiv.
Obwohl das Konzept der gemeinsamen Betrachtung von Bildaufnahme und -verarbeitung bereits in den Anfangsjahren der Halbleiter-Bildsensoren aufgegriffen wurde, können die meisten beschriebenen Sensoren als Machbarkeitsnachweise für bestimmte Pixelzellen- bzw. Bildverarbeitungstechnologien betrachtet werden. So finden sich, bis auf den in der optischen Maus eingesetzten Sensor zur Bestimmung der Verschiebung relativ zum Untergrund, nur für sehr wenige Sensoren Hinweise auf einen kommerziellen Einsatz. Neben einer geringen optischen Auflösung und einer eingeschränkten Empfindlichkeit können der Verzicht auf integrierte Steuerwerke und die erhebliche Komplexität bzgl. der Programmierung als wesentliche Hindernisse für einen breiten Einsatz genannt werden.
Im Rahmen dieser Arbeit werden wesentliche Beiträge zu der zum Einsatz von Vision Chips in realen Aufgabenstellungen erforderlichen Infrastruktur geliefert. So wird zur Ansteuerung der einzelnen Funktionseinheiten (Functional Unit, FU) zunächst das Konzept eines integrierten, Multi-ASIP (Application Specific Instruction-set Processor) basierten Steuerwerks erarbeitet, das durch die Bereitstellung mehrerer Kontrollflüsse die Ansteuerung paralleler FU ermöglicht. Die praktische Umsetzung des Konzepts in Hardware erfolgt als Bestandteil eines Vision-System-on-Chip (VSoC). Dieses verfügt gegenüber dem Stand der Technik über eine höhere Auflösung sowie eine größere Empfindlichkeit und bildet die Grundlage der weiteren Betrachtungen. Eine umfangreiche Simulationsumgebung ermöglicht Untersuchungen implementierter Algorithmen sowohl hinsichtlich zeitabhängiger Effekte als auch bzgl. der Auswirkung einzelner, in Bildaufnahme- und Verarbeitung gezielt eingebrachter Fehler und Nicht-Idealitäten. Die zum Betrieb des VSoC erforderliche Entwicklungs- und Kameraplattform ist sowohl für den Einsatz unter realen Bedingungen als auch zur Entwicklung von Bildverarbeitungsaufgaben geeignet und ermöglicht dabei die transparente Nutzung der Simulationsumgebung komplementär zur eigentlichen Hardware. Zur Erschließung der vom VSoC bereitgestellten Funktionalität für tatsächliche Aufgabenstellungen erfolgt die ganzheitliche Betrachtung einer Bildverarbeitungsaufgabe bestehend aus VSoC-basierter Vor- und konventioneller Nachverarbeitung in Form sog. "Vision Tasks". Zur Vereinfachung der Implementierung werden parametrierbare Skeletons bereitgestellt, in denen generelle Abläufe zur Bildaufnahme und -verarbeitung hinterlegt werden. Basierend auf den entwickelten Konzepten werden schließlich mehrere Anwendungsbeispiele umgesetzt.
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Cousin, Jean-Gabriel. "Methodologies de conception de coeurs de processeurs specifiques (asip) : mise en oeuvre sous contraintes, estimation de la consommation." Rennes 1, 1999. http://www.theses.fr/1999REN10085.
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L'evolution rapide des applications de telecommunications, du multimedia et de l'electronique grand public offre la possibilite de realiser un systeme complet sur une meme puce. L'integration a un niveau d'abstraction eleve de ces applications sur des curs de processeurs flexibles, permet de reduire le temps de conception et le cout du produit. Nous etudions ici l'asip, une solution materielle heterogene, specifique, performante et flexible, de surface et de consommation reduites. Nous definissons des methodologies de conception de curs d'asip pour un environnement de synthese de haut niveau. Ces methodologies s'appuient sur des algorithmes d'ordonnancement par liste et sont nanties d'estimateurs de consommation assistant l'integration d'algorithmes en vue d'une optimisation. Nous ciblons et experimentons sur les applications de traitement du signal et d'images orientees flot de donnees, contraintes en temps ou restreintes en surface. Une premiere methodologie synthetise continument les algorithmes contraints en temps choisis pour caracteriser l'application consideree, et concoit le cur d'asip correspondant dont on deduit le jeu d'instructions ; la seconde, similaire a la premiere, permet de surcroit d'agir sur l'algorithmie ou sur l'architecture en cours de conception, en reaction aux informations delivrees par nos estimateurs. La troisieme nous confere la possibilite de concevoir une architecture vlsi a ressources contraintes. Par cette technique et par la flexibilite de l'architecture, nous prospectons sur l'implementation d'algorithmes par le biais de notre environnement de synthese materielle. Notre presentation des techniques avancees d'estimation et d'optimisation de la consommation, nous permet de degager les modeles caracterisant les composants de nos asip. Nous presentons trois estimateurs de la consommation : le premier agit lors de l'execution des modules usuels de la synthese, le second estime apres synthese complete de l'algorithme cible et le troisieme s'appuie sur le jeu d'instructions du cur d'asip synthetise. Pour assurer le suivi de nos recherches, nous effectuons une analyse critique, tant sur le developpement de nos outils elabores et sur la conduite de nos methodologies, que sur les resultats de nos experimentations
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Eusse, Giraldo Juan Fernando [Verfasser], Rainer [Akademischer Betreuer] Leupers, and Holger [Akademischer Betreuer] Blume. "ASIP algorithmic/architectural co-exploration based on high level performance estimation / Juan Fernando Eusse Giraldo ; Rainer Leupers, Holger Blume." Aachen : Universitätsbibliothek der RWTH Aachen, 2019. http://d-nb.info/1220359505/34.
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Lundgren, Björn, and Anders Ödlund. "Exposure of Patterns in Parallel Memory Acces." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9795.
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The concept and advantages of a Parallel Memory Architecture (PMA) in computer systems have been known for long but it’s only in recent time it has become interesting to implement modular parallel memories even in handheld embedded systems. This thesis presents a method to analyse source code to expose possible parallel memory accesses. Memory access Patterns may be found, categorized and the corresponding code marked for optimization. As a result a PMA compatible with found pattern(s) and code optimization may be specified.
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Radhakrishnan, Swarnalatha Computer Science & Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.
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Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.
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Léonardon, Mathieu. "Décodage de codes polaires sur des architectures programmables." Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0399/document.
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Les codes polaires constituent une classe de codes correcteurs d’erreurs inventés récemment qui suscite l’intérêt des chercheurs et des industriels, comme en atteste leur sélection pour le codage des canaux de contrôle dans la prochaine génération de téléphonie mobile (5G). Un des enjeux des futurs réseaux mobiles est la virtualisation des traitements numériques du signal, et en particulier les algorithmes de codage et de décodage. Afin d’améliorer la flexibilité du réseau, ces algorithmes doivent être décrits de manière logicielle et être déployés sur des architectures programmables. Une telle infrastructure de réseau permet de mieux répartir l’effort de calcul sur l’ensemble des noeuds et d’améliorer la coopération entre cellules. Ces techniques ont pour but de réduire la consommation d’énergie, d’augmenter le débit et de diminuer la latence des communications. Les travaux présentés dans ce manuscrit portent sur l’implémentation logicielle des algorithmes de décodage de codes polaires et la conception d’architectures programmables spécialisées pour leur exécution.Une des caractéristiques principales d’une chaîne de communication mobile est l’instabilité du canal de communication. Afin de remédier à cette instabilité, des techniques de modulations et de codages adaptatifs sont utilisées dans les normes de communication.Ces techniques impliquent que les décodeurs supportent une vaste gamme de codes : ils doivent être génériques. La première contribution de ces travaux est l’implémentation logicielle de décodeurs génériques des algorithmes de décodage "à Liste" sur des processeurs à usage général. En plus d’être génériques, les décodeurs proposés sont également flexibles.Ils permettent en effet des compromis entre pouvoir de correction, débit et latence de décodage par la paramétrisation fine des algorithmes. En outre, les débits des décodeurs proposés atteignent les performances de l’état de l’art et, dans certains cas, les dépassent.La deuxième contribution de ces travaux est la proposition d’une nouvelle architecture programmable performante spécialisée dans le décodage de codes polaires. Elle fait partie de la famille des processeurs à jeu d’instructions dédiés à l’application. Un processeur de type RISC à faible consommation en constitue la base. Cette base est ensuite configurée,son jeu d’instructions est étendu et des unités matérielles dédiées lui sont ajoutées. Les simulations montrent que cette architecture atteint des débits et des latences proches des implémentations logicielles de l’état de l’art sur des processeurs à usage général. La consommation énergétique est réduite d’un ordre de grandeur. En effet, lorsque l’on considère le décodage par annulation successive d’un code polaire (1024,512), l’énergie nécessaire par bit décodé est de l’ordre de 10 nJ sur des processeurs à usage général contre 1 nJ sur les processeurs proposés.La troisième contribution de ces travaux est également une architecture de processeur à jeu d’instructions dédié à l’application. Elle se différencie de la précédente par l’utilisation d’une méthodologie de conception alternative. Au lieu d’être basée sur une architecture de type RISC, l’architecture du processeur proposé fait partie de la classe des architectures déclenchées par le transport. Elle est caractérisée par une plus grande modularité qui permet d’améliorer très significativement l’efficacité du processeur. Les débits mesurés sont alors supérieurs à ceux obtenus sur les processeurs à usage général. La consommation énergétique est réduite à environ 0.1 nJ par bit décodé pour un code polaire (1024,512) avec l’algorithme de décodage par annulation successive. Cela correspond à une réduction de deux ordres de grandeur en comparaison de la consommation mesurée sur des processeurs à usage généralPolar codes are a recently invented class of error-correcting codes that are of interest to both researchers and industry, as evidenced by their selection for the coding of control channels in the next generation of cellular mobile communications (5G). One of the challenges of future mobile networks is the virtualization of digital signal processing, including channel encoding and decoding algorithms. In order to improve network flexibility, these algorithms must be written in software and deployed on programmable architectures.Such a network infrastructure allow dynamic balancing of the computational effort across the network, as well as inter-cell cooperation. These techniques are designed to reduce energy consumption, increase through put and reduce communication latency. The work presented in this manuscript focuses on the software implementation of polar codes decoding algorithms and the design of programmable architectures specialized in their execution.One of the main characteristics of a mobile communication chain is that the state of communication channel changes over time. In order to address issue, adaptive modulationand coding techniques are used in communication standards. These techniques require the decoders to support a wide range of codes : they must be generic. The first contribution of this work is the software implementation of generic decoders for "List" polar decoding algorithms on general purpose processors. In addition to their genericity, the proposed decoders are also flexible. Trade-offs between correction power, throughput and decodinglatency are enabled by fine-tuning the algorithms. In addition, the throughputs of the proposed decoders achieve state-of-the-art performance and, in some cases, exceed it.The second contribution of this work is the proposal of a new high-performance programmable architecture specialized in polar code decoding. It is part of the family of Application Specific Instruction-set Processors (ASIP). The base architecture is a RISC processor. This base architecture is then configured, its instruction set is extended and dedicated hardware units are added. Simulations show that this architecture achieves through puts and latencies close to state-of-the-art software implementations on generalpurpose processors. Energy consumption is reduced by an order of magnitude. The energy required per decoded bit is about 10 nJ on general purpose processors compared to 1nJ on proposed processors when considering the Successive Cancellation (SC) decoding algorithm of a polar code (1024,512).The third contribution of this work is also the design of an ASIP architecture. It differs from the previous one by the use of an alternative design methodology. Instead of being based on a RISC architecture, the proposed processor architecture is part of the classof Transport Triggered Architectures (TTA). It is characterized by a greater modularity that allows to significantly improve the efficiency of the processor. The measured flowrates are then higher than those obtained on general purpose processors. The energy consumption is reduced to about 0.1 nJ per decoded bit for a polar code (1024,512) with the SC decoding algorithm. This corresponds to a reduction of two orders of magnitude compared to the consumption measured on general purpose processors
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Qin, An. "Design and Implementation of a Source Code Profiling Toolset for Embedded System Analysis." Thesis, Linköpings universitet, Datorteknik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63525.
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The market needs for embedded or mobile devices were exploding in the last few years. Customers demand for devices that not only have high capacity of managing various complex jobs, but also can do it fast. Manufacturers therefore, are looking for a new field of processors that fits the special needs of embedded market, for example low power consumption, highly integrated with most components, but also provides the ability to handle different use cases. The traditional ASICs satisfied the market with great performance-per-watt but limited scalability. ASIP processors on the other hand, impact the new market with the ability of high-speed optimized general computing while energy efficiency is only slightly lower than ASICs. One essential problem in ASIP design is how to find the algorithms that can be accelerated. Hardware engineers used to optimize the instruction set manually. But with the toolset introduced in this thesis, design automation can be made by program profiling and the development cycle can be trimmed therefore reducing the cost. Profiling is the process of exposing critical parts of a certain program via static code analysis or dynamic performance analysis. This thesis introduced a code profiler that targeted at discovering repetition section of a program through static and dynamic analysis. The profiler also measures the payload of each loop and provides profiling report with a user friendly GUI client.
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Hepp, Diego. "Influência dos genes candidatos MC1R, ASIP, TYRP1 e kit na pigmentação em ovinos crioulos e predição do efeito dos polimorfismos não sinônimos no gene MC1R humano." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/119623.
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A coloração dos animais é uma característica que apresenta uma grande diversidade de fenótipos nas diferentes espécies. Diferentes abordagens podem ser utilizadas para o entendimento da diversidade na coloração existente nas espécies animais. Através da análise de genes candidatos as mutações responsáveis pela variação na coloração têm sido descritas em diferentes espécies, demonstrando o envolvimento de mecanismos moleculares variados na sua regulação. Este trabalho tem por objetivo a utilização de duas abordagens genéticas para o estudo da variação na coloração, a análise de genes candidatos e a predição computacional do efeito de polimorfismos não sinônimos. Em ovinos a coloração da lã é uma característica com importância na produção e para a identificação das raças. Polimorfismos em diferentes genes foram associados com a coloração da lã, entretanto, estes não foram estudados em muitas raças que apresentam variação fenotípica. A ovelha crioula é uma raça local existente no sul do Brasil que apresenta uma ampla diversidade de cores na lã, incluindo branco, preto e diversos tons intermediários. O gene receptor de melanocortina 1 (MC1R) foi previamente associado com a coloração na raça crioula, entretanto, outros genes também devem estar envolvidos na regulação da coloração na raça. Este trabalho avaliou a influência dos genes MC1R, ASIP (proteína sinalizadora agouti), TYRP1 (proteína relacionada à tirosinase 1) e KIT (homólogo do oncogene de sarcoma felino viral v-kit Hardy-Zuckerman 4) na coloração da lã na raça ovina crioula. Amostras de 410 animais de diferentes cores foram analisadas, sendo a variação na coloração da lã determinada por colorimetria. O padrão de herança dos fenótipos foi avaliado através de cruzamentos dirigidos entre indivíduos de diferentes cores. Os polimorfismos nos genes foram avaliados através da realização do sequenciamento e da análise de fragmentos e a quantificação da expressão do gene ASIP foi realizada por PCR em Tempo Real. Foi observada a associação significativa entre polimorfismos nos genes MC1R e ASIP e a cor da lã na raça crioula. O alelo dominante do gene MC1R, provocado pelas mutações p.M73K e p.D121N, foi encontrado apenas em indivíduos pigmentados. Este alelo resulta na ativação constitutiva do receptor, e consequentemente na produção constante de eumelanina, sendo epistático sobre o gene ASIP. Nos animais homozigotos para o alelo selvagem do MC1R a manifestação do fenótipo branco ocorreu somente nos portadores de um alelo contendo a duplicação do gene ASIP. Os portadores da duplicação do ASIP apresentaram níveis elevados de expressão do gene enquanto os homozigotos para a cópia simples do ASIP não expressaram o gene e apresentaram fenótipos pigmentados. Os resultados obtidos permitiram identificar a influência da interação epistática dos genes MC1R e ASIP na coloração da lã nos ovinos crioulos. O estudo de genes candidatos envolvidos na rota da pigmentação mostrou-se uma abordagem adequada para a análise da variação na coloração nestes animais. Espera-se que o conhecimento adquirido neste trabalho auxilie na criação e na preservação da raça através da manutenção da diversidade fenotípica existente. A avaliação computacional dos polimorfismos não sinônimos vem sendo utilizada recentemente a fim de determinar os SNPs que potencialmente afetam o funcionamento dos genes e identificar os mecanismos responsáveis por doenças complexas e pela variação nos fenótipos. A predição do efeito de polimorfismos nos genes utilizando ferramentas computacionais apresenta-se como uma abordagem alternativa para o estudo da genética da coloração. O gene MC1R humano apresenta uma grande quantidade de polimorfismos alguns dos quais foram associados com a variação na pigmentação e com suscetibilidade a tumores de pele. Entretanto, muitas das variações existentes no gene não foram avaliadas quanto às suas consequências funcionais e o seu papel na variação da pigmentação. Foi realizada a predição computacional dos polimorfismos não sinônimos no gene MC1R humano com o objetivo de identificar os nsSNPs mais provavelmente danosos, e estabelecer aqueles com potencial efeito na função do MC1R. Foram utilizadas 11 ferramentas de predição individuais (SIFT, MutPred, Polyphen-2, PROVEAN, I-Mutant 3.0, PANTHER, SNPs3D, Mutation Assessor, PhD-SNP, SNPs&GO e SNAP) e dois programas consenso (PON-P e PredictSNP 1.0) para a análise de 92 nsSNPs localizados no gene. Os programas utilizados baseiam-se em métodos evolutivos, estruturais e computacionais, resultando na identificação dos 14 nsSNPs mais danosos (L48P, R67W, H70Y, P72L, S83P, R151H, S172I, L206P, T242I, G255R, P256S, C273Y, C289R e R306H). Apesar das diferenças nos resultados de cada programa a combinação dos diferentes métodos permitiu diferenciar os polimorfismos neutros dos danosos, mostrando concordância com os programas consenso. A predição computacional demonstrou ser uma abordagem eficiente para a identificação dos alelos danosos no gene MC1R e para a priorização de mutações para posteriores estudos funcionais e populacionais.Animal color is a characteristic that presents a large diversity of phenotypes. Different approaches can be used to understand the color diversity existing among and within species. Through analysis of candidate genes the mutations responsible for the color variation have been described in different species, showing the involvement of various molecular mechanisms of regulation. The objective of this work is the use of two genetic approaches to the study of color variation, the analysis of candidate genes and the computational prediction of non-synonym polymorphism effects (nsSNPs). In sheep the wool color is a feature with commercial importance and in identifying breeds. Polymorphisms in different genes have been associated with wool color, but they have not been studied in many breeds that show phenotypic variation regarding such a charactere. The Creole is a local breed from southern most Brazil that presents a wide range of wool color, varying from white to black, and including several intermediate hues. The melanocortin 1 receptor (MC1R) was previously associated with the wool color in the Creole, however, other genes might also be involved in the regulation of color in the breed. This study evaluated the influence of the genes MC1R, ASIP (agouti signaling protein), TYRP1 (tyrosinase related protein 1) and KIT (v-kit Hardy- Zuckerman 4 feline sarcoma viral oncogene homolog) in the Creole breed wool color. Samples from 410 specimens of different colors were analyzed. The variation in the color of the wool was performed by colorimetry. The inheritance pattern of the phenotypes was assessed by crossbreeding individuals of different colors. Polymorphisms in the genes were evaluated by performing sequencing and fragment analysis, and the quantification of the ASIP gene expression was performed by Real Time-PCR. It was observed a significant association between polymorphisms in MC1R and ASIP gene and the wool color in Creole breed. The dominant allele of the MC1R gene, caused by p.M73K and p.D121N mutations was found only in pigmented individuals. This allele leads to the constitutive activation of the receptor and therefore in constant production of eumelanin and is epistatic on the ASIP gene. In the homozygous to the wild-type allele of MC1R the manifestation of white phenotype occurred only in individuals with one allele containing a duplication of the ASIP gene. The carriers of the duplicated copy of ASIP showed high levels of gene expression while homozygous for the simple copy of the ASIP did not expressed the gene, and showed pigmented phenotypes. The results allowed the identification of the influence of epistatic interaction of MC1R and ASIP gene in the wool color in Creole breed. The study of candidate genes involved in the pigmentation pathway proved to be a suitable approach for the analysis of variation in pigmentation in these animals. It is expected that the knowledge acquired in this work will assist on stablishment of commercial breeding and preservation policies of this sheep breed. The computational evaluation of non-synonymous polymorphism has been used to determine SNPs that potentially affect the function of the genes and identify the mechanisms responsible for complex diseases and by the variation in phenotypes. The prediction of the effect of polymorphisms in genes using computational tools presents an alternative approach to the study of the genetic of coloration. The human MC1R gene has a large number of know polymorphisms, some of which were associated with changes in pigmentation and susceptibility to skin tumors. However, many existing variations in the gene have not been evaluated regarding the functional consequences and its role in the variation of pigmentation. Computational prediction of nonsynonymous polymorphisms was performed in the human MC1R gene in order to identify the most likely harmful nsSNPs and to establish those with potential effect on the function of MC1R. Eleven individual tools (SIFT, MutPred, Polyphen-2, PROVEAN, I-Mutant 3.0, PANTHER, SNPs3D, Mutation Assessor, PhD-SNP, SNPs&GO and SNAP) and two consensus programs (PON-P and PredictSNP 1.0) were used to the analysis of 92 nsSNPs located in the gene. The programs used are based in evolutionary, structural and computational methods, resulting in the identification of the 14 most damaging nsSNPs (L48P, R67W, H70Y, P72L, S83P, R151H, S172I, L206P, T242I, G255R, P256S, C273Y, C289R and R306H). Despite the differences in the results of the each program the combination of different methods allowed the differentiation of the neutral polymorphisms from the most damaging, showing agreement with the consensus programs. The computational prediction has proved to be an efficient approach for the identification of harmful alleles in the MC1R gene and for the prioritization of mutations for further functional and population studies.
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Mikó, Albert. "Akcelerace aplikací pomocí specializovaných instrukcí." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255444.
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The design of specialized instructions for application specific processors is a challenging task. This thesis describes the issues of effective specification and use of specialized instructions for optimization of applications. It focuses on improvements of the outputs and usability of the semiatomatic method of selection of specialized instructions to allow the optimization of complicated applications. This method combines manual selection of instructions by marking a section of source code in the application and automatic generation of the instruction description in the modelling language.
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Akhlaq, Faisal, and Sumathi Loganathan. "Assembler Generator and Cycle-Accurate Simulator Generator for NoGAP." Thesis, Linköping University, Department of Computer and Information Science, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56999.
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System-on-Chip is increasingly built using ASIP(Application Specific Instruction set Processor) due to the flexibility and efficiency obtained from ASIPs. NoGAP (Novel Generator of Accelerator and Processor framework) is an innovative approach for ASIP design, which provides the advantage of both ADL (Architecture Description Language) and HDL (Hardware Description Language) to the designer.
For the processors designed using NoGAP, software tools need to be automatically generated, to aid the designer in programming and verifying the processor. As part of the master thesis work, we have developed two generators namely Assembler generator and Cycle-Accurate Simulator generator for NoGAP using C++. The Assembler generator automatically generates an assembler, which is used to convert the assembly code written by a programmer into relocatable binary code. The Cycle-Accurate Simulator generator automatically generates a cycle-accurate simulator to model the behavior of the designed processor. Both these generators are static, and can be used to generate the tools for any processor created using NoGAP.
In this report, we have detailed the concepts behind the generators,and the implementation details of the generators. We have listed the results obtained from running assembler and cycle-accurate simulator on a test processor created using NoGAP.
NoGAP
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McRobie, Helen R. "The genetic and molecular basis of melanism in the grey squirrel (sciurus carolinensis)." Thesis, Anglia Ruskin University, 2014. https://arro.anglia.ac.uk/id/eprint/576178/1/The%20Genetic%20and%20Molecular%20Basis%20of%20Melanism%20in%20the%20Grey%20Squirrel%20Helen%20McRobie.pdf.
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The grey squirrel (Sciurus carolinensis) has wildtype and melanic (dark) colour morphs.
Melanism is associated with variations in the melanocortin-1 receptor (MC1R) gene in a
number of species. The MC1R protein is a G-protein coupled receptor, predominantly
expressed in melanocytes, where it is a key regulator of pigment production. To investigate
the genetic and molecular basis of melanism, the MC1R genes of the wildtype and melanic
grey squirrel were sequenced. The wildtype (MC1R-wt) and melanic (MC1RΔ24) variants of
the MC1R were then functionally characterised in a cell-based assay.
The MC1R gene of the grey squirrel was found to have a 24 base pair (bp) deletion associated
with melanism. The MC1R is typically activated by its agonist, the alpha-melanocyte
stimulating hormone (α-MSH), which stimulates dark pigment production by raising
intracellular cAMP levels. Conversely, the MC1R is inactivated by its inverse agonist, the
agouti signalling protein (ASIP), which stops dark pigment production by lowering
intracellular cAMP levels. To investigate the effects that the 24 bp deletion have on receptor
function, MC1R-wt and MC1RΔ24 genes were transfected into HEK293 cells. Cells
expressing either MC1R-wt or MC1RΔ24 were stimulated with α-MSH or ASIP and
intracellular cAMP levels were measured. Unstimulated MC1RΔ24 cells showed higher basal
activity than the MC1R-wt cells. Both MC1R-wt and MC1RΔ24 cells responded to α-MSH
with a concentration-dependent increase in intracellular cAMP. However, while the MC1Rwt
cells responded to ASIP with a concentration-dependent decrease in intracellular cAMP,
MC1RΔ24 cells responded with an increase in cAMP.
Melanism in the grey squirrel is associated with a 24 bp deletion in the MC1R. Cells
expressing MC1RΔ24 have higher basal levels of cAMP than MC1R-wt cells. ASIP acts as
an inverse agonist to the MC1R-wt but as an agonist to the MC1RΔ24. As MC1RΔ24 cells
have higher levels of cAMP, and higher levels of cAMP lead to dark pigment production, the
24 bp deletion is the likely molecular cause of melanism in the grey squirrel.
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McRobie, Helen R. "The genetic and molecular basis of melanism in the grey squirrel (Sciurus carolinensis)." Thesis, Anglia Ruskin University, 2014. http://arro.anglia.ac.uk/576178/.
Full textAbstract:
The grey squirrel (Sciurus carolinensis) has wildtype and melanic (dark) colour morphs. Melanism is associated with variations in the melanocortin-1 receptor (MC1R) gene in a number of species. The MC1R protein is a G-protein coupled receptor, predominantly expressed in melanocytes, where it is a key regulator of pigment production. To investigate the genetic and molecular basis of melanism, the MC1R genes of the wildtype and melanic grey squirrel were sequenced. The wildtype (MC1R-wt) and melanic (MC1RΔ24) variants of the MC1R were then functionally characterised in a cell-based assay. The MC1R gene of the grey squirrel was found to have a 24 base pair (bp) deletion associated with melanism. The MC1R is typically activated by its agonist, the alpha-melanocyte stimulating hormone (α-MSH), which stimulates dark pigment production by raising intracellular cAMP levels. Conversely, the MC1R is inactivated by its inverse agonist, the agouti signalling protein (ASIP), which stops dark pigment production by lowering intracellular cAMP levels. To investigate the effects that the 24 bp deletion have on receptor function, MC1R-wt and MC1RΔ24 genes were transfected into HEK293 cells. Cells expressing either MC1R-wt or MC1RΔ24 were stimulated with α-MSH or ASIP and intracellular cAMP levels were measured. Unstimulated MC1RΔ24 cells showed higher basal activity than the MC1R-wt cells. Both MC1R-wt and MC1RΔ24 cells responded to α-MSH with a concentration-dependent increase in intracellular cAMP. However, while the MC1Rwt cells responded to ASIP with a concentration-dependent decrease in intracellular cAMP, MC1RΔ24 cells responded with an increase in cAMP. Melanism in the grey squirrel is associated with a 24 bp deletion in the MC1R. Cells expressing MC1RΔ24 have higher basal levels of cAMP than MC1R-wt cells. ASIP acts as an inverse agonist to the MC1R-wt but as an agonist to the MC1RΔ24. As MC1RΔ24 cells have higher levels of cAMP, and higher levels of cAMP lead to dark pigment production, the 24 bp deletion is the likely molecular cause of melanism in the grey squirrel.
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Lemos, Ana Cláudia Cavalcante Espósito [UNESP]. "Estudo histomorfométrico, ultraestrutural e da expressão de Wnt1, WIF-1 e ASIP na pele com melasma em comparação com a pele sã perilesional e retroauricular." Universidade Estadual Paulista (UNESP), 2017. http://hdl.handle.net/11449/151232.
Full textAbstract:
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Fundo de Apoio à Dermatologia de São Paulo (FUNADERSP)
O melasma é hipermelanose crônica e adquirida decorrente de um complexo processo que envolve hipertrofia melanocítica e disfunção melanogênica. Acomete preferencialmente o sexo feminino e as lesões ocorrem nas áreas fotoexpostas, especialmente a face. Sua patogênese não é bem compreendida e os estudos clássicos avaliam apenas pele acometida e perilesional, mas pouco se sabe do comportamento da pele fotoprotegida, submetida aos mesmos fatores sistêmicos e genéticos. Neste estudo, objetivamos avaliar características histológicas, vias epidérmicas que influem na melanogênese (Wnt e ASIP) e características ultraestruturais da pele com melasma em comparação com a pele sã adjacente e retroauricular. Para a execução deste estudo transversal com controle intra-sujeito, foram coletadas três biópsias cutâneas (punch 3 mm) de onze mulheres com melasma facial. As áreas de coleta foram a pele com melasma, pele sã adjacente (distando no máximo 2 cm do limite da lesão) e pele retroauricular ipsilateral. Os fragmentos provenientes de dez participantes foram corados por hematoxilina-eosina, ácido periódico de Schiff, Fontana-Masson, picrosirius red, azul de toluidina e Verhöff; imunomarcados para CD34 e submetidos à imunofluorescência direta (IFD) de dupla marcação para proteínas Wnt1, WIF-1 e ASIP. Já os três fragmentos de uma das participantes foram processados para Microscopia Eletrônica de Transmissão (MET). Os dados obtidos foram comparados entre as topografias por modelo linear generalizado de efeitos mistos. As participantes eram fototipo III ou IV de Fitzpatrick, com idade média (desvio-padrão) de 42,9 (8,9) anos e apresentavam lesões há 16,7 (7,9) anos. Houve adelgaçamento da camada córnea na pele com melasma e na pele adjacente. Na pele com melasma houve maior compactação da córnea, maior pigmentação melânica epidérmica, maior heterogeneidade do colágeno, elastose solar, maior número de mastócitos, falhas da integridade da zona da membrana basal, melanócitos em pêndulo, bem como maior celularidade e vasos na derme superficial. IFD evidenciou maior intensidade de marcação de Wnt1 na pele com melasma em relação à pele adjacente e maior intensidade na pele retroauricular em relação à pele sã adjacente. Não houve diferença estatística significativa na intensidade de marcação de WIF-1 e ASIP entre as topografias. À MET, houve maior dano estrutural na lâmina lúcida no melasma, bem como maior número de melanossomas maduros e organelas citoplasmáticas nos melanócitos e queratinócitos basais. Tais resultados evidenciam que a pele com melasma apresenta, além da hipertrofia melanocítica, alterações na barreira epidérmica, na derme superior, zona de membrana basal e maior ativação da via Wnt, que diferem da pele fotoexposta adjacente e da retroauricular, configurando um fenótipo individualizado e não somente uma extensão do fotoenvelhecimento ou do envelhecimento intrínseco.
Melasma is a chronic and acquired hypermelanosis resulting from a complex process which involves melanocytic hypertrophy and melanogenic dysfunction. Melasma mainly affects females and lesions occur in the photoexposed areas, especially the face. Its pathogenesis is not well understood, and classical studies evaluate only the affected and perilesional skin, but little is known about the behavior of the non-sun-exposed skin, subjected to the same systemic and genetic factors. In this study, we aimed to evaluate histological features, epidermal pathways that influence melanogenesis (Wnt and ASIP) and ultrastructural characteristics of the skin with melasma in comparison to healthy adjacent and retroauricular skin. For the execution of this cross-sectional study with intrasubject control, three skin biopsies (punch 3 mm) were collected from eleven women with facial melasma. The areas of collection were the skin with melasma, adjacent healthy skin and retroauricular skin. Fragments from ten participants were stained with hematoxylin-eosin, periodic acid from Schiff, Fontana-Masson, picrosirius red, toluidine blue and Verhöff; immunomarked for CD34 and subjected to double-labeled direct immunofluorescence (DIF) for Wnt1, WIF-1 and ASIP proteins. The three fragments of one of the participants were processed for Transmission Electron Microscopy (TEM). The data obtained were compared between topographies by generalized linear model of mixed effects. Participants were Fitzpatrick's phototype III or IV; the mean age (standard deviation) was 42.9 (8.9) years and they had lesions for 16.7 (7.9) years. There was thinning of the corneal layer on the skin with melasma and adjacent skin. In the skin with melasma, there was more corneal compaction, greater epidermal melanic pigmentation, greater collagen heterogeneity, solar elastosis, more mast cells, defects of the basement membrane area, pendulum melanocytes, as well as greater cellularity and vessels in the superficial dermis. DIF showed a greater intensity of Wnt1 marking in the skin with melasma in relation to the adjacent skin, and greater intensity in the retroauricular skin in relation to the adjacent healthy skin. There was no significant statistical difference in the intensity of WIF-1 and ASIP marking between topographies. At TEM, there was more structural damage to the lamina lucida in melasma, as well as more mature melanosomes and cytoplasmic organelles in melanocytes and basal keratinocytes. These results show that melasma skin presents, in addition to melanocytic hypertrophy, alterations in the epidermal barrier, upper dermis, basement membrane zone and greater activation of the Wnt pathway, which differ from adjacent and retroauricular photoexposed skin, forming an individualized phenotype and not only an extension of photoaging or intrinsic aging.
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Lemos, Ana Cláudia Cavalcante Espósito. "Estudo histomorfométrico, ultraestrutural e da expressão de Wnt1, WIF-1 e ASIP na pele com melasma em comparação com a pele sã perilesional e retroauricular." Botucatu, 2017. http://hdl.handle.net/11449/151232.
Full textAbstract:
Orientador: Hélio Amante MiotResumo: O melasma é hipermelanose crônica e adquirida decorrente de um complexo processo que envolve hipertrofia melanocítica e disfunção melanogênica. Acomete preferencialmente o sexo feminino e as lesões ocorrem nas áreas fotoexpostas, especialmente a face. Sua patogênese não é bem compreendida e os estudos clássicos avaliam apenas pele acometida e perilesional, mas pouco se sabe do comportamento da pele fotoprotegida, submetida aos mesmos fatores sistêmicos e genéticos. Neste estudo, objetivamos avaliar características histológicas, vias epidérmicas que influem na melanogênese (Wnt e ASIP) e características ultraestruturais da pele com melasma em comparação com a pele sã adjacente e retroauricular. Para a execução deste estudo transversal com controle intra-sujeito, foram coletadas três biópsias cutâneas (punch 3 mm) de onze mulheres com melasma facial. As áreas de coleta foram a pele com melasma, pele sã adjacente (distando no máximo 2 cm do limite da lesão) e pele retroauricular ipsilateral. Os fragmentos provenientes de dez participantes foram corados por hematoxilina-eosina, ácido periódico de Schiff, Fontana-Masson, picrosirius red, azul de toluidina e Verhöff; imunomarcados para CD34 e submetidos à imunofluorescência direta (IFD) de dupla marcação para proteínas Wnt1, WIF-1 e ASIP. Já os três fragmentos de uma das participantes foram processados para Microscopia Eletrônica de Transmissão (MET). Os dados obtidos foram comparados entre as topografias por modelo linear generali... (Resumo completo, clicar acesso eletrônico abaixo)
Mestre
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Cheung, Newton Computer Science & Engineering Faculty of Engineering UNSW. "Design automation methodologies for extensible processor platform." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/26118.
Full textAbstract:
This thesis addresses two ubiquitous trends in the embedded system world - the increasing importance of design turnaround time as a design metric, and the move towards closing the design productivity gap. Adopting the right choice of design approach has been recognised as an integral part of the design flow in order to meet desired characteristics such as increasing software content, satisfying the growing complexities of an application, reusing off-the-shelf components, and exploring design metrics tradeoff, which closes the design productivity gap. The importance of design turnaround time is motivated by the intensive competition between manufacturers, especially makers of mainstream electronic consumer products, who shrinks the product life cycle and requires faster time-to-market to maximise economic benefits. This thesis presents a suite of design automation methodologies to automatically design embedded systems for an application in the state-of-the-art design approach - the extensible processor platform. These design automation methodologies systematise the extensible processor platform???s design flow, with particular emphasis on solving four challenging design problems: i) code segment identification; ii) instruction generation; iii) architectural customisation selection; and iv) processor evaluation. Our suite of design automation methodologies includes: i) a semi-automatic design system - to design an extensible processor that maximises the application performance while satisfying the area constraint. By specifying a fitting function to identify suitable code segments within an application, a two-level hierarchy selection algorithm is used to first select a predefined processor and then select the right instruction, and a performance estimator is used to estimate an application's performance; ii) a tool to match instructions - to automatically match the pre-designed instructions with computationally intensive code segments, reducing verification time and effort; iii) an instructions estimation model - to estimate the area overhead, latency, power consumption of extensible instructions, exploring larger design space; and iv) an instructions generation tool - to generate new extensible instructions that maximises the speedup while minimising power dissipation. A number of techniques such as system decomposition, combinational equivalence checking and regression analysis etc., have been heavily relied upon in the creation of the final design system. This thesis shows results at every stage to demonstrate the efficacy of our design methodologies in the creation of extensible processors. The methodologies and results presented in this thesis demonstrate that automating the design process for an extensible processor platform results in significant performance increase - on average, an increase of 4.74x (up to 15.71x) compared to the original base processor. Our system achieves significant design turnaround time savings (2.5% of the full simulation time for the entire design space) with majority Pareto points obtained (91% on average), and can lead to fewer and faster design iterations. Our instruction matching tool is 7.3x faster on average compared to the best known approaches to the problem (partial simulations). Our estimation model has a mean absolute error as small as 3.4% (6.7% max.) for area overhead, 5.9% (9.4% max.) for latency, and 4.2% (7.2% max.) for power consumption, compared to estimation through the time consuming synthesis and simulation steps using commercial tools. Finally, the instruction generation tool reduces energy consumption by a further 5.8% on average (up to 17.7%) compared to extensible instructions generated by previous approaches.
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Engroff, Alian Moreira. "Asipampium: uma ferramenta de desenvolvimento automático de processadores de aplicação específica." Universidade Federal do Pampa, 2017. http://dspace.unipampa.edu.br:8080/jspui/handle/riu/2031.
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Nas ultimas décadas houve um crescimento exponencial no desenvolvimento de sistemas embarcados, que são alocados no mais diversos equipamentos como eletrodomésticos e eletrônicos portáteis. Os sistemas embarcados são compostos por processadores de uso geral ou especıfico, os quais são desenvolvidos para cada sistema, apresentando restrições quanto ao custo de área, consumo de energia e tempo de processamento. Essas restrições dependem da aplicação e das funcionalidades. Dentre vários tipos de metodologias de projeto que buscam atender´ as necessidade de desenvolvimento de processadores para esses equipamentos, destaca-se a metodologia de desenvolvimento ASIP, do inglêsˆ Application Specific Integrated Processor. Os ASIPs são desenvolvidos de forma otimizada para cada aplicação, com um conjunto de instruções, tipos de memoria, quantidade e formas de acesso customizados. No entanto, a otimização do hardware implica em muito esforço para o desenvolvimento do processador. Nesse sentido, e necessário uma plataforma de desenvolvimento automático de ASIPs que analise o programa, as restrições da aplicação, e também forneça suporte a simulação e compilação. Este trabalho tem como objetivo principal elaborar uma ferramenta para o desenvolvimento automático de processadores de aplicação especıfica chamada ASIPAMPIUM, buscando tornar o desenvolvimento de um ASIP fácil e rápido com uma boa relação entre custo de área, consumo de potencia e velocidade de processamento. Para isso, foi proposta uma arquitetura de um processador reconfigurável, chamado PAMPIUM, que e definida como uma arquitetura RISC com 80 instruções, utilizando operações apenas com registradores. Esta arquitetura e utilizada como base para o ASIP, pois ela possui a flexibilidade necessária para se adaptar as características das mais diversas aplicações. A utilização de uma arquitetura base permite que o usuário possa desenvolver ASIPs para as mais variadas aplicações utilizando uma mesma plataforma de desenvolvimento. O processador gerado pelo ASIPAMPIUM e disponível em linguagem de descrição hardware, de forma que possa ser sintetizado para a fabricação de circuitos integrados ou para gravação em FPGA. Para o desenvolvimento do ASIP são utilizadas três versões base do PAMPIUM: monociclo, pipeline e superescalar. Desta forma o processador gerado leva em consideração as principais estatísticas do compilador e do simulador. Para validação a ferramenta ASIPAMPIUM foi utilizada no desenvolvimento de uma FFT e comparadas suas características com outros trabalhos, mostrando uma boa equivalência nos resultados. Também foi desenvolvido um sistema de controle de uma rede de antenas retrodiretivas. Este sistema foi testado e validado em FPGA. Além disso, foi elaborada uma versão do PAMPIUM em silício, denominada PAMPIUM IC, a qual foi prototipada em tecnologia 0 ,18µm da TSMC, testada e validada eletricamente. Estas aplicações demonstram o correto funcionamento da metodologia proposta, gerando hardware de alto desempenho com um curto tempo de desenvolvimento.
In the last years there has been an exponential increase in the development of embedded systems, which are used in the most diverse equipment such as home appliances and portable electronics. Embedded systems are made up of processors of specific or general purpose. Specific processors are developed for each system, with restrictions on area, energy consumption and processing time. These restrictions are depend on the application and the features. Among several types of design methodologies for the development of processors for these equipments, stands out the development methodology for Application Specific Integrated Processors (ASIPs). ASIPs are optimally developed for each application, with a set of instructions, types of memory, quantity and custom access forms. However, the optimization of the hardware implies a lot of effort for the development of the processor. It is also necessary to develop a set of tools, such as compilers and simulators for ASIP. In that sense an automatic ASIP development platform is needed that analyzes the program, the application restrictions, and also provides support for simulation and compilation. This work has as main objective to elaborate a tool for the automatic development of specific application processors called ASIPAMPIUM. This tool seeks to make the development of an ASIP easy and fast, with a good relation between area, power consumption and processing speed. For this, a reconfigurable processor architecture, called PAMPIUM, was proposed, which is defined as a RISC architecture with 80 instructions, using register operations only. This architecture is used as the basis for ASIP, since it has the necessary flexibility to adapt to the characteristics of the most diverse applications. The use of a base architecture allows the user to develop ASIPs for the most varied applications using the same development platform. The processor generated by ASIPAMPIUM is available in hardware description language, so that it can be synthesized for the manufacture of integrated circuits or for FPGA implementation. Three basic versions of PAMPIUM are used: monocycle, pipeline and superscalar. In this way the generated processor takes into account the main compiler and simulator statistics. For validation, the ASIPAMPIUM tool was used in the development of an FFT and compared its characteristics with other works, showing a good equivalence in the results. Also has been developed control system for a retrodirective antennas array. This system has been tested and validated in FPGA. In addition, a version of PAMPIUM in silicon, called PAMPIUM IC, was developed, which was prototyped in TSMC 0 ,18µ technology, tested and validated electrically. These applications demonstrate the correct functioning of the proposed methodology, generating high performance hardware with a short development time.
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Bourgeois, Yann. "Génétique évolutive d'un cas extrême de polymorphisme de la coloration du plumage chez un oiseau insulaire, Zosterops borbonicus (Zosteropideae)." Toulouse 3, 2013. http://www.theses.fr/2013TOU30333.
Full textAbstract:
Les polymorphismes de coloration sont d'un intérêt tout particulier en biologie évolutive. Accessibles, impliqués dans de nombreux processus sélectifs, ils ont grandement contribué à notre compréhension de la mise en place de la diversité biologique. Nous avons étudié un cas de polymorphisme à petite échelle chez Zosterops borbonicus en usant d'approches indirectes de génétique et de génomique. Il apparaît que les changements de couleur ne reposent pas sur des gènes précédemment identifiés comme points chauds évolutifs. Nous identifions également un locus associé à la couleur du plumage sur le chromosome 1 jamais mis en évidence auparavant. De grands effectifs et un flux de gènes limité favorisent l'action de la sélection à petite échelle. Cette étude illustre comment des approches indirectes peuvent permettre d'établir le contexte d'apparition de la diversité phénotypiqueColor polymorphisms are of considerable interest in evolutionary biology. As they are accessible and involved in a variety of selective processes, they have contributed significantly to our understanding of biological diversity. We studied a case of polymorphism at a small spatial scale in Zosterops borbonicus, using indirect approaches such as population genetics and genomics. It appears that coloration changes are not due to genes classically described as 'evolutionary hotspots'. We also identified a locus linked to coloration on chromosome 1. This locus is not yet described as affecting feathers or hair coloration. High effective population sizes and moderate gene flow have probably favored selective effects in shaping this polymorphism. This study illustrates how indirect approaches can allow inferring the context in which phenotypic diversity occurs
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Andriamisaina, Choukataly Caaliph. "Synthèse d'architecture multi-modes pour les applications du traitement du signal et de l'image." Lorient, 2008. http://www.theses.fr/2008LORIS127.
Full textAbstract:
Le marché des télécommunications et du multimédia ne cesse de s’accroître avec une demande de plus en plus forte en fonctionnalité, performance, durée d’autonomie, compacité et faible coût de conception. Ces besoins ont ainsi conduit à des recherches de dispositifs performants, flexibles, compacts et faible consommation. Ainsi, pour avoir un compromis entre la flexibilité et la performance, l’ajout de flexibilité aux architectures matérielles et/ou l’amélioration des performances des architectures logicielles peuvent être envisagés. Cet ajout de flexibilité donne lieu à ce qui est appelé dans la littérature, des architectures multi-modes. Ce type d’architectures est spécialement conçu pour implémenter un ensemble d’applications mutuellement exclusives dans le temps. Les architectures multi-modes sont aussi utilisées pour réduire le surcoût du temps de reconfiguration dans les FPGAs et pour implémenter des accélérateurs de nids de boucles utilisés comme accélérateurs matériels (co-processeurs) ou accélérateurs d’instructions (ASIP). Nous proposons dans cette thèse une méthodologie de conception, basée sur la synthèse de haut niveau (HLS), automatisant la génération d’architectures multi-modes. La synthèse de haut niveau est une technique qui permet une augmentation considérable de la productivité par l’élévation du niveau d’abstraction de la spécification et par l’automatisation de la conception. Dans le contexte de la HLS, nous proposons de modifier les étapes d’allocation, d’ordonnancement et d’assignation dans le but de réduire le coût en surface de l’architecture générée tout en gardant un surcoût en performance et en consommation faible. Pour obtenir une surface totale minimale, nous proposons de diminuer le coût en surface du chemin de données et aussi du contrôleur. La réduction du coût du contrôleur s’obtient grâce à l’augmentation de la similarité des ressources présentes entre les étapes de contrôle des modes. Alors que, la réduction du coût du chemin de données est obtenue grâce essentiellement au partage de ressources entre les modes et à la prise en compte du coût des interconnections lors de ce partage. L'approche que nous proposons a été implémentée dans un environnement de conception dédié à la génération d’architecture multi-modes. Cette suite logicielle s’articule autour des outils : GAUT « Multi-modes », et STARGene « Multi-modes » et permet, en partant d'une description fonctionnelle spécifiée en langage C/C++, d'obtenir automatiquement une architecture multi-modes de niveau transfert de registres décrite en VHDL. Un ensemble d’expériences ont été menés pour mettre en avant l’efficacité de notre approche et les outils associés. De ces expériences, nous avons pu constater qu’avec notre approche, nous arrivions à réduire fortement (jusqu'à 60%) la surface occupée par les différents modes à implémenter tout en ayant un surcoût en performance (en moyenne de 5%) et en consommation (en moyenne de 16%) raisonnableEmerging standards lead an increasing demand for high performance, flexibility and low power of embedded systems. These requirements had led to the research on efficient devices to respect these constraints. To have a good trade-off between flexibility and performance, adding flexibility to dedicated architectures and/or improving software performances can be considered. In the literature, the architectures, which result from the addition of flexibility in dedicated architectures, are named multi-modes architectures. The multi-modes or multi-configurations architectures are specifically designed for a set of time-wise mutually exclusive applications (multi-standard applications). They are also used to reduce the reconfiguration time overhead in FPGAs and to implement loop accelerators. We propose a design methodology, based on the High-Level Synthesis (HLS) technique, dedicated to the multi-modes architectures generation. The high-level synthesis is a technique, which considerably increase the productivity by raising the level of abstraction of the input specification and by automating the design. In the context of HLS, we propose to modify the allocation, scheduling and binding steps in order to reduce the area cost of the generated architecture by limiting the performance and power consumption overhead. In order to obtain an area efficient multi-modes architecture, we propose to reduce the area cost of the datapath and the controller. The controller complexity reduction is obtained by increasing the resources similarity between the control steps of the different modes. Whereas, the datapath complexity reduction is obtained by the resources sharing between the modes, and by the consideration of the interconnections cost during this sharing. This approach was integrated in a design environment, dedicated to the multi-modes architectures generation. This environment is based on different tools: GAUT “Multi-modes”, CDFG2UCOM and STARGene “Multi-modes”. It takes as input a functional description specified in C/C++ language in order to obtain automatically a multi-modes architecture at register transfer level described in VHDL. A set of experiment has been done to show the effectiveness of our approach and its associated high-level synthesis tools. From these experiments, we notice that with our approach, we can greatly reduce (up to 60%) the area occupied by the different modes to implement. With this important area reduction, we also obtain a low performance (average of 5%) and power consumption (average of 16%) overhead
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Carro, Luigi. "Algoritmos e arquiteturas para o desenvolvimento de sistemas computacionais." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1996. http://hdl.handle.net/10183/17780.
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Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida.This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.
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Rochus, Christina. "Diversité génétique du mouton domestique : exemple de populations suédoises et françaises." Thesis, Paris, Institut agronomique, vétérinaire et forestier de France, 2017. http://www.theses.fr/2017IAVF0008.
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Les moutons domestiques sont élevés pour la production de viande, de lait et de laine et sont retrouvés partout dans le monde dans des environnements variés. On a montré que les moutons présentaient une certaine diversité génétique, mais celle-ci n'a pas été complètement caractérisée: il existe encore de nombreuses populations de moutons qui n'ont pas été étudiées. L’objectif de cette thèse était d'étudier la diversité génétique dans des races de moutons suédoises et françaises, en utilisant puces de marqueurs de haute densité. De plus, dans les populations suédoises, d’autres méthodes ont été utilisées: le génotypage de marqueurs microsatellites, de séquences de rétrovirus endogènes et les données de pedigree. Dans la population Gute, l’estimation du niveau de consanguinité et d’'hétérozygotie, en utilisant le pedigree de toute la population suédoise enregistrée, ainsi que le pedigree et des génotypages de microsatellites complémentaires d'un échantillon de la population (N = 94) ont indiqué un schéma de sélection orienté vers une réduction de la consanguinité. L'étude des relations génétiques entre les races grâce au génotypage de rétrovirus endogènes a montré que les races ovines Klövsjö, Värmland, Finewool, Gute et Roslag avaient des caractéristiques de races primitives (absence de rétrovirus ou présence de la séquence rétrovirale spécifique enJSRV-7) tandis que les races ovines Finewool, Gute et Roslag avaient des fréquences modérées de enJSRV-18, ce qui signe des races de moutons plus modernes. L'étude des variants de deux gènes de coloration de la toison, ASIP et MC1R, et leur association avec la couleur noire a révélé différentes histoires de sélection dans cinq races de moutons suédoises étudiées. L'étude de la structure des populations de moutons Dalapäls, Fjällnäs, Gotland, Gute et Klövsjö, grâce au génotypage de puces SNP à haute densité a révélé que ces races sont génétiquement distinctes. Leur comparaison avec d'autres races européennes et des races du Sud-Ouest asiatique les rapproche d'autres races de moutons à queue courte du nord de l'Europe et montre qu’elles ont accumulé plus de dérive génétique que les races provenant d'autres zones géographiques. L'étude de 27 races françaises avec des génotypages de puces à haute densité a révélé que les populations de moutons français abritent une grande partie de la diversité des moutons européens au sein d’une petite région géographique. Les balayages sélectifs ont montré : des points chauds de sélection, des cibles de sélection partagées par de nombreuses espèces, l’introgression d'un allèle adaptatif et une hétérogénéité allélique, qui a été confirmée par le reséquençage ciblé d'un gène de couleur de la toison, MC1R, dans des races sous sélectionDomestic sheep are raised for meat, milk and fibre production and are found all around the world in many types of environments. Sheep have been shown to be genetically diverse but this genetic diversity has not been fully described: there are still many sheep populations which have not yet been studied. The purpose of this thesis was to study genetic diversity in Swedish and French sheep breeds using high density marker arrays. Additional methods, including genotyping of microsatellite markers, and endogenous retroviruses and pedigree information were used to study Swedish sheep populations. Inbreeding and heterozygosity estimated in Gute sheep using the pedigree of the entire registered Swedish population and additionally microsatellite genotypes and pedigree from a sample of the population (N=94) indicated a breeding program with the purpose of reducing inbreeding. Studying genetic relationships among breeds by genotyping endogenous retroviruses indicated Klövsjö, Värmland, Finewool, Gute and Roslag sheep breeds had characteristics of primitive breeds (absence of retroviruses or presence of the specific retrovirus event enJSRV-7) although Finewool, Gute and Roslag sheep breeds had moderate frequencies of enJSRV-18 which is indicative of more modern sheep breeds. Studying variants in two coat colour genes, ASIP and MC1R, and their association with black coat colour revealed different selection histories in five Swedish sheep breeds studied. Studying the population structure of Dalapäls, Fjällnäs, Gotland, Gute and Klövsjö sheep, using high density SNP genotyping revealed that these breeds are genetically distinct breeds. When comparing with other European breeds and south west Asian breeds, they grouped with other north European short-tailed sheep breeds and they had generally accumulated more drift than breeds from other geographical areas. Studying 27 French breeds with high density genotypes revealed that French sheep populations harbour much of European sheep diversity in a small geographic area. Selective sweeps identified: selection hotspots, selection targets in many species; introgression of an adaptive allele; and allelic heterogeneity, which was confirmed with targeted resequencing of a coat colour gene, MC1R, in breeds under selection
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Milliot, David. "Processus ASEM (Asia-Europe meeting) : vers l'émergence du trans-régionalisme Asie-Europe ?" Paris 10, 2003. http://www.theses.fr/2003PA100025.
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Les relations euro-asiatiques ont longtemps été marquées par des rapports inégaux. Il faudra attendre la fin du XXe siècle pour voir disparaitre le déséquilibre historique des relations Europe-Asie. Le lancement de l'ASEM (Asia-Europe Meeting) à Bangkok en 1996 a été le symbole le plus marquant de ce rééquilibrage. Sous-tendue par un mode de fonctionnement original, l'ASEM a créé une dynamique de convergence inscrite dans la durée avec la tenue des Sommets biennaux. Toutefois, son mode de fonctionnement ternaire (politique, économique, culturel) révèle certaines lacunes que les mesures adoptées au Sommet de Copenhague (2002) cherchent à combler. L'ASEM est l'histoire d'une double reconquête : la reconquête de la scène internationale par l'Asie tout d'abord. Pour la première fois, un cadre de dialogue et de coopération avec l'Europe s'inspire, dans son mode de fonctionnement, directement des techniques diplomatiques asiatiques. Face à des contraintes internes et externes de plus en plus lourdes, l'ASEAN a perdu son rôle moteur dans le processus. Dans ce contexte, l'ASEM peut jouer un rôle utile comme espace de dialogue complémentaire aux relations inter-régionales (ASEAN-UE), bilatérales et multilatérales. Dans le même temps, le "recyclage" de l'ASEM permet à l'Asie de développer des relations inédites avec d'autres pôles régionaux. Les fonctions du trans-régionalisme de l'ASEM révèlent également une stratégie de reconquête de la scène internationale par les états. Objet non identifié des relations internationales, le trans-régionalisme de l'ASEM peut répondre à plusieurs types d'interprétation. Les relations trans-régionales sont des outils utiles à l'émergence d'un concept de gouvernance mondiale : elles permettent à la fois le renforcement des relations entre pôles régionaux et à la création d'espaces de dialogue transversaux inédits. Le trans-régionalisme de l'ASEM serait-il le lien manquant entre mondialisation et régionalisation ?The launching of the ASEM process in Bangkok in 1996 was the first step towards a global agenda among two equal partners, Asia and Europe. Supported by specific working procedures and biannual summits, ASEM has created a new dynamic between the two regions. From ASEM I in Bangkok (1996) to ASEM IV in Copenhaguen (2002), ASEM has developed a complete new set of methods of fostering political and economic dialogue as well as functional co-operation. Its working, achievements and shortcomings are analysed. But the key question is : what both partners want to achieve through this process ? First, ASEM aims at increasing the profile of Asia and Europe in international relations. But it also underlines a number of functions which help States managing their bilateral, inter-regional and multilateral affairs. The trans-regionalism of ASEM is in fact an important feature of this new process. As a political and diplomatic process, ASEM is to a large extent more influenced by the informal Asian ways of conducting business than the legalistic European approach. The consequences of the ASEM process on Asian regionalism, especially the building-up of an East-Asian Community, are also to be considered. Whereas Southeast Asia is searching ways to consolidate its position in the context of emerging China and the increasing dynamism of the Indian subcontinent, ASEM provides with new linkages. The role of the ASEM process in the international affairs is not meaningless : it has emerged as being a new layer of co-operation and has created a window of opportunity for fostering new types of co-operation between regions in the world. In fact, ASEM has served as a blueprint respectively for Europe and Asia to foster new relations with other regions (Latin America, Africa, Middle East). Hence, it raises the issue of a new global governance in international relations. Will ASEM be the missing link between regionalism and globalization ?
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Martin, Kevin. "Génération automatique d'extensions de jeux d'instructions de processeurs." Phd thesis, Université Rennes 1, 2010. http://tel.archives-ouvertes.fr/tel-00526133.
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Les processeurs à jeux d'instructions spécifiques (ASIP) sont des processeurs spécialisés qui combinent la flexibilité d'un processeur programmable avec la performance d'un processeur dédié. L'une des approches de conception de tels processeurs consiste à spécialiser un cœur de processeur existant en y ajoutant des instructions spécialisées, mises en œuvre dans un module matériel fortement couplé au chemin de données du processeur. C'est l'extension de jeu d'instructions. La conception d'un ASIP nécessite des méthodologies et des outils logiciels appropriés garantissant une maîtrise des contraintes de conception et de la complexité grandissante des applications. Dans ce contexte, cette thèse vise à proposer une méthodologie de génération automatique d'extensions de jeux d'instructions. Celle-ci consiste à tout d'abord identifier l'ensemble des instructions candidates qui satisfont les contraintes architecturales et technologiques, afin de garantir leurs mises en œuvre. Ensuite, les instructions candidates qui minimisent le temps d'exécution séquentielle de l'application sont sélectionnées. Les ressources matérielles de l'extension, telles que les registres et les multiplexeurs, sont optimisées. Enfin, la dernière étape génère la description matérielle et le modèle de simulation de l'extension. Le code applicatif est adapté pour tenir compte des nouvelles instructions. Cette thèse propose des techniques basées sur la programmation par contraintes pour résoudre les problèmes difficiles (voir intraitables) que sont l'identification d'instructions, la sélection d'instructions et l'allocation de registres.
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Janáková, Zuzana. "Čínska soft power v ázijskom regióne." Master's thesis, Vysoká škola ekonomická v Praze, 2009. http://www.nusl.cz/ntk/nusl-16060.
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Within the context of the foreign policy of the People's Republic of China, one hears frequently about Chinese "soft power". This work deals with Chinese soft power in three Asian subregions - Southeast Asia, Japan & South Korea and Central Asia - in order to verify to what extent can soft power be regarded a universal approach in Chinese foreign policy. After introducing the concept of soft power this work is aiming to explain the characteristics of Chinese soft power, define the potentials and limits of Chinese soft power resources and explain how soft power corresponds with China's general strategy of foreign policy. In order to create an image of Chinese soft power in each of the three subregions, I define the key soft power tools according to which I measure Chinese soft power: Bilateral and multilateral diplomacy, promotion of culture and language (mainly through Confucius institutes), education of foreign students at Chinese universities and foreign aid. The rest of work is an analysis of employment of these tools in the respective subregions.
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Floc'h, Antoine. "Compilation optimisante pour processeurs extensibles." Phd thesis, Université Rennes 1, 2012. http://tel.archives-ouvertes.fr/tel-00726420.
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Les processeurs à jeu d'instructions spécifiques (ASIP) constituent un compromis entre les performances d'un circuit matériel dédié et la flexibilité d'un processeur programmable. Ces processeurs spécialisés peuvent être composés d'un processeur généraliste dont le jeu d'instructions est étendu par des instructions spécifiques à une ou plusieurs applications et qui sont exécutées sur une extension matérielle. On parle alors de processeurs extensibles. Si le coût de conception et de vérification de telles architectures est considérablement réduit en comparaison à une conception complète, la complexité est en partie reportée sur l'étape de compilation. En effet, le jeu d'instructions d'un processeur extensible est à la fois une entrée et une sortie du processus de compilation. Cette thèse propose plusieurs contributions pour guider le processus de conception de telles architectures à travers des techniques d'optimisations adaptées aux processeurs extensibles. La première de ces contributions consiste à sélectionner et à ordonnancer les instructions spécialisées VLIW en résolvant un unique problème d'optimisation de programmation par contraintes (CP). D'autre part, nous proposons une technique originale qui traite de l'interaction entre l'optimisation de code et l'extension de jeu d'instructions. Le principe est de transformer automatiquement le code original des nids de boucles d'un programme (à l'aide du modèle polyédrique) afin de sélectionner des instructions spécialisées vectorisables et dont les données temporaires, produites lors d'une itération de boucle, sont mémorisées sur l'extension matérielle du processeur.
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Svoboda, Jan. "ASEAN a perspektivy jeho vnější integrace." Master's thesis, Vysoká škola ekonomická v Praze, 2010. http://www.nusl.cz/ntk/nusl-74029.
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This paper is focused on an analysis of current regionalism in Asia-Pacific region and on evaluation of creation of relatively wide and relatively deep regional integration. Possible benefits of this integration concept can be exemplified by development of Association of South East Asian Nations (ASEAN) whose member states have substantially different interests due to historic and socioeconomic reasons. However, ASEAN was able to overcome these different interests by a specific integration model which is based on mutual trust, consensual decision-making and gradual changes. As a result, natural suspicions were eliminated to some extent and member states were able to deepen their integration. Main powers in the region noticed its success and they began to strive to develop closer relations not only with ASEAN, but also with other regional powers through ASEAN structure.
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Zmijanović, Katarina. "Regionalismus v rozvojové Asii." Master's thesis, Vysoká škola ekonomická v Praze, 2010. http://www.nusl.cz/ntk/nusl-75151.
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The main goal of the thesis is the analysis of regional integrations in developing Asia and their success. The thesis analyses the Association of Southeast Asian Nations, integrations of China with India, Republic of Korea, and Pakistan, and integrations of India with Republic of Korea and Indonesia.
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Pešková, Veronika. "Obchodní vztahy EU s asijskými státy." Master's thesis, Vysoká škola ekonomická v Praze, 2011. http://www.nusl.cz/ntk/nusl-124583.
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The thesis analyzes trade relations between the European Union and Asian countries. The work includes the characteristics of trade in goods and briefly deals also with foreign direct investments and trade in services. The thesis describes the contractual basis for the mutual relations and estimate their future development.
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Regent, Kamil. "Ekonomický rozvoj jihoasijských zemí." Master's thesis, Vysoká škola ekonomická v Praze, 2012. http://www.nusl.cz/ntk/nusl-162795.
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The aim of this work is to verify Rostow's Stages of growth model and the Solow-Swan growth model empirically using statistical data from Asian countries. In the theoretical part ("Teoretická část"), the main characteristics of the Rostow's Stages of growth model and the Solow-Swan growth model are explained. The empirical part ("Empirická část") consists of the empirical verification based on statistical data from a total of 51 Asian countries. This includes 47 independent Asian states, 2 partially recognized states (Palestine and Taiwan) and 2 dependent territories (Hong Kong and Macao). The conclusion is devoted specifically to the People's Republic of China and in particular to the evaluation of its economic development, including efforts to predict future developments in relation to Czech businesses.
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Barták, Jiří. "Model procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255393.
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The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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Revire, Nicolas. "The Enthroned Buddha in Majesty : an Iconological Study." Thesis, Sorbonne Paris Cité, 2016. http://www.theses.fr/2016USPCA157/document.
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Cette thèse étudie en détail un type particulier de représentation du Bouddha où il est représenté assis sur un trône prééminent, le bhadrapīṭha ou bhadrāsana, dans une posture majestueuse avec les deux jambes pendantes, c’est-à-dire assis en bhadrāsana ou dans l’attitude « de bon augure ». Cette iconographie, étroitement associée à l’imagerie du trône, se retrouve largement représentée dans l’art de l’Asie du Sud, de l’Est et du Sud-Est, et est, en règle générale, intimement liée aux modèles de la royauté, de la fertilité, et même du divin. Plusieurs implications notables ressortent de cet examen iconologique concernant les origines, la diffusion, et le développement de l’art bouddhique dans ces contrées, particulièrement au cours du premier millénaire de notre èreThis dissertation provides a detailed study of a particular representation of the Buddha, in which he sits on a prominent throne, i.e. a bhadrapīṭha or bhadrāsana, in a majestic posture with two legs pendant, that is, in bhadrāsana or the “auspicious pose.” This pendant-legged imagery, generally associated with the throne, has been found widely depicted in South, East, and Southeast Asian art and is, as a rule, mostly associated with kingship, fertility, and even divinity. The results of this iconological examination have wide implications for understanding the origins, spread, and development of Buddhist art in those lands, particularly during the first millennium CE
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Konieczná, Ewa. "Politika rozvojové spolupráce EU se zeměmi Jižní a Jihovýchodní Asie." Master's thesis, Vysoká škola ekonomická v Praze, 2011. http://www.nusl.cz/ntk/nusl-85885.
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Since the second half of the 20th century in Asia is evident the emergence of the new centers of economic growth. The success of the Asian newly industrialized countries is followed by different in character but also dynamic development of the Asian newly industrialized countries of the second generation. The growing economic powers in Asia as also in global measures are China and India. The importance of these countries in the context of the global economy will be likely to increase. However, these countries face many typical for developing countries constraints of the economic and social development. This paper describes the European Union's approach to development cooperation with the states of South and Southeast Asia, its application, effectiveness, and in particular the importance of modern optimal growth of these countries for the future of the EU in terms of its growth and sustainable development.
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Petr, Zdeněk. "Dovoz potravin ze států východní Asie." Master's thesis, Vysoká škola ekonomická v Praze, 2015. http://www.nusl.cz/ntk/nusl-205910.
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The diploma thesis deals with the issues linked to transport of foodstuffs from East Asia to Europe. The theoretical part contains a comprehensive overview on international trade with foodstuff and food logistics. The practical part is an analysis of transport process of rice between the two regions.
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Nájera, Rendón Daniel. "Asia Town + Casa Asia Puebla." Thesis, Universidad de las Américas Puebla, 2011. http://catarina.udlap.mx/u_dl_a/tales/documentos/lar/najera_r_d/.
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Hojzáková, Věra. "East Asia's Security System." Master's thesis, Vysoká škola ekonomická v Praze, 2012. http://www.nusl.cz/ntk/nusl-162792.
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The aim of the master thesis is to characterize and evaluate the current security system in East Asia, to show the security strategies of the system actors and the existing friction points, and to assess the future development of the security system in place. For this purpose the author first defines the East Asia's security system using the conceptual tools of three international relations theories, namely neo-realism, neo-liberalism, and constructivism. In the following section, the security strategies and security issues are discussed. In the final section, the international relations theories are used again to assess the stability of the current security system and lastly the prospects for a change of the system are evaluated.