Dissertations / Theses on the topic 'ASIC'
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Lothian, Angus, Ivar Härnqvist, Adam Jakobsson, Arvid Westerlund, Felix Goding, Jacob Wahlman, Kevin Scott, and Rasmus Karlsson. "B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.
Full textArumugam, Prakash. "Investigations into ASIC desensitization." Connect to resource, 2006. http://hdl.handle.net/1811/6036.
Full textTitle from first page of PDF file. Document formattted into pages: contains 16 p.; also includes graphics. Includes bibliographical references (p. 16). Available online via Ohio State University's Knowledge Bank.
Ghuman, Parminder, Salman Sheikh, Steve Koubek, Scott Hoy, and Andrew Gray. "High Rate Digital Demodulator ASIC." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609676.
Full textThe architecture of the High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA’s Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an overview of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.
Ramsten, Johannes, and Markus Klum. "Implementation av fältbuss ASIC i FPGA." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-4523.
Full textHMS Industrial Networks AB is in need of changing a communications solution that iscurrently based on an ASIC. This will be achieved by moving the communications solution toa FPGA with the help of the programming language VHDL. By doing this, it is possible toreduce the need for specific circuits, get a more flexible platform and thus get a cheapersolution.
This report describes a solution for how to move a network protocol from an ASIC to anFPGA. The report shows that the network slave device is working under the guidelines forthis project. This means that it is quite realistic to implement a fieldbus protocol on an FPGA,using VHDL and to maintain the same functionality as the earlier communications solution.
Harrison, Andrew. "ASIC based recorders of electrophysiological signals." Thesis, University of Nottingham, 1995. http://eprints.nottingham.ac.uk/13305/.
Full textDobson, Jonathan M. "ASIC implementations of the Viterbi Algorithm." Thesis, University of Edinburgh, 1999. http://hdl.handle.net/1842/13669.
Full textPerumalla, Anvesh Kumar. "A Genetic Algorithm for ASIC Floorplanning." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.
Full textHoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.
Full textDroste, Dirk. "Realisierung eines Wellenfrontsensors mit einem ASIC." [S.l. : s.n.], 1999. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB8337986.
Full textHussain, Waqar Muhammad. "Low Power Implantable ASIC forBio-Impedance Measurements." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-105098.
Full textKhawaja, Jaleed Ejaz. "Asic gas sensors based on ratiometric principles." Thesis, University of Warwick, 2009. http://wrap.warwick.ac.uk/2230/.
Full textGuzmaÌn, JesuÌs GarciÌa. "Smart ratiometric ASIC chip for VOC monitoring." Thesis, University of Warwick, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422141.
Full textLe, Thai Q. (Thai Quoc) Carleton University Dissertation Engineering Electrical. "Application specific integrated circuit (ASIC) hardwired microcontroller." Ottawa, 1991.
Find full textBryksin, Vladyslav Sergeevich. "ASIC life extension through hardware patch interfaces." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1464873.
Full textTitle from first page of PDF file (viewed July 2, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 46-47).
Paschou, Michail. "ASIC implementation of LSTM neural network algorithm." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254290.
Full textLSTM neurala nätverk har använts för taligenkänning, bildigenkänning och andra artificiella intelligensapplikationer i många år. De flesta applikationer utför LSTM-algoritmen och de nödvändiga beräkningarna i digitala moln. Offline lösningar inkluderar användningen av FPGA och GPU men de mest lovande lösningarna inkluderar ASIC-acceleratorer utformade för endast dettaändamål. Denna rapport presenterar en ASIC-design som kan utföra multipla iterationer av LSTM-algoritmen på en enkelriktad neural nätverksarkitetur utan peepholes. Den föreslagna designed ger aritmetrisk nivå-parallellismalternativ som block som är instansierat baserat på parametrar. Designens inre konstruktion implementerar pipelinerade, parallella, eller seriella lösningar beroende på vilket anternativ som är optimalt till alla fall. Konsekvenserna för dessa beslut diskuteras i detalj i rapporten. Designprocessen beskrivs i detalj och utvärderingen av designen presenteras också för att mäta noggrannheten och felmarginal i designutgången. Resultatet av arbetet från denna rapport är en fullständig syntetiserbar ASIC design som har implementerat ett LSTM-lager, ett fullständigt anslutet lager och ett Softmax-lager som kan utföra klassificering av data baserat på tränade viktmatriser och biasvektorer. Designen använder huvudsakligen 16bitars fast flytpunktsformat med 5 heltal och 11 fraktions bitar men ökade precisionsrepresentationer används i vissa block för att minska felmarginal. Till detta har även en verifieringsmiljö utformats som kan utföra simuleringar, utvärdera designresultatet genom att jämföra det med resultatet som produceras från att utföra samma operationer med 64-bitars flytpunktsprecision på en SystemVerilog testbänk och mäta uppstådda felmarginal. Resultaten avseende noggrannheten och designutgångens felmarginal presenteras i denna rapport.Designen gick genom Logisk och Fysisk syntes och framgångsrikt resulterade i en funktionell nätlista för varje testad konfiguration. Timing, area och effektmätningar på den genererade nätlistorna av olika konfigurationer av designen visar konsistens och rapporteras i denna rapport.
CHENG, WEISHUAI. "Development of ASIC for SiPM sensor readout." Doctoral thesis, Politecnico di Torino, 2020. http://hdl.handle.net/11583/2842529.
Full textMehrez, Fatima. "Design and test of a readout ASIC for a SiPM - based camera : ALPS (ASIC de lecture pour un photodétecteur SiPM)." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT131/document.
Full textThis thesis is the R&D on front-end electronics for a second generation camera based on the SiPM detectors for the Large Size Telescope (LST) of the CTA project. It is a part of the SiPM collaboration involving the LAPP, the University of Padua, the INFN and the MPI in Munich. The first part of the thesis is the characterization of an array of 16 SiPMs from Hamamatsu. The study proves the advantages of using such detectors in the LST. It defines the specifications of the readout electronics that are the aim of this work. Especially that it should ameliorate the gain dispersion of the 16 pixels that was found of about 10%. The second part is the design of the readout ASIC. The scheme tends to measure the SiPMs’ signals with minimum disturbance of the detector. It integrates slow control facilities that adjust the detector’s gain, minimize the dispersion in gain and provide the possibility of deleting noisy channels or even completely jumping over the control process. These facilities could perfectly get rid of the gain dispersion. Outputs of the 16 pixels will be summed on both high gain and low gain so that only two signals are delivered to the acquisition system that follows. A trigger function will also generate a trigger signal to the acquisition system. The choice was made to realize this ASIC according to the rules of the AMS 0.35um BiCMOS technology. Simulation shows a linearly-covered dynamic range up to 2000 photoelectrons with good signal to noise ratio that allows the measurement of the single photoelectron. Laboratory tests confirm a great part of these results
Ehliar, Andreas. "Performance driven FPGA design with an ASIC perspective." Doctoral thesis, Linköpings universitet, Datorteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16372.
Full textSadiq, Ejaz. "Short Message Network-On-Chip Interconnect for ASIC." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175761.
Full textHan, Tony. "SWASAD Smith & Waterman-algorithm-specific ASIC design /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16391.pdf.
Full textDvořák, Vojtěch. "Implementace výpočtu FFT v obvodech FPGA a ASIC." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220087.
Full textDUTTA, MADHULIKA. "DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.
Full textOlsson, Martin. "Portning och utökning av processor för ASIC och FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18250.
Full textIn this master thesis, the possibilities of customizing a low-cost microprocessor with the purpose of replacing an existing microprocessor solution are investigated. A brief survey of suitable processors is carried out wherein a replacement is chosen. The replacement processor is then analyzed and extended with accelerators in order to match set requirements.
The result is a port of the processor Lattice Mico32 for the FPGA curcuit Xilinx Virtex-5 which replaces an earlier solution using Xilinx MicroBlaze. To reach the set requirements, accelerators for floating point arithmetics and FIR filtering have been developed. The toolchain for the processor has been modified to support the addition of accelerated floating point arithmetics.
A final evaluation of the presented solution shows that it fulfills the set requirements and constitutes a functional replacement for the previous solution.
Yesil, Soner. "A High-speed Asic Implementation Of The Rsa Cryptosystem." Master's thesis, METU, 2003. http://etd.lib.metu.edu.tr/upload/3/1124783/index.pdf.
Full textm AMI Semiconductor Standard Cell Libraries. By suiting the design into a systolic and regular architecture, the broadcasting signals and routing delays are minimized in the implementation. With this regular architecture, the results of 3ns clock period (627Kbps) using 87K gates (8.7mm2 with I/O pads) for the 512-bit implementation, and 4ns clock period (237Kps) using 132K gates (10.4mm2 with I/O pads) for the 1024-bit implementation have been achieved. These results are obtained for the worst-case conditions and they include the post-layout routing delays. The design is also verified in real time using the Xilinx V2000E FPGA on the Celoxica RC1000 Hardware. The 1024-bit VLSI implementation has been sent to IMEC for fabrication as a prototype chip through Europractice Multi-Project Wafer (MPW) runs.
Venditti, Michael B. "Receiver, transmitter, and ASIC design for optoelectronic-VLSI applications." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84444.
Full textThe design of receivers, transmitters, and OE-VLSI application-specific integrated circuits (ASICs) are described from a system implementation perspective. Numerous techniques to overcome technological problems and allow the successful operation of large receiver and transmitter arrays are considered. The use of a fully differential optical and electrical architecture is strongly advocated. The testing of receiver and transmitter circuits and skew in highly parallel and synchronous digital systems employing optical receivers is also considered.
The major portion of this thesis details the design, construction, and optical and electrical testing of two OE-VLSI ASICs. The experiences obtained during the design and test of these ASICs, in conjunction with further analytical and simulation-based analyses, resulted in the conclusion that a fully differential optical and electrical architecture is optimal for OE-VLSI applications. The remainder of the thesis considers receiver and transmitter testing and the integration of testing methodologies at the ASIC level, and the management of skew in large receiver arrays.
Simpson, Zachary P. "Optimization of RSA Cryptography for FPGA and ASIC Applications." Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1609146/.
Full textZuo, Yongbo. "Fair Comparison of ASIC Performance for SHA-3 Finalists." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/33446.
Full textMaster of Science
Gilda, Shubham. "ASIC design to monitor current for low frequency applications." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1291390501.
Full textKUGATHASAN, RAMSHAN. "Low-Power Mixed-Signal ASIC for Cryogenic SiPM Readout." Doctoral thesis, Politecnico di Torino, 2020. http://hdl.handle.net/11583/2842523.
Full textSuikkanen, E. (Essi). "Detection algorithms and ASIC designs for MIMO–OFDM downlink receivers." Doctoral thesis, Oulun yliopisto, 2017. http://urn.fi/urn:isbn:9789526215013.
Full textTiivistelmä Tulevaisuuden langattomat tietoliikennejärjestelmät edellyttävät suurta datanopeutta ja vähäistä tehonkulutusta datan lähetyksessä ja käsittelyssä. Monitulo-monilähtötekniikan (MIMO) ja monikantoaaltomoduloinnin (OFDM) yhdistelmä (MIMO–OFDM) on lupaava lähestymistapa hyvän suorituskyvyn saavuttamiseksi, sekä kapasiteetin että luotettavuuden kannalta. Yksi langattoman vastaanottimen eniten tehoa kuluttavista osista on ilmaisin. Tehonkulutuksen minimoimiseksi tulisi ilmaisimen pystyä vaihtamaan ilmaisinalgoritmia radiokanavan olosuhteisiin sopivaksi. Tässä väitöskirjatyössä tarkastellaan erilaisten MIMO-ilmaisinalgoritmien sopivuutta mukautuvaan ilmaisuun. Listapalloilmaisimen (list sphere detector, LSD), valikoivan laajennuksen listailmaisimen (selective spanning with fast enumeration, SSFE), lineaarisen pienimmän keskineliövirheen ilmaisimen (linear minimum mean square error, LMMSE) ja peräkkäisen häiriönpoistoilmaisimen (successive interference cancellation, SIC) suorituskykyjä verrataan toisiinsa sekä 4 × 4 että 8 × 8 MIMO–OFDM järjestelmissä. Pienimmän neliösumman (LS) ja pienimmän keskineliövirheen (MMSE) kanavaestimointialgoritmien, vastaanottimen nopeuden ja lähetyksen esikoodauksen vaikutus ilmaisinalgoritmin valintaan otetaan huomioon vertailussa. Haastavissa kanavaolosuhteissa SIC-ilmaisin kärsii virheen etenemisestä. SSFE-ilmaisimen suorituskyky on huonompi kuin K-best LSD-ilmaisimen, ja joissakin tilanteissa huonompi kuin LMMSE-ilmaisimen. LMMSE-ilmaisin pystyy parempaan suorituskykyyn kuin K-best LSD-ilmaisin kun signaali-kohinasuhde (SNR) on pieni, vastaanottimen nopeus on suuri ja radiokanavan korrelaatio on matala tai kohtalainen. LMMSE-ilmaisin myös kestää epätarkat kanavaestimaatit paremmin kuin LSD-ilmaisin. Realistisessa vastaanottimessa mukautuva ilmaisin tukee vain kahta ilmaisinalgoritmia, ja sen takia K-best LSD and LMMSE-ilmaisimet valittiin suorituskykytulosten perusteella toteutettaviksi ASIC-teknologialla. Valittuja ilmaisinalgoritmeja arvioidaan sekä suorituskyvyn että toteutustulosten perusteella. K-best LSD-ilmaisimella on hyvä suorituskyky haastavissa kanavaolosuhteissa, mutta toteutus on monimutkainen ja tehonkulutus korkea. LMMSE-ilmaisin on energiatehokas, mutta suorituskyky on huono korreloivissa kanavissa. Poikkeuksia näihin tilanteisiin kuitenkin esiintyy, ja työssä esitetään suositus milloin yksinkertaista ilmaisinta voidaan käyttää tehonkulutuksen minimoimiseksi ja milloin taas monimutkainen ilmaisin on välttämätön luotettavan tiedonsiirron takaamiseksi
Dulipovici, Andrei. "Signatures des circuits ASIC - approche pour détermination des pannes systématiques." Mémoire, École de technologie supérieure, 2011. http://espace.etsmtl.ca/886/1/DULIPOVICI_Andrei.pdf.
Full textMurphy, Julian. "Standard cell and full custom power-balanced logic : ASIC implementation." Thesis, University of Newcastle Upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.533690.
Full textAuras, Dominik [Verfasser], Gerd [Akademischer Betreuer] Ascheid, and Andreas [Akademischer Betreuer] Burg. "MIMO Detector ASIC Design / Dominik Auras ; Gerd Ascheid, Andreas Burg." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/116249963X/34.
Full textNygård, Skalman Jonas. "CO2 Sensor Core on FPGA : ASIC prototyping and cost estimates." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-35963.
Full textGreen, Forrest Oliver Reece. "ALA ASIC : a standard cell library for Asynchronous Logic Automata." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61160.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 83-84).
This thesis demonstrates a hardware library with related tools and designs for Asynchronous Logic Automata (ALA) gates in a generic 90nm process development kit that allows a direct one-to-one mapping from software to hardware. Included are basic design tools to enable writing ALA software, the necessary hardware designs for implementation, and simulation techniques for quickly verifying correctness and performance. This thesis also documents many of the hazards and opportunities for improving them including helpful variations to the ALA model, design tool needs, better simulation models, and hardware improvements. To embody software you could compile a hardware description language to an FPGA or synthesize it all the way to transistors. Alternatively, you could use your favorite high level language and run it on a standard processor. However, the widening gap between traditional models of computation and the reality of the underlying hardware has led to massive costs for design and fabrication as well as numerous issues for scalability and portability. Unlike any of these other approaches, ALA aligns computational and physical descriptions making it possible to use a direct one-to-one mapping to convert an ALA program to a circuit or other physical artifact that executes that program. No unpredictable fitters or compilers are needed and no extra expertise is needed for specific technologies. Similar to Mead-Conway design rules ALA designs trade flexibility for portability and ease of design. Unlike Mead- Conway design rules, ALA designs do not require any further verification-the design rule primitives are logical operations suitable for use in analysis at the algorithmic level. ALA separates many of the scaling issues that plague integrated circuit design by cleanly separating algorithm design from hardware engineering-improving design verification, tape-out costs (by reusing masks), yield, portability, and the ability to break designs across multiple chips. ALA designs are not limited to integrated circuits and could just as easily be implemented in microfluidics, magnetic logic, or a lattice of molecular logic gates. Although each of these technologies would require implementing a basic set of gates and tiling rules, hardware (or equivalently software) can be developed using the same deterministic noiseless digital abstraction using the same design in many different technologies.
by Forrest Oliver Reece Green.
M.Eng.
Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.
Full textLin, Cheng-Hsien Kenny. "An ASIC application for DNA sequencing by Smith-Waterman algorithm (DNASSWA) /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe18716.pdf.
Full textMahnke, Torsten. "Low power ASIC design using voltage scaling at the logic level." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=970311974.
Full textDemirci, Kemal Safak. "Chemical microsystem based on integration of resonant microsensor and CMOS ASIC." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41182.
Full textMcIntosh, James Alexander. "Implementation of an ASIC for detector instrumentation in nuclear physics applications." Thesis, University of Edinburgh, 1996. http://hdl.handle.net/1842/1781.
Full textMcMahon, Michael, Albert Rhoads, Frank Winter, and Graham Pierson. "A VERSATILE PROGRAMMABLE FUNCTION RF ASIC FOR SPACE-BASED RF SYSTEMS." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608302.
Full textA programmable RF ASIC is described which provides most of the RF functions within a next generation S-band transponder for space applications. The unique 18-contact LCC device can be programmed to perform a variety of RF and analog functions. This single space qualified high speed bipolar "function toolbox" is used in 39 locations throughout the transponder to provide a flexible radio architecture. The ASIC design process, internal electrical design, circuit application, space environment performance, and RF testing of the RF ASIC are described. This proprietary part provides a space-qualified solution for RF circuitry that can be applied to a variety of space application products.
Ke, Chen-Maih, and 柯清邁. "ASIC implementationof DCT." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/95414103571037761257.
Full text義守大學
電子工程學系
88
With the significant property of high signal density, discrete cosine transform (DCT) has been applied in many fields of digital signal processing. The design of the DCT or IDCT chips need to consider several important factors such as the chip area, running frequency and delay time. In this paper, we develop an architectures for DCT computation and compared with architectures that other authors presented before. The ASIC implementation for these DCT architectures is carry out by using Verilog hardware description language to synthesis the cell-based and an Altera Flex 10 k chip.
Adarsha, Rao S. J. "Polymorphic ASIC : For Video Decoding." Thesis, 2013. http://etd.iisc.ac.in/handle/2005/3291.
Full textAdarsha, Rao S. J. "Polymorphic ASIC : For Video Decoding." Thesis, 2013. http://hdl.handle.net/2005/3291.
Full text邱志豪. "An Economic Evaluator for ASIC Development." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/51823616215903670442.
Full text中華大學
電機工程研究所
86
Cost, quality, and time to market are the basic constraints of any design project. The costs developing a ASIC include design costs, production costs, and test costs. Costs of components are sensitive to competition. For example, changing cost by $1 may change list price by $3~$4. Without understanding the relationship of cost to list price the component designer may not understand the impact on list price of adding, deleting, or replacing components. The feature of eletronic products is high volume and short lifetime. The short lifetimes have made it increasingly important to get new products to market on time. If we are late to market we will have less time to sell our product. As a result we will sell less, we will make less profit and we may also lose market share. Thus, design schedule is a key factor in developing a new product or component. The traditional way of reducing schedules through increase in team size is ineffective an costly. But, sometime we must adopt this way to get new product to market earlier in order to make more profit. In this text we present a economic evaluator to facilitate the prediction of all costs influenced by the ASIC development. The cost model is integrated with a market model to evaluate the influence of a late project. The evaluator is intended for use by ASIC designers and project leaders, and the analysis can help when decisions about design schedule and costs need to be made for a project.
Philipp, Torsten Scarbata Gerd. "Layoutsynthese von Datenwegstrukturen für den ASIC-Entwurf /." 1991. http://www.gbv.de/dms/ilmenau/toc/019694709.PDF.
Full textHe, Yi-Ru, and 何宜儒. "Buffer Insertion for ASIC and FPGA Designs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/51612808809154222102.
Full text國立清華大學
資訊工程學系
95
With the technology process going into nanometer regime, the interconnect delay is a crucial determining factor of circuit performance in modern VSLI designs. Buffer insertion is one of the effective technique to improve the circuit performance. We explore two different problems related to buffer insertion in ASIC and FPGA designs in this thesis. In modern ASIC designs, a large number of buffers need to be inserted to a large number of nets to improve performance and/or signal integrity. These buffers increase the power consumption and occupy silicon area. So it is important to avoid over-buffering. Buffering spaces are more limited in the denser regions of a layout. Thus it is also necessary to reserve the more premium buffering spaces in the denser regions until they are absolutely needed during physical synthesis. We present a buffer insertion algorithm with consideration of both power dissipation and design density under a given timing constraint for ASIC designs. We propose two formulations for this multi-objective problem and a heuristic solver using Lagrangian relaxation technique. In FPGAs, signals passing through a long wire do not always exit at the end of the wire. Therefore, the expected delay other than end to end delay of the long wire should be optimized. We adopt a dynamic programming based approach to insert buffers to minimize the expected delay for FPGA designs and a Lagrangian relaxation based method to achieve low power and timing closure. Experiments for ASIC buffering show that our method can significantly improve the overall design density while achieving low power to obtain better timing closure. The experiments for FPGA buffering show that our method can improve the expected delay by up to 17% compared to the buffered interconnect which only considers end to end delay optimization.
Mlynek, Mario Beierke Stefan. "Entwicklung und Validierung von ASIC-Testsystemen am Beispiel eines zu entwickelnden Rapid Prototyping Testsystems für einen RFIDAutomotive Reader ASIC /." 2008. http://www.gbv.de/dms/ilmenau/abs/564558451mlyne.txt.
Full textYu, Zhengtao. "Rotary clock based high-frequency ASIC design methodology." 2007. http://www.lib.ncsu.edu/theses/available/etd-10252007-214239/.
Full textHsiao, Yi-Mao, and 蕭詣懋. "High Speed ASIC Design for IPv6 Routing Lookup." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/29901660472776506666.
Full text國立中正大學
電機工程所
94
For the IP-based network today, there are three main issues of router design— link speed, router performance, and routing lookup. Routing lookup is a bottleneck inside a router. With the growth of Internet users and services, IP address has been exhaustedly used. In order to solve this problem of exhaustion, the quick solution like CIDR is presented, and the future will be IPv6. In this paper, a routing lookup system for IPv6 is presented. The system is composed of routing lookup ASIC and off-chip memory set. The off-chip memory set is a two-level hierarchical memory architecture. 91.89% routing entries of the routing table can be searched in one memory access, and the worst case about 10% in this system is two-memory accesses .The ASIC includes a function unit and a Binary CAM . The Binary CAM is used as cache memory with FIFO replacement algorithm .There are 1024 cache entries in the CAM with 80% hit ratio. The routing lookup system approaches 160Mlps (81.92Gb/s), and now it has overwhelmed the basic necessity. In the future, the bigger requirement will be available. In the system, routing table only needs 20.04KB TCAM, 10.24KB BCAM, and 29.29MB SRAM for a 150000 entries.