Journal articles on the topic 'ASIC semiconductor'
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FIJALKOWSKI, BOGDAN T., and JAN W. KROSNICKI. "CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS." Journal of Circuits, Systems and Computers 04, no. 04 (December 1994): 501–16. http://dx.doi.org/10.1142/s0218126694000296.
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Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.
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FITRIO, DAVID, SUHARDI TJOA, ANAND MOHAN, RONNY VELJANOVSKI, ANDREW BERRY, and GORAN PANJKOVIC. "A CMOS ANALOG INTEGRATED CIRCUIT FOR PIXEL X-RAY DETECTOR." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 71–87. http://dx.doi.org/10.1142/s0218126611007086.
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A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.
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Qi, Min, An-qiang Guo, and Dong-hai Qiao. "A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers." Sensors 20, no. 1 (December 31, 2019): 241. http://dx.doi.org/10.3390/s20010241.
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This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.
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Andorno, M., M. Andersen, G. Borghello, A. Caratelli, D. Ceresa, J. Dhaliwal, K. Kloukinas, and R. Pejasinovic. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.
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Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.
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Liu, Yu-Sian, and Kuei-Ann Wen. "Implementation of a CMOS/MEMS Accelerometer with ASIC Processes." Micromachines 10, no. 1 (January 12, 2019): 50. http://dx.doi.org/10.3390/mi10010050.
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This paper presents the design, simulation and mechanical characterization of a newly proposed complementary metal-oxide semiconductor (CMOS)/micro-electromechanical system (MEMS) accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. An approximate analytical model for the spring design is presented. The experiments showed that the resonant frequency of the proposed tri-axis accelerometer was around 5.35 kHz for out-plane vibration. The tri-axis accelerometer had an area of 1096 μm × 1256 μm.
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Bonnefoy, J. P., D. Lattard, F. Mathy, J. L. Martin, R. Poujois, J. P. Rostaing, Ph Trystram, and J. Crétolle. "A novel ASIC for readout electronics in semiconductor γ-ray detection." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 380, no. 1-2 (October 1996): 342–45. http://dx.doi.org/10.1016/s0168-9002(96)00382-8.
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Anghinolfi, F., W. Bialas, N. Busek, A. Ciocio, D. Cosgrove, V. Fadeyev, C. Flacco, et al. "ASIC wafer test system for the ATLAS Semiconductor Tracker front-end chip." IEEE Transactions on Nuclear Science 49, no. 3 (June 2002): 1080–85. http://dx.doi.org/10.1109/tns.2002.1039618.
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Kim, Taehoon, Fabian Fool, Djalma Simoes dos Santos, Zu-Yao Chang, Emile Noothout, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, and Michiel A. P. Pertijs. "Design of an Ultrasound Transceiver ASIC with a Switching-Artifact Reduction Technique for 3D Carotid Artery Imaging." Sensors 21, no. 1 (December 29, 2020): 150. http://dx.doi.org/10.3390/s21010150.
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This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.
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Mertol, A. "Optimization of Extruded Type External Heat Sink for Multichip Module." Journal of Electronic Packaging 115, no. 4 (December 1, 1993): 440–44. http://dx.doi.org/10.1115/1.2909354.
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A three-dimensional finite element model of a multichip module (MCM) has been developed by using ANSYS™ finite element simulation code. The model has been used for thermal characterization of the module. In addition, optimum dimensions of an external heat sink, which maintains the specified device’s junction temperature within desired operating temperature limits, are determined as functions of air flow rate and power density of surrounding semiconductor devices. Parametric studies have been performed to study the effects of heat sink height, width and length on junction-to-ambient thermal resistance of a high power application specific integrated circuit (ASIC) device found in the MCM assembly. A set of curves are generated to select either heat sink dimensions or air speed for a given design requirements. Influence of the power output of surrounding devices on the thermal performance of the high power ASIC device is also assessed. The predicted results indicate that the ASIC device’s junction temperature as well as junction-to-ambient resistance increase as the power of the surrounding packages increases. This effect diminishes if a sufficiently large heat sink is used to cool the package.
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Anghinolfi, F., W. Dabrowski, E. Delagnes, J. Kaplon, U. Koetz, P. Jarron, F. Lugiez, C. Posch, S. Roe, and P. Weilhammer. "SCTA-a rad-hard BiCMOS analogue readout ASIC for the ATLAS Semiconductor Tracker." IEEE Transactions on Nuclear Science 44, no. 3 (June 1997): 298–302. http://dx.doi.org/10.1109/23.603659.
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Lv, Risheng, Qiang Fu, Liang Yin, Yuan Gao, Wei Bai, Wenbo Zhang, Yufeng Zhang, Weiping Chen, and Xiaowei Liu. "An Interface ASIC for MEMS Vibratory Gyroscopes with Nonlinear Driving Control." Micromachines 10, no. 4 (April 22, 2019): 270. http://dx.doi.org/10.3390/mi10040270.
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This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm2. Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.
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Vandermeulen, Mark, Andrew Smith, and Ron Csermak. "A Novel Approach to 3D Chip Stacking." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 000797–816. http://dx.doi.org/10.4071/2011dpc-tp14.
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Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures. A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market. This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.
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Benz, Jason, William Bentley, and Joseph Myers. "Selective Dielectric Removal for Failure Analysis of Thin Films on Semiconductor Devices." EDFA Technical Articles 11, no. 2 (May 1, 2009): 23–29. http://dx.doi.org/10.31399/asm.edfa.2009-2.p023.
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Abstract Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.
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Lv, Risheng, Qiang Fu, Weiping Chen, Liang Yin, Xiaowei Liu, and Yufeng Zhang. "A Digital Interface ASIC for Triple-Axis MEMS Vibratory Gyroscopes." Sensors 20, no. 19 (September 23, 2020): 5460. http://dx.doi.org/10.3390/s20195460.
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This paper proposes a solution for sensing spatial angular velocity. A high-performance digital interface application specific integrated circuit (ASIC) for triple-axis micro-electromechanical systems (MEMS) vibratory gyroscopes is presented. The technique of time multiplexing is employed for synergetic stable drive control and precise angular velocity measurement in three separate degrees of freedom (DOF). Self-excited digital closed loop drives the proof mass in sensing elements at its inherent resonant frequency for Coriolis force generation during angular rotation. The analog front ends in both drive and sense loops are comprised of low-noise charge-voltage (C/V) converters and multi-channel incremental zoom analog-to-digital converters (ADC), so that capacitance variation between combs induced by mechanical motion is transformed into digital voltage signals. Other circuitry elements, such as loop controlling and accurate demodulation modules, are all implemented in digital logics. Automatic amplitude stabilization is mainly realized by peak detection and proportion-integration (PI) control. Nonlinear digital gain adjustment is designed for rapid establishment of resonance oscillation and linearity improvement. Manufactured in a standard 0.35-μm complementary metal-oxide-semiconductor (CMOS) technology, this design achieves a bias instability of 2.1°/h and a nonlinearity of 0.012% over full-scale range.
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Pan, James N. "Optoelectronic CMOS Transistors: Performance Advantages for Sub-7nm ULSI, RF ASIC, Memories, and Power MOSFETs." MRS Advances 4, no. 48 (2019): 2585–91. http://dx.doi.org/10.1557/adv.2019.211.
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AbstractSubstantial increase of output current, and Ion / Ioff ratio for sub-7nm low power CMOS transistors, can be accomplished using a novel optoelectronic technology, which is 100% compatible with existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower Rdson and high voltage at the same time. For semiconductor memories, such as DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.
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Li, Xiangyu, Yangong Zheng, Xiangyan Kong, Yupeng Liu, and Danling Tang. "Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC." Sensors 20, no. 24 (December 18, 2020): 7280. http://dx.doi.org/10.3390/s20247280.
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High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.
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Baudin, D., O. Limousin, O. Gevin, A. Meuris, K. Altenmuller, P. Bausson, F. Ceraudo, et al. "IDeF-X HDBD: Low-Noise ASIC for Imaging Spectroscopy With Semiconductor Detectors in Space Science Applications." IEEE Transactions on Nuclear Science 69, no. 3 (March 2022): 620–26. http://dx.doi.org/10.1109/tns.2022.3144464.
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Lin, Chih-Hsuan, Chao-Hung Song, and Kuei-Ann Wen. "Multi-Function Microelectromechanical Systems Implementation with an ASIC Compatible CMOS 0.18 μm Process." Micromachines 12, no. 3 (March 17, 2021): 314. http://dx.doi.org/10.3390/mi12030314.
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A multi-function microelectromechanical system (MEMS) with a three-axis magnetometer (MAG) and three-axis accelerometer (ACC) function was implemented with an application-specific integrated circuit (ASIC)-compatible complementary metal-oxide-semiconductor (CMOS) 0.18 μm process. The readout circuit used the nested chopper, correlated double-sampling (CDS), noise reduction method; the frequency division multiplexing method; the time-division multiplexing method; and the calibration method. Sensing was performed by exciting the MEMS three-axis magnetometer at X/Y/Z axes mechanical resonant frequencies of 3.77/7.05/7.47 kHz, respectively. A modest die-level vacuum packaging resulted in in-plane and out-of-plane mechanical quality factors of 471–500 and 971–1000, respectively. The sensitivities of both the three-axis magnetometer with 2 mA driving current and the three-axis accelerometer were 7.1–10.7 uV/uT and 58.37–88.87 uV/ug. The resolutions of both the three-axis magnetometer with 2 mA driving current and three-axis accelerometer resolution were 44.06–87.46 nT/√Hz and 5.043–7.5 ng/√Hz. The resolution was limited by circuit noise equivalent acceleration (CNEM) and Brownian noise equivalent magnetic field (BNEM).
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Wang, Li, Hui-Bin Tao, Hang Dong, Zhi-Biao Shao, and Fei Wang. "A Non-Linear Temperature Compensation Model for Improving the Measurement Accuracy of an Inductive Proximity Sensor and Its Application-Specific Integrated Circuit Implementation." Sensors 20, no. 17 (September 3, 2020): 5010. http://dx.doi.org/10.3390/s20175010.
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The non-linear characteristic of a non-contacting Inductive Proximity Sensor (IPS) with the temperature affects the computation accuracy when measuring the target distance in real time. The linear model based method for distance estimation shows a large deviation at a low temperature. Accordingly, this paper presents a non-linear measurement model, which computes the target distance accurately in real time within a wide temperature range from −55 °C to 125 °C. By revisiting the temperature effect on the IPS system, this paper considers the non-linear characteristic of the IPS measurement system due to the change of temperature. The proposed model adopts a non-linear polynomial algorithm rather than the simple linear Look-Up Table (LUT) method, which provides more accurate distance estimation compared to the previous work. The introduced model is fabricated in a 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process and packaged in a CQFN40. For the most commonly used sensing distance of 4 mm, the computed distance deviation of the Application-Specific Integrated Circuit (ASIC) chips falls within the range of [−0.2,0.2] mm. According to the test results of the ASIC chips, this non-linear temperature compensation model successfully achieves real-time and high-accuracy computation within a wide temperature range with low hardware resource consumption.
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Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Hardware Optimized and Error Reduced Approximate Adder." Electronics 8, no. 11 (October 24, 2019): 1212. http://dx.doi.org/10.3390/electronics8111212.
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This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.
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Campabadal, F., C. Fleta, M. Key, M. Lozano, C. Martinez, G. Pellegrini, J. M. Rafi, et al. "Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 552, no. 3 (November 2005): 292–328. http://dx.doi.org/10.1016/j.nima.2005.07.002.
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Liang, Victor, Harlan Sur, and Subhas Bothra. "Case History: Passive Voltage Contrast Technique for In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS." EDFA Technical Articles 1, no. 3 (August 1, 1999): 19–30. http://dx.doi.org/10.31399/asm.edfa.1999-3.p019.
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Abstract Passive voltage contrast (PVC) has traditionally been used by semiconductor engineers for end-of-line post-mortem analysis. PVC distinguishes between open and short structures and is both nondestructive and noncontact. When applied during process development for in-line characterization, it allows wafers to be examined at multiple points, where electrical probing might not be feasible. This provides feedback on the cumulative effect of the process on critical parameters such as oxide integrity and can reduce development cycle times because wafers do not have to be deprocessed in order to determine the exact location of failures. Two case studies are presented in this article, demonstrating the use of PVC in a process development environment.
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Chen, Po-Chou, Shu-Mei Chang, Hao-Chung Kuo, Fu-Cheng Chang, Yu-An Li, and Chao-Cheng Ting. "Reliability Enhancement of 14 nm HPC ASIC Using Al2O3 Thin Film Coated with Room-Temperature Atomic Layer Deposition." Coatings 12, no. 9 (September 7, 2022): 1308. http://dx.doi.org/10.3390/coatings12091308.
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In this research, a 14 nm high-performance computing application-specific integrated circuit was coated with a 5–20 nm Al2O3 thin film by atomic layer deposition in room-temperature conditions to study its performance in terms of reliability with different thicknesses. An open/short test, standby current measurement, interface input/output performance test, and phase-locked loops functional test were used to verify chip performance. Furthermore, an unbiased highly accelerated temperature and humidity stress test and a 72 h wear-out test were used to study the effects of the atomic layer deposition coating. The results showed that the coating thickness of 15 nm provided the best performance in the wear-out test, as well as the unbiased highly accelerated temperature humidity stress. This study demonstrates that room-temperature atomic layer deposition is a promising technique for enhancing the reliability of advanced node semiconductor chips.
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Denoyelle, Dirk. "Up Close: The Interuniversity Microelectronics Center (IMEC), Leuven, Belgium." MRS Bulletin 14, no. 6 (June 1989): 35–38. http://dx.doi.org/10.1557/s0883769400062692.
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The Interuniversity Microelectronics Center, Leuven, Belgium (IMEC) is one of the world's largest independent research centers for microelectronics. It was established in 1984 by the Flemish government as a part of a comprehensive program to promote high technology in Flanders, Belgium. Benefiting from existing experience available mainly at the University of Leuven, IMEC moved into its present facilities in 1986 (Figure 1).The Center covers a wide range of research topics in the microelectronics domain—VLSI systems design methodologies, advanced semiconductor processing, materials, packaging, and more.About 50 people work on computer-aided design, developing a series of “true” silicon compilers: CATHEDRAL. With this software, ASIC (application specific integrated circuit) design becomes extremely attractive, since CATHEDRAL covers design from the high system level down to layout.INVOMEC, the training division of IMEC, supports universities in ASIC design. It trains people for both educational institutes and industry in chip design, makes available the necessary software, and has a well-established Multi Project Chip—Multi Project Wafer service.The Processing Technologies and Materials Divisions involve about 200 people and have a 3,600 m2 clean room at their disposal. The clean room consists of a 20% class 10 area with a fast-turnaround prototyping line and an 80% class 1000 area.IMEC's objectives are: to perform research in the microelectronics field, supporting both industry and universities, and to stimulate the microelectronics industry in Flanders.IMEC performs research on both silicon and III-V technologies.
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Balasubramanian, Padmanabhan, Raunaq Nayar, and Douglas L. Maskell. "Digital Image Compression Using Approximate Addition." Electronics 11, no. 9 (April 25, 2022): 1361. http://dx.doi.org/10.3390/electronics11091361.
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This paper analyzes the usefulness of approximate addition for digital image compression. Discrete Cosine Transform (DCT) is an important operation in digital image compression. We used accurate addition and approximate addition individually while calculating the DCT to perform image compression. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders individually. The accurate adder and approximate adders were implemented in an application specific integrated circuit (ASIC)-type design environment using a 32–28 nm complementary metal oxide semiconductor (CMOS) standard cell library and in a field programmable gate array (FPGA)-based design environment using a Xilinx Artix-7 device. Error analysis was performed to calculate the error parameters of various approximate adders by applying one million random input vectors. It is observed that the approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design parameters compared to the accurate adder. For an ASIC-type implementation using standard cells, an optimum approximate adder achieved 27.1% reduction in delay, 46.4% reduction in area, and 50.3% reduction in power compared to a high-speed accurate carry look-ahead adder. With respect to an FPGA-based implementation, an optimum approximate adder achieved 8% reduction in delay and 19.7% reduction in power while requiring 47.6% fewer look-up tables (LUTs) and 42.2% fewer flip-flops compared to the native accurate FPGA adder.
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Balasubramanian, Padmanabhan, Raunaq Nayar, and Douglas L. Maskell. "Digital Image Compression Using Approximate Addition." Electronics 11, no. 9 (April 25, 2022): 1361. http://dx.doi.org/10.3390/electronics11091361.
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This paper analyzes the usefulness of approximate addition for digital image compression. Discrete Cosine Transform (DCT) is an important operation in digital image compression. We used accurate addition and approximate addition individually while calculating the DCT to perform image compression. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders individually. The accurate adder and approximate adders were implemented in an application specific integrated circuit (ASIC)-type design environment using a 32–28 nm complementary metal oxide semiconductor (CMOS) standard cell library and in a field programmable gate array (FPGA)-based design environment using a Xilinx Artix-7 device. Error analysis was performed to calculate the error parameters of various approximate adders by applying one million random input vectors. It is observed that the approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design parameters compared to the accurate adder. For an ASIC-type implementation using standard cells, an optimum approximate adder achieved 27.1% reduction in delay, 46.4% reduction in area, and 50.3% reduction in power compared to a high-speed accurate carry look-ahead adder. With respect to an FPGA-based implementation, an optimum approximate adder achieved 8% reduction in delay and 19.7% reduction in power while requiring 47.6% fewer look-up tables (LUTs) and 42.2% fewer flip-flops compared to the native accurate FPGA adder.
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Grout, Ian A., Muhaned Zaidi, Karel L. Sterckx, and Abu Khari Bin A'ain. "RGB LED Driver Circuit Design for an Optical Fiber Sensor System." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 11, no. 2 (December 11, 2017): 163–77. http://dx.doi.org/10.37936/ecti-cit.2017112.63707.
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In this paper, the design of a programmable mixed-signal electronic circuit to control the light output of a red-green-blue (RGB) light emitting diode (LED) to be used in an optical fiber sensor system is presented and discussed. The LED is to be used as a light transmitter (light source) within the sensor system. The output of each LED color is to be independently controlled using either a d.c. current or a pulse width modulation (PWM) encoded current. The idea for, and architecture of, the mixed-signal electronic circuit design is considered as both a discrete implementation using off-the-shelf components and the concept for an application specific integrated circuit (ASIC) solution using a 0.35 µm complementary metal oxide semiconductor (CMOS) fabrication process. In this paper, the design operation principles, circuit architecture, simulation results and hardware requirements for this LED driver circuit are considered.
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Marantis, Alexandros, and on Behalf of the ATLAS Collaboration. "The ATLAS Fast TracKer—Architecture, Status and High-Level Data Quality Monitoring Framework." Universe 5, no. 1 (January 16, 2019): 32. http://dx.doi.org/10.3390/universe5010032.
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The Fast Tracker (FTK) is a highly parallel processor dedicated to a quick and efficient reconstruction of tracks in the Pixel and Semiconductor Tracker (SCT) detectors of the ATLAS experiment at LHC. It is designed to identify charged particle tracks with transverse momentum above 1 GeV and reconstruct their parameters at an event rate of up to 100 kHz. The average latency of the processing is below 100 μs at the expected collision intensities. This performance is achieved by using custom ASIC chips with associative memory for pattern matching, while modern FPGAs calculate the track parameters. This paper describes the architecture, the current status and a High-Level Data Quality Monitoring framework of the FTK system. This monitoring framework provides an online comparison of the FTK hardware output with the FTK functional simulation, which is run on the pixel and SCT detector data at a low rate, allowing the detection of non-expected outputs of the FTK system.
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Ali, Md Liakot, Md Ismail Hossain, and Fakir Sharif Hossain. "Area efficient camouflaging technique for securing IC reverse engineering." PLOS ONE 16, no. 11 (November 4, 2021): e0257679. http://dx.doi.org/10.1371/journal.pone.0257679.
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Reverse engineering is a burning issue in Integrated Circuit (IC) design and manufacturing. In the semiconductor industry, it results in a revenue loss of billions of dollars every year. In this work, an area efficient, high-performance IC camouflaging technique is proposed at the physical design level to combat the integrated circuit’s reverse engineering. An attacker may not identify various logic gates in the layout due to similar image output. In addition, a dummy or true contact-based technique is implemented for optimum outcomes. A library of gates is proposed that contains the various camouflaged primitive gates developed by a combination of using the metal routing technique along with the dummy contact technique. This work shows the superiority of the proposed technique’s performance matrix with those of existing works regarding resource burden, area, and delay. The proposed library is expected to make open source to help ASIC designers secure IC design and save colossal revenue loss.
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Chiu, Yihsiang, Chen Wang, Dan Gong, Nan Li, Shenglin Ma, and Yufeng Jin. "A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs." Micromachines 12, no. 3 (March 8, 2021): 284. http://dx.doi.org/10.3390/mi12030284.
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This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.
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Massin, Loïc, Cyril Lahuec, Fabrice Seguin, Vincent Nourrit, and Jean-Louis de Bougrenet de la Tocnaye. "Multipurpose Bio-Monitored Integrated Circuit in a Contact Lens Eye-Tracker." Sensors 22, no. 2 (January 13, 2022): 595. http://dx.doi.org/10.3390/s22020595.
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We present the design, fabrication, and test of a multipurpose integrated circuit (Application Specific Integrated Circuit) in AMS 0.35 µm Complementary Metal Oxide Semiconductor technology. This circuit is embedded in a scleral contact lens, combined with photodiodes enabling the gaze direction detection when illuminated and wirelessly powered by an eyewear. The gaze direction is determined by means of a centroid computation from the measured photocurrents. The ASIC is used simultaneously to detect specific eye blinking sequences to validate target designations, for instance. Experimental measurements and validation are performed on a scleral contact lens prototype integrating four infrared photodiodes, mounted on a mock-up eyeball, and combined with an artificial eyelid. The eye-tracker has an accuracy of 0.2°, i.e., 2.5 times better than current mobile video-based eye-trackers, and is robust with respect to process variations, operating time, and supply voltage. Variations of the computed gaze direction transmitted to the eyewear, when the eyelid moves, are detected and can be interpreted as commands based on blink duration or using blinks alternation on both eyes.
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Tamburrino, A., G. Claps, F. Cordella, F. Murtas, and D. Pacella. "Timepix3 detector for measuring radon decay products." Journal of Instrumentation 17, no. 06 (June 1, 2022): P06009. http://dx.doi.org/10.1088/1748-0221/17/06/p06009.
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Abstract The present work is focused on the characterization of a Timepix3 (TPX3) based test system for the identification of particles produced by the complex decay chain of 222Rn. The detector used is composed of a pixelated Cadmium Telluride (CdTe) semiconductor (500 μm thick) bump-bonded on an ASIC TPX3 chip. Measurements were carried out at the NIXT Laboratory (ENEA Frascati) using radioactive sources and exploiting the presence of natural radon gas by collecting its decay products on the sensor surface. Estimation of the radon gas risk is one of the most important problems in radiation protection and has stimulated further development of new advanced methods suitable for detecting this gas in confined environments. A study of the spatial uniformity and high energy calibration is also presented and an improved cluster analysis is introduced. The performance highlighted in this study will allow a detailed and faster analysis of the radon products and may have an important impact on the environmental radioprotection applications. This paper describes the application and use of this test system to identify the different decay signatures and follow the temporal evolution of the Radon decay chain.
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Oancea, C., C. Bălan, J. Pivec, C. Granja, J. Jakubek, D. Chvatil, V. Olsansky, and V. Chiș. "Stray radiation produced in FLASH electron beams characterized by the MiniPIX Timepix3 Flex detector." Journal of Instrumentation 17, no. 01 (January 1, 2022): C01003. http://dx.doi.org/10.1088/1748-0221/17/01/c01003.
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Abstract This work aims to characterize ultra-high dose rate pulses (UHDpulse) electron beams using the hybrid semiconductor pixel detector. The Timepix3 (TPX3) ASIC chip was used to measure the composition, spatial, time, and spectral characteristics of the secondary radiation fields from pulsed 15–23 MeV electron beams. The challenge is to develop a single compact detector that could extract spectrometric and dosimetric information on such high flux short-pulsed fields. For secondary beam measurements, PMMA plates of 1 and 8 cm thickness were placed in front of the electron beam, with a pulse duration of 3.5 µs. Timepix3 detectors with silicon sensors of 100 and 500 µm thickness were placed on a shifting stage allowing for data acquisition at various lateral positions to the beam axis. The use of the detector in FLEXI configuration enables suitable measurements in-situ and minimal self-shielding. Preliminary results highlight both the technique and the detector’s ability to measure individual UHDpulses of electron beams delivered in short pulses. In addition, the use of the two signal chains per-pixel enables the estimation of particle flux and the scattered dose rates (DRs) at various distances from the beam core, in mixed radiation fields.
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Vikram, Abhishek, and Vineeta Agarwal. "Patterning approach for detecting defect in device manufacturing." Физика и техника полупроводников 51, no. 12 (2017): 1716. http://dx.doi.org/10.21883/ftp.2017.12.45192.8203.
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Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication --- optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron- beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper. DOI: 10.21883/FTP.2017.12.45192.8203
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Zamora, Iván, Eyglis Ledesma, Arantxa Uranga, and Núria Barniol. "Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays." Sensors 20, no. 4 (February 22, 2020): 1205. http://dx.doi.org/10.3390/s20041205.
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This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.
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Pan, J., S. Afroz, N. Crain, W. Henning, J. Oliver, and T. Knight. "Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC." MRS Advances 4, no. 44-45 (2019): 2377–82. http://dx.doi.org/10.1557/adv.2019.224.
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AbstractIn this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.
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Johannsen, Lucas, Claus Kestel, Oliver Griebel, Timo Vogt, and Norbert Wehn. "Partial Order-Based Decoding of Rate-1 Nodes in Fast Simplified Successive-Cancellation List Decoders for Polar Codes." Electronics 11, no. 4 (February 12, 2022): 560. http://dx.doi.org/10.3390/electronics11040560.
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Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. The decoding of Rate-1 nodes belongs to the most complex tasks in SCL decoding. In this paper, we present a new algorithm that largely reduces the number of considered candidates in a Rate-1 node and generate all required candidates in parallel. For this purpose, we use a partial order of the candidate paths to prove that only a specified number of candidates needs to be considered. Further complexity reductions are achieved by an extended threshold-based path exclusion scheme at the cost of negligible error-correction performance loss. We present detailed Application-Specific Integrated Circuit (ASIC) implementation data on a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide-Semiconductor (CMOS) technology for decoders with code length 128. We show that the new decoders outperform state-of-the-art reference decoders. For list size 8, improvements of up to 158.8% and 62.5% in area and energy efficiency are observed, respectively.
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Bhowmik, Pankaj, Md Jubaer Hossain Pantho, and Christophe Bobda. "HARP: Hierarchical Attention Oriented Region-Based Processing for High-Performance Computation in Vision Sensor." Sensors 21, no. 5 (March 4, 2021): 1757. http://dx.doi.org/10.3390/s21051757.
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Cameras are widely adopted for high image quality with the rapid advancement of complementary metal-oxide-semiconductor (CMOS) image sensors while offloading vision applications’ computation to the cloud. It raises concern for time-critical applications such as autonomous driving, surveillance, and defense systems since moving pixels from the sensor’s focal plane are expensive. This paper presents a hardware architecture for smart cameras that understands the salient regions from an image frame and then performs high-level inference computation for sensor-level information creation instead of transporting raw pixels. A visual attention-oriented computational strategy helps to filter a significant amount of redundant spatiotemporal data collected at the focal plane. A computationally expensive learning model is then applied to the interesting regions of the image. The hierarchical processing in the pixels’ data path demonstrates a bottom-up architecture with massive parallelism and gives high throughput by exploiting the large bandwidth available at the image source. We prototype the model in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) for integrating with a pixel-parallel image sensor. The experiment results show that our approach achieves significant speedup while in certain conditions exhibits up to 45% more energy efficiency with the attention-oriented processing. Although there is an area overhead for inheriting attention-oriented processing, the achieved performance based on energy consumption, latency, and memory utilization overcomes that limitation.
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Granja, C., J. Jakubek, P. Soukup, M. Jakubek, D. Turecek, L. Marek, S. Polansky, et al. "Spectral and directional sensitive composition characterization of mixed-radiation fields with the miniaturized radiation camera MiniPIX Timepix2." Journal of Instrumentation 17, no. 11 (November 1, 2022): C11014. http://dx.doi.org/10.1088/1748-0221/17/11/c11014.
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Abstract The semiconductor pixel detector Timepix2 is operated with highly integrated readout electronics as a miniaturized and portable MiniPIX TPX2 radiation camera for radiation imaging and spectral-sensitive particle tracking in wide field-of-view. The device provides room-temperature operation, ease of use (single USB 2.0 port), online response with single track visualization, fast frame readout (up to 60 fps) and double per-pixel response for detailed measurements with per-pixel energy and counting or energy and timing sensitivity. We evaluate the response and applicability of a MiniPIX TPX2 camera with the Timepix2 ASIC chip equipped with a 300 µm thick silicon sensor for wide-range composition and spectral characterization of mixed-radiation fields. Measurements were performed in high-energy proton radiotherapy environments with protons of selected energies in the range 225–70 MeV and water-equivalent targets of varying configuration (size, dimension, geometry). High-resolution pattern recognition and spectral-tracking analysis of the single particle tracks in the pixelated detector enable to resolve and classify all detected signals according particle species, direction and energy loss. Based on the experimental calibrations performed with well-defined radiation fields together with quantum imaging visualization of single particle tracks, ten broad-range particle-event classes are resolved. Mixed-radiation fields are thus analyzed according particle-event types in wide range of deposited energy, linear-energy-transfer LET, particle fluxes and dose rates. The spatial distribution over the detector sensor matrix of the distinguished groups can be visualized as well as the directional mapping of energetic charged particles.
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Ma, C., X. Zhao, S. Gao, F. Zhang, G. Wu, X. Li, L. Yu, L. Lu, H. Ye, and H. Qian. "An FPGA Based energy correction method for one-to-one coupled PET detector: model and evaluation." Journal of Instrumentation 17, no. 01 (January 1, 2022): T01003. http://dx.doi.org/10.1088/1748-0221/17/01/t01003.
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Abstract A PET scanner based on silicon photomultipliers (SiPMs) has been widely used as an advanced nuclear medicine imaging technique that yields quantitative images of regional in vivo biology and biochemistry. The compact size of the SiPM allows direct one-to-one coupling between the scintillation crystal and the photosensor, yielding better timing and energy resolutions than the light sharing methods that have to be used in photomultiplier tube (PMT) PET systems. To decrease the volume of readout electronics, a front-end multiplexer with position decoder is a common choice for the one-to-one system without a highly integrated application specific integrated circuit (ASIC). However, in this case we cannot measure each crystal's deposited energy inspired by an annihilation photon, so the inter-crystal scatter (ICS) events will lead to the crystal mispositioning and then deteriorate the detector intrinsic resolution. Besides, considering the events rejection within the energy window resulting from the gain dispersion and non-linear outputs of the SiPMs, an energy correction mechanism is needed. Yet, lack of the information of each crystal's energy will introduce large energy correction error for the ICS events. For this issue, an online energy correction mechanism implemented on a Kintext-7 Field Programmable Gate Array (FPGA) device is presented in this paper. Experiments in the laboratory were performed using an 8 × 8 segmented LYSO crystals coupled with an 8 × 8 SiPM (J-series, from ON Semiconductor) array which is under 22Na point source excitation. Test results indicate that both the energy of the non-ICS and ICS events can be precisely corrected and the energy resolution is better than 12 %. We also applied this method to an actual clinical PET scanner under a 68Ge line source to verify its multi-channel reliability.
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Riches, S. T., I. White, G. Rickard, and G. Chadwick. "Implementation of Silicon-on-Insulator (SOI) Control Electronics to Accelerometers for High Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000233–37. http://dx.doi.org/10.4071/hiten-paper5-sriches.
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The requirement to install control systems integrated with sensors in high temperature environments has posed a challenge to the traditional limit of 125°C for conventional electronics. There is a need to operate at temperatures of 200°C and above in restricted space for example in down-well, aero-engine or geothermal applications in combination with high pressures, vibrations and potentially corrosive environments. Piezo-electric accelerometers based on ferro-electric ceramics have been used in a wide range of applications for measuring vibrations, fluid flow and turbulence and are capable of operating as a transducer alone at temperatures up to 250°C, which has made them attractive in sensing applications for down-well drilling and aero-engine health and usage monitoring. However, the electronics traditionally used to carry out the signal conditioning and processing (e.g. charge to voltage conversion, filtering) has been limited to a qualification limit of 125°C, which results in a reduced sensitivity of the transducer output as the signal conditioning and processing cannot be performed close to the sensor. With the development of Silicon-On-Insulator (SOI) semiconductor technology, which can operate at temperatures of up to 250°C, many of the signal conditioning and processing operations can be carried out in-situ with the accelerometers to create a new generation of high temperature products. In addition, the integration of many of the functions that used to require discrete components into one SOI based device has led to further miniaturisation opportunities and a protection against obsolescence of specialist analogue devices. This paper will describe the migration of the traditional low temperature electronics to a high temperature SOI based ASIC device and the implementation of high temperature electronics packaging technology to instrumentation for piezo-electric accelerometers, leading to products that are suitable for high temperature monitoring in restricted spaces in down-well drilling and aero-engine applications.
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Di Patrizio Stanchieri, Guido, Andrea De Marcellis, Marco Faccio, Elia Palange, Graziano Battisti, and Ulkuhan Guler. "A 180 nm CMOS Integrated Optoelectronic Sensing System for Biomedical Applications." Electronics 11, no. 23 (November 29, 2022): 3952. http://dx.doi.org/10.3390/electronics11233952.
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This paper reports on a CMOS fully integrated optoelectronic sensing system composed of a Si photodiode and a transimpedance amplifier acting as the electronic analog front-end for the conditioning of the photocurrent generated by the photodiode. The proposed device has been specifically designed and fabricated for wearable/portable/implantable biomedical applications. The massive employment of sensor systems in different industrial and medical fields requires the development of small sensing devices that, together with suitable electronic analog front ends, must be designed to be integrated into proper standard CMOS technologies. Concerning biomedical applications, these devices must be as small as possible, making them non-invasive, comfortable tools for patients and operating with a reduced supply voltage and power consumption. In this sense, optoelectronic solutions composed of a semiconductor light source and a photodiode fulfill these requirements while also ensuring high compatibility with biological tissues. The reported optoelectronic sensing system is implemented and fabricated in TSMC 180 nm integrated CMOS technology and combines a Si photodiode based on a PNP junction with a Si area of 0.01 mm2 and a transimpedance amplifier designed at a transistor level requiring a Si area of 0.002 mm2 capable to manage up to nanoampere input currents generated by the photodiode. The transimpedance amplifier is powered at a 1.8 V single supply showing a maximum power consumption of about 54 μW, providing a high transimpedance gain that is tunable up to 123 dBΩ with an associated bandwidth of about 500 kHz. The paper reports on both the working principle of the developed ASIC and the experimental measurements for its full electrical and optoelectronic characterizations. Moreover, as case-examples of biomedical applications, the proposed integrated sensing system has also been validated through the optical detection of emulated standard electrocardiography and photoplethysmography signal patterns.
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Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "Quasi-Delay-Insensitive Implementation of Approximate Addition." Symmetry 12, no. 11 (November 20, 2020): 1919. http://dx.doi.org/10.3390/sym12111919.
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Asynchronous quasi-delay-insensitive (QDI) implementation of approximate addition is described in this article. The objective is to provide an insight into the optimization in design metrics that can be achieved with approximate addition compared to accurate addition based on a QDI implementation by considering a practical digital image processing application. For the QDI implementation, some approximate adder architectures are considered which are deemed suitable for both ASIC and FPGA based implementations. The accurate and approximate adders considered are of size 32-bits. The delay-insensitive dual-rail code was used for data encoding, and four-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols were used separately for data communication. The implementations used a 32/28-nm complementary metal oxide semiconductor (CMOS) technology. The simulation results show that an approximate adder HOERAA achieves a 19.7% reduction in cycle time, a 12.5% reduction in area, and an 17.7% reduction in energy compared to the accurate adder for RTZ handshaking. For RTO handshaking, HOERAA achieves an 18.7% reduction in cycle time, a 12.4% reduction in area, and a 16.6% reduction in energy compared to the accurate adder. Another approximate adder HEAA achieves a 19.7% reduction in cycle time, a 12.9% reduction in area, and a 20.2% reduction in energy, compared to the accurate adder for RTZ handshaking. For RTO handshaking, HEAA achieves an 18.7% reduction in cycle time, a 12.9% reduction in area, and a 19.2% reduction in energy compared to the accurate adder. Nevertheless, the RTO handshaking is preferable to RTZ handshaking as the former facilitates slightly better optimizations in design metrics compared to the latter. The mean absolute error (MAE) and the root mean square error (RMSE), which are popular error metrics used in approximate computing, were calculated for the approximate adders and are given for a comparison. While the MAE of HOERAA and HEAA are comparable, HOERAA has 8.6% reduced RMSE compared to HEAA. Digital image processing results based on accurate and approximate additions are also given, to substantiate the usefulness of approximate addition.
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Jérôme, Folla Kamdem, Wembe Tafo Evariste, Essimbi Zobo Bernard, Maria Liz Crespo, Andres Cicuttin, Mamun Bin Ibne Reaz, and Mohammad Arif Sobhan Bhuiyan. "An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors." Sensors 21, no. 5 (March 4, 2021): 1760. http://dx.doi.org/10.3390/s21051760.
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The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.
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Olsansky, V., C. Granja, C. Oancea, A. Mackova, V. Havranek, D. Chvatil, and J. Bila. "Spectral-sensitive proton radiography of thin samples with the pixel detector Timepix3." Journal of Instrumentation 17, no. 04 (April 1, 2022): C04016. http://dx.doi.org/10.1088/1748-0221/17/04/c04016.
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Abstract We evaluate a high-resolution contrast-enhanced method for energy-sensitive radiography of thin samples with low-energy protons at the light-ion Tandetron accelerator of the NPI-CAS in Rez near Prague. We make use of the high-sensitivity of the hybrid semiconductor pixel detectors Timepix enabled by integrated per-pixel signal processing electronics. For this work we use the Timepix3 ASIC chip equipped with a 500 µm Si sensor operated with the fast data rate AdvaPix readout electronics interface. Measurements are performed in air with a 2.9 MeV proton microbeam on thin samples (<100 µm thick). As referential and testing sample we use a set of aluminum foils stacked into a closely packed assembly of varying layers of well-defined thickness. This and other samples were imaged and placed in front of the detector in transmission geometry. Radiographies were collected with focused beam (few mm size) and a microbeam (few µm size). The imaging principle is based on high-resolution spectrometry of single transmitted particles. Contrast is obtained by registration of small differences in the deposited energy of the proton after passing through the sample. This can be measured in wide-range by detailed spectral-tracking analysis of the pixelated clusters in the pixel detector. We examine and evaluate various cluster-track parameters sensitive for imaging contrast such as deposited energy, cluster area (number of pixels) and cluster height (maximum energy value of the pixels in the cluster). The position of interaction in the detector is registered in sub-pixel resolution down to few µm scale for the particles and geometry used. Radiographies are reconstructed based on these individual parameters imaged in image bins of adjustable size (few µm up to few tens of µm). The technique developed with different cluster parameters is presented together with evaluation of image contrast sensitivity on various types of samples and beam energies.
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Ryndin, E. A., N. V. Andreeva, V. V. Luchinin, K. S. Goncharov, and V. S. Raiimzhonov. "Neuromorphic Functional Modules of Spiking Neural Network." Nano- i Mikrosistemnaya Tehnika 23, no. 6 (December 23, 2021): 317–26. http://dx.doi.org/10.17587/nmst.23.317-326.
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In the current era, design and development of artificial neural networks exploiting the architecture of the human brain have evolved rapidly. Artificial neural networks effectively solve a wide range of common for artificial intelligence tasks involving data classification and recognition, prediction, forecasting and adaptive control of object behavior. Biologically inspired underlying principles of ANN operation have certain advantages over the conventional von Neumann architecture including unsupervised learning, architectural flexibility and adaptability to environmental change and high performance under significantly reduced power consumption due to heavy parallel and asynchronous data processing. In this paper, we present the circuit design of main functional blocks (neurons and synapses) intended for hardware implementation of a perceptron-based feedforward spiking neural network. As the third generation of artificial neural networks, spiking neural networks perform data processing utilizing spikes, which are discrete events (or functions) that take place at points in time. Neurons in spiking neural networks initiate precisely timing spikes and communicate with each other via spikes transmitted through synaptic connections or synapses with adaptable scalable weight. One of the prospective approach to emulate the synaptic behavior in hardware implemented spiking neural networks is to use non-volatile memory devices with analog conduction modulation (or memristive structures). Here we propose a circuit design for functional analogues of memristive structure to mimic a synaptic plasticity, pre- and postsynaptic neurons which could be used for developing circuit design of spiking neural network architectures with different training algorithms including spike-timing dependent plasticity learning rule. Two different circuits of electronic synapse were developed. The first one is an analog synapse with photoresistive optocoupler used to ensure the tunable conductivity for synaptic plasticity emulation. While the second one is a digital synapse, in which the synaptic weight is stored in a digital code with its direct conversion into conductivity (without digital-to-analog converter andphotoresistive optocoupler). The results of the prototyping of developed circuits for electronic analogues of synapses, pre- and postsynaptic neurons and the study of transient processes are presented. The developed approach could provide a basis for ASIC design of spiking neural networks based on CMOS (complementary metal oxide semiconductor) design technology.
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Holmes, Jim, A. Matthew Francis, Ian Getreu, and Michael Glover. "A Unified ASIC and LTCC Module Design Kit for High-Temperature High-Density Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, CICMT (May 1, 2016): 000169–72. http://dx.doi.org/10.4071/2016cicmt-wp43.
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Abstract State of the art high temperature ASIC design requires the complement of high temperature modules and circuit boards. Certain LTCC tape systems have coefficients of thermal expansion that are well matched to advanced high temperature semiconductors such as SiC, making them an attractive option for low to mid-volume high temperature products. A computer aided process design kit that supports unified design of high temperature SiC ASICs and the corresponding LTCC module is presented herein. The CAD tools used in the design kit are open source and include basic features such as schematic capture layout drafting, design rule checking, and schematic to layout equivalency checking. In addition, advanced features are included such as automatic routing, automatic pad frame generation, and parasitic extraction for high-fidelity simulation. The kit also allows for the generation of a 3D mock-up rendering of the ASIC and LTCC co-design. Most importantly, pattern file generation for ASIC and LTCC manufacturing data formats is supported. Revision control is also easily accomplished, making collaboration within large design teams tractable. A 12-Volt high-temperature amplifier design using a SiC ASIC process and a compatible LTCC process is presented as a case study.
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Rothrock, Stephen M. "Coronavirus, chip boom, and supply shortage: The new normal for global semiconductor manufacturing." International Symposium on Microelectronics 2021, no. 1 (October 1, 2021): 000026–30. http://dx.doi.org/10.4071/1085-8024-2021.1.000026.
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Abstract Over the past 50 years, the semiconductor industry has faced its fair share of difficult challenges. The COVID-19 pandemic the world is currently experiencing has caused the worst downturn since the financial crisis of 2008, devastating global economies. And yet, the semiconductor industry has repeatedly shown incredible resilience in the face of adversity. Despite the pandemic, the market has not experienced such a dramatic upturn since 2003 and as a result, the new market upturn breaks open the fundamental flaws and risks of manufacturing concentration and outsourcing. At a time when the world is precariously dependent on Taiwan for semiconductors, how can the global supply chain forecast, manage, and plan for such sudden shifts in the future? Now more than ever before, advanced technology companies need to keep the finger on the pulse of supply and demand to successfully inform their strategic manufacturing decisions and remain agile to ensure continuity of supply. As chip demand booms in the midst of a supply shortage over the coming months and supply is no longer a given, what does the future hold for manufacturing fabs? Will greenfield become the rule rather than the exception in this new normal? How will the market upturn impact global fab location choices? Reflecting on some 20 years of experience completing international semiconductor manufacturing asset transactions in North America, Europe, and Asia, ATREG Founder, President, and CEO Stephen M. Rothrock will provide insights into the current global manufacturing asset market and how it is likely to evolve as part of the current market upturn.
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Chen, Jianhua, Kun Yang, Xin Zhou, and Xugang Guo. "Ladder-Type Heteroarene-Based Organic Semiconductors." Chemistry - An Asian Journal 13, no. 18 (August 8, 2018): 2587–600. http://dx.doi.org/10.1002/asia.201800860.
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Zaitsev, Kirill V., Viktor A. Tafeenko, Yuri F. Oprunenko, Anastasia V. Kharcheva, Zhaisan Zhanabil, Yerlan Suleimen, Kevin Lam, et al. "Molecular Oligogermanes and Related Compounds: Structure, Optical and Semiconductor Properties." Chemistry - An Asian Journal 12, no. 11 (February 28, 2017): 1240–49. http://dx.doi.org/10.1002/asia.201700151.
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