Relevant bibliographies by topics / ASIC semiconductor

Academic literature on the topic 'ASIC semiconductor'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "ASIC semiconductor"

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FIJALKOWSKI, BOGDAN T., and JAN W. KROSNICKI. "CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS." Journal of Circuits, Systems and Computers 04, no. 04 (December 1994): 501–16. http://dx.doi.org/10.1142/s0218126694000296.

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Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.
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FITRIO, DAVID, SUHARDI TJOA, ANAND MOHAN, RONNY VELJANOVSKI, ANDREW BERRY, and GORAN PANJKOVIC. "A CMOS ANALOG INTEGRATED CIRCUIT FOR PIXEL X-RAY DETECTOR." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 71–87. http://dx.doi.org/10.1142/s0218126611007086.

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A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.
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Qi, Min, An-qiang Guo, and Dong-hai Qiao. "A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers." Sensors 20, no. 1 (December 31, 2019): 241. http://dx.doi.org/10.3390/s20010241.

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This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.
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Andorno, M., M. Andersen, G. Borghello, A. Caratelli, D. Ceresa, J. Dhaliwal, K. Kloukinas, and R. Pejasinovic. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.

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Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.
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Liu, Yu-Sian, and Kuei-Ann Wen. "Implementation of a CMOS/MEMS Accelerometer with ASIC Processes." Micromachines 10, no. 1 (January 12, 2019): 50. http://dx.doi.org/10.3390/mi10010050.

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This paper presents the design, simulation and mechanical characterization of a newly proposed complementary metal-oxide semiconductor (CMOS)/micro-electromechanical system (MEMS) accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. An approximate analytical model for the spring design is presented. The experiments showed that the resonant frequency of the proposed tri-axis accelerometer was around 5.35 kHz for out-plane vibration. The tri-axis accelerometer had an area of 1096 μm × 1256 μm.
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Bonnefoy, J. P., D. Lattard, F. Mathy, J. L. Martin, R. Poujois, J. P. Rostaing, Ph Trystram, and J. Crétolle. "A novel ASIC for readout electronics in semiconductor γ-ray detection." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 380, no. 1-2 (October 1996): 342–45. http://dx.doi.org/10.1016/s0168-9002(96)00382-8.

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Anghinolfi, F., W. Bialas, N. Busek, A. Ciocio, D. Cosgrove, V. Fadeyev, C. Flacco, et al. "ASIC wafer test system for the ATLAS Semiconductor Tracker front-end chip." IEEE Transactions on Nuclear Science 49, no. 3 (June 2002): 1080–85. http://dx.doi.org/10.1109/tns.2002.1039618.

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Kim, Taehoon, Fabian Fool, Djalma Simoes dos Santos, Zu-Yao Chang, Emile Noothout, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, and Michiel A. P. Pertijs. "Design of an Ultrasound Transceiver ASIC with a Switching-Artifact Reduction Technique for 3D Carotid Artery Imaging." Sensors 21, no. 1 (December 29, 2020): 150. http://dx.doi.org/10.3390/s21010150.

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This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.
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Mertol, A. "Optimization of Extruded Type External Heat Sink for Multichip Module." Journal of Electronic Packaging 115, no. 4 (December 1, 1993): 440–44. http://dx.doi.org/10.1115/1.2909354.

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A three-dimensional finite element model of a multichip module (MCM) has been developed by using ANSYS™ finite element simulation code. The model has been used for thermal characterization of the module. In addition, optimum dimensions of an external heat sink, which maintains the specified device’s junction temperature within desired operating temperature limits, are determined as functions of air flow rate and power density of surrounding semiconductor devices. Parametric studies have been performed to study the effects of heat sink height, width and length on junction-to-ambient thermal resistance of a high power application specific integrated circuit (ASIC) device found in the MCM assembly. A set of curves are generated to select either heat sink dimensions or air speed for a given design requirements. Influence of the power output of surrounding devices on the thermal performance of the high power ASIC device is also assessed. The predicted results indicate that the ASIC device’s junction temperature as well as junction-to-ambient resistance increase as the power of the surrounding packages increases. This effect diminishes if a sufficiently large heat sink is used to cool the package.
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Anghinolfi, F., W. Dabrowski, E. Delagnes, J. Kaplon, U. Koetz, P. Jarron, F. Lugiez, C. Posch, S. Roe, and P. Weilhammer. "SCTA-a rad-hard BiCMOS analogue readout ASIC for the ATLAS Semiconductor Tracker." IEEE Transactions on Nuclear Science 44, no. 3 (June 1997): 298–302. http://dx.doi.org/10.1109/23.603659.

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Dissertations / Theses on the topic "ASIC semiconductor"

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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.

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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Pang, Tak-yuen Philip. "Topic : an analysis of contemporary semiconductor manufacturing and the role of Asia Pacific Region within /." Hong Kong : University of Hong Kong, 1997. http://sunzi.lib.hku.hk/hkuto/record.jsp?B18835880.

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彭德源 and Tak-yuen Philip Pang. "Topic: an analysis of contemporary semiconductor manufacturing and the role of Asia Pacific Region within." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31268274.

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Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

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Demirci, Kemal Safak. "Chemical microsystem based on integration of resonant microsensor and CMOS ASIC." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41182.

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The main topic of this thesis is the development of a chemical microsystem based on integration of a silicon-based resonant microsensor and a CMOS ASIC for portable sensing applications. Cantilever and disk-shape microresonators have been used as mass-sensitive sensors. Based on the characteristics of the microresonators, CMOS integrated interface and control electronics have been implemented. The CMOS ASIC utilizes the self-oscillation method, which incorporates the microresonator in an amplifying feedback loop as the frequency determining element. In this manner, the ASIC includes a main feedback loop to sustain oscillation at or close to the fundamental resonance frequency of the microresonator. For stable oscillation, an automatic gain control loop regulates the oscillation amplitude by controlling the gain of the main feedback loop. In addition, an automatic phase control loop has been included to adjust the phase of the main feedback loop to ensure an operating point as close as possible to the resonance frequency, resulting in improved frequency stability. The CMOS chip has been interfaced to cantilever and disk-shape microresonators and short-term frequency stabilities as low as 3.4×10-8 in air have been obtained with a 1 sec gate time. The performance of the implemented microsystem as a chemical sensor has been evaluated experimentally with microresonators coated with chemically sensitive polymer films. With a gas-phase chemical measurement setup constructed in this work, chemical measurements have been performed and different concentrations of VOCs, such as benzene, toluene and m-xylene have been detected with limits of detection of 5.3 ppm, 1.2 ppm and 0.35 ppm, respectively. To improve the long-term stability in monitoring applications with slowly changing analyte signatures, a method to compensate for frequency drift caused by environmental disturbances has been implemented on the CMOS chip. This method uses a controlled stiffness modulation generated by a frequency drift compensation circuit to track the changes in the resonator's Q-factor in response to variations in the environmental conditions. The measured Q-factor is then used to compensate for the frequency drift using an initial calibration step. The feasibility of the proposed method has been verified experimentally by compensating for temperature-induced frequency drift during gas-phase chemical measurements.
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Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.

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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.
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Asif, Ali [Verfasser], and Joachim [Akademischer Betreuer] Burghartz. "Laterally diffused metal oxide semiconductor transistors on ultra-thin single-crystalline silicon / Ali Asif. Betreuer: Joachim Burghartz." Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2011. http://d-nb.info/1016459262/34.

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Bouyjou, Florent. "Nouvelles chaînes d'instrumentation intégrées multivoies pour l'astrophysique." Phd thesis, Institut National Polytechnique de Toulouse - INPT, 2011. http://tel.archives-ouvertes.fr/tel-00766655.

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L'exploration du système solaire et l'étude de l'univers lointain sont principalement basées sur la mesure d'ions et de particules in-situ. Les détecteurs, utilisés pour convertir l'énergie en charges électriques mesurables, sont étroitement liés à leur électronique analogique Analog-Front-End (AFE) et cette combinaison forme des chaines astrophysiques de détection appelées "sensor heads". La nécessité d'améliorer les résolutions spatiales et spectrales des détecteurs nécessite la conception d'une électronique intégrée multivoies. Par ailleurs, pour s'adapter au mieux à chaque détecteur, une instrumentation spécifique devra être mise en oeuvre. Ainsi, le développement d'une électronique spatiale de type Application Specific Integrated Circuit (ASIC) doit être développée, nécessitant un savoir faire spécifique. La première partie de la thèse est consacrée à décrire les différentes méthodes de mesure des particules en environnement spatial. Le deuxième chapitre présente l'architecture d'un détecteur constitué de MicroChannel Plates (MCP), puis l'architecture d'un détecteur à base de semi-conducteurs pour la spectrométrie d'électrons énergétique. Le premier détecteur est utilisé pour la détection de particules alors que le deuxième permet de mesurer le niveau d'énergie déposé par les électrons dans des semi-conducteurs (Si et CdZnTe). Le simulateur GEANT 4 a permis de déterminer la géométrie optimale du détecteur en quantifiant le nombre de paires électron-positron créées dans les semi-conducteurs en fonction de l'énergie des particules incidentes. Le troisième chapitre présente une méthodologie de conception des chaînes d'instrumentation en technologie CMOS permettant de s'adapter aux différents détecteurs. Une étude succincte des effets de l'environnement spatial sur l'électronique CMOS est également réalisée. La structure analogique permettant de convertir une charge en tension est présentée et des pistes dont proposées afin de l'optimiser en vitesse, en bruit et en consommation. Le quatrième et cinquième chapitres de la thèse traitent du développement de deux ASICs, l'un permettant d'instrumenter un détecteur à MCP, l'autre un détecteur à semi-conducteurs. Enfin, le dernier chapitre présente les validations expérimentales et les performances des chaînes de détection pour la MCP et les semi-conducteurs. Les résultats de ces mesures ont permis de montrer la faisabilité de l'intégration multivoies de deux chaînes d'instrumentation spatiale validant ainsi la méthodologie de conception. Les performances obtenues sont meilleures que celles obtenues en électronique discrète et sont adaptées à l'environnement spatial. Ces nouvelles chaînes multivoies réalisées ouvrent donc de nouvelles perspectives dans les futures missions en astrophysique.
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DA, Huang Chun, and 黃俊達. "Investigation on Operating Efficiency of the Asia Semiconductor Foundries --An Application of the DEA Method." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80878616296621231558.

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碩士
大葉大學
國際企業管理學系碩士在職專班
93
In Asia semiconductor markets, there exist top three semiconductor foundries of worldwide markets. Although USA and Japan withdrawn from foundry market gradually, Taiwan still need to face and compete against the new strong chipmaker from Asia (for examples, China, Korea, Japan...etc.) with low-price strategy in order to join this field. So how to improve the company operating efficiency is the first priority for Taiwan Semiconductor Manufacturer. This thesis takes 8 chip foundry companies of Asia as object of research. The main statistics data we used for is the official financial data by the year of 2003. This research focused on estimation of the efficiency analysis between input resources and output results by DEA (Data envelopment analysis). The parameters we used for input variables are assets、employee number and for output variable is the volume of sales. We use the software of the Frontier Analyst to calculate the overall technical efficiency of the sample chip foundry companies by CCR Mode and acquire pure technical efficiency with BCC mode. And than combine with the above two numbers we can acquire scale efficiency. Research results obtain by DEA analysis show that the Efficiency Rating number of TSMC and DongbuAnam are both 1. That means their operating between investing and producing at optimum situation. Therefore, they become goals of other companies.
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Chang, Kevin Hann, and 張翰. "Regional Operations Strategy in Asia — A Case Study of an US Semiconductor Capital Equipment Company." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/26147323010914773078.

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碩士
國立政治大學
經營管理碩士學程(EMBA)
96
In the 21st century, the globalization movement to multinational corporations is an inevitable process to maintain the continuous business growth. Asia, in particular, has drawn all the attention of multinational corporations worldwide and is considered as the region of the century. This research is designed to study the Asian regional operations of a multinational corporate in semiconductor equipment industry. In response to the regional customers demand, the regional competition, and the regional operations cost reduction, the case company has strategically established regional operations centers in Asia, covering the aspects of technical support, technical training, parts logistics, parts sourcing and repairing, as well as service outsourcing. This study found that the outstanding regional operations strategy plays a key role in the industrial competition and the overall operational excellence. The service enhancement through the technical support and spares sourcing can directly benefit the IC manufacturing customers and reword to the cost reduction of the regional operations. The studied case company clearly can be a benchmark of the regional operations practices for semiconductor equipment industry as well as for other related industries. Furthermore, the objective of this research is to provide useful suggestions that may help the firms in the industry on their future regional operations strategies setting as well as offer the academic researchers with a good case study of the development of regional operations in Asia.
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Books on the topic "ASIC semiconductor"

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Memory, microprocessor, and ASIC. Boca Raton: CRC Press, 2003.

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (1st 1990 Danvers, Mass.). IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop: Theme, "World class manufacturing" : ASMC '90 proceedings. New York: Institute of Electrical and Electronics Engineers, 1990.

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Semiconductor Equipment and Masterials International., ed. IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop: ASMC '91 proceedings : October 21-23, 1991, Boston, Massachusetts. New York: Institute of Electrical and Electronics Engineers, 1991.

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (3rd 1992 Cambridge, Mass.). IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop: ASMC '92 proceedings, September 30-October 1, 1992, Cambridge, Massachusetts. New York: Institute of Electrical and Electronics Engineers, 1992.

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (10th 1999 Boston, Mass.). 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop: ASMC 99 proceedings : September 8-10, 1999, Boston, Massachusetts, USA. Piscataway, N.J: IEEE, 1999.

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (4th 1993 Boston, Mass.). IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop: Theme, "Factory of the future" : ASMC '93 proceedings, October 18-19, 1993, Boston, Massachusetts. [New York: Institute of Electrical and Electronics Engineers], 1993.

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IEEE/SEMI, Advanced Semiconductor Manufacturing Conference and Workshop (10th 1999 Boston Massachusetts). ASMC 99: 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop : [proceedings] : September 8-10, 1999, the Fairmont Copley Plaza, Boston, Massachusetts, USA. Piscataway, New Jersey: IEEE, 1999.

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (7th 1996 Cambridge, Mass.). IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop: ASMC 96 proceedings : theme, Innovative approaches to growth in the semiconductor industry, November 12-14, 1996, Cambridge, Massachusetts. [New York, N.Y.]: Institute of Electrical and Electronics Engineers, 1996.

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (2nd 1991 Boston, Mass.). IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop: ASMC '91 proceedings : October 21-23, 1991, Boston Massachusetts. New York, N.Y: The Institute of Electrical and Electronics Engineers, 1991.

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IEEE/SEMI, Advanced Semiconductor Manufacturing Conference and Workshop (13th 2002 Boston Mass ). ASMC 2002: The 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference [and Workshop : Advancing the science of semiconductor manufacturing excellence] : April 30-May 2, Seaport Hotel, Boston, MA, USA. Piscataway, N.J: IEEE, 2002.

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Book chapters on the topic "ASIC semiconductor"

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Davies, M. S., and P. D. T. O’Connor. "Reliability Assessment of Cmos Asic Designs." In Semiconductor Device Reliability, 137–46. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-009-2482-6_8.

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Mele, Filippo. "Application Specific Integrated Circuits for High Resolution X and Gamma Ray Semiconductor Detectors." In Special Topics in Information Technology, 31–42. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_3.

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AbstractThe increasing demand for performance improvements in radiation detectors, driven by cutting-edge research in nuclear physics, astrophysics and medical imaging, is causing not only a proliferation in the variety of the radiation sensors, but also a growing necessity of tailored solutions for the front-end readout electronics. Within this work, novel solutions for application specific integrated circuits (ASICs) adopted in high-resolution X and $$\upgamma $$ γ ray spectroscopy applications are studied. In the first part of this work, an ultra-low noise charge sensitive amplifier (CSA) is presented, with specific focus on sub-microsecond filtering, addressing the growing interest in high-luminosity experiments. The CSA demonstrated excellent results with Silicon Drift Detectors (SDDs), and with room temperature Cadmium-Telluride (CdTe) detectors, recording a state-of-the-art noise performance. The integration of the CSA within two full-custom radiation detection instruments realized for the ELETTRA (Trieste, Italy) and SESAME (Allan, Jordan) synchrotrons is also presented. In the second part of this work, an ASIC constellation designed for X-Gamma imaging spectrometer (XGIS) onboard of the THESEUS space mission is described. The presented readout ASIC has a highly customized distributed architecture, and integrates a complete on-chip signal filtering, acquisition and digitization with an ultra-low power consumption.
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Tejedor, C., L. Brey, G. Platero, and P. A. Schulz. "Magnetotunneling in Semiconductor Microstructures." In NATO ASI Series, 407–23. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6565-6_27.

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Wieder, H. H. "Narrow Bandgap Semiconductor Devices." In NATO ASI Series, 231–50. Boston, MA: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-1879-8_20.

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Prinz, Gary A. "Hybrid Ferromagnetic/Semiconductor Structures." In NATO ASI Series, 41–54. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4899-2590-9_5.

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Cingolani, Roberto. "Quantum Confined Semiconductor Lasers." In NATO ASI Series, 83–97. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-2998-9_6.

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Ciraci, S., and Inder P. Batra. "Metallization of Metal-Semiconductor Interfaces." In NATO ASI Series, 335–49. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4613-0795-2_22.

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Esaki, L. "Implications of Semiconductor Superlattice Research." In NATO ASI Series, 55–82. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4899-3686-8_6.

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Kapon, E., J. P. Harbison, R. Bhat, and D. M. Hwang. "Patterned Quantum Well Semiconductor Lasers." In NATO ASI Series, 49–59. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4684-7278-3_5.

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Van Houten, H., C. W. J. Beenakker, and A. A. M. Staring. "Coulomb-Blockade Oscillations in Semiconductor Nanostructures." In NATO ASI Series, 167–216. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2166-9_5.

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Conference papers on the topic "ASIC semiconductor"

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Gavrus, Radu, and Carmen Gerigan. "Logic BIST for Structured ASIC." In 2006 International Semiconductor Conference. IEEE, 2006. http://dx.doi.org/10.1109/smicnd.2006.284039.

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Varachiu, Nicolae, J. L. Noullet, A. Rumeau, and Daniela Dragomirescu. "Process Capability Evaluation for Fabrication of ASIC IR-UWB Transceivers." In 2019 International Semiconductor Conference (CAS). IEEE, 2019. http://dx.doi.org/10.1109/smicnd.2019.8923859.

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Rajah, A., and M. Khalil Hani. "ASIC design of a Kohonen neural network microchip." In 2004 IEEE International Conference on Semiconductor Electronics. IEEE, 2004. http://dx.doi.org/10.1109/smelec.2004.1620857.

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Chong, Ang Boon. "Gross Die Estimator's caveats for ASIC floorplanning." In 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2012. http://dx.doi.org/10.1109/smelec.2012.6417179.

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Loh Siang Poh and Lim Chooi Pei. "Hybrid clock network for altera structure ASIC devices." In 2008 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2008. http://dx.doi.org/10.1109/smelec.2008.4770269.

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Tulbure, Traian, and Radu Gavrus. "A test optimized dynamic reconfigurable CPLD for structured ASIC technology." In 2011 International Semiconductor Conference (CAS 2011). IEEE, 2011. http://dx.doi.org/10.1109/smicnd.2011.6095812.

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Hamashima, K. "Many-Kinds Small-Amount Production In ASIC Factory." In 2008 IEEE International Symposium on Semiconductor Manufacturing (ISSM 2008). IEEE, 1994. http://dx.doi.org/10.1109/issm.1994.729419.

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Hoe Oh, Guan, Wey Tsen Lor, Hee Kong Phoon, and Chooi Pei Lim. "High performance configurable distributed hybrid memory in structured ASIC." In 2008 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2008. http://dx.doi.org/10.1109/smelec.2008.4770270.

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Alias, Nurul Ezaila, Suhaila Ishaak, Koo Jian Hong, Michael Loong Peng Tan, Afiq Hamzah, and Yasmin Abdul Wahab. "ASIC Implementation and Optimization of 16 Bit SDRAM Memory Controller." In 2020 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2020. http://dx.doi.org/10.1109/icse49846.2020.9166869.

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Phoon, Hee Kong, Matthew Yap, and Chuan Khye Chai. "A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration." In 2006 IEEE International Conference on Semiconductor Electronics. IEEE, 2006. http://dx.doi.org/10.1109/smelec.2006.381114.

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