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Journal articles on the topic 'Approximate multipliers'

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Published: 28 June 2021

Last updated: 7 February 2022

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1

Balasubramanian, Padmanabhan, Raunaq Nayar, and Douglas L. Maskell. "Approximate Array Multipliers." Electronics 10, no. 5 (March 9, 2021): 630. http://dx.doi.org/10.3390/electronics10050630.

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This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.

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2

Lotrič, Uroš, Ratko Pilipović, and Patricio Bulić. "A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing." Electronics 10, no. 10 (May 14, 2021): 1175. http://dx.doi.org/10.3390/electronics10101175.

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Multiplication is an essential image processing operation commonly implemented in hardware DSP cores. To improve DSP cores’ area, speed, or energy efficiency, we can approximate multiplication. We present an approximate multiplier that generates two partial products using hybrid radix-4 and logarithmic encoding of the input operands. It uses the exact radix-4 encoding to generate the partial product from the three most significant bits and the logarithmic approximation with mantissa trimming to approximate the partial product from the remaining least-significant bits. The proposed multiplier fills the gap between highly accurate approximate non-logarithmic multipliers with a complex design and less accurate approximate logarithmic multipliers with a more straightforward design. We evaluated the multiplier’s efficiency in terms of error, energy (power-delay-product) and area utilisation using NanGate 45 nm. The experimental results show that the proposed multiplier exhibits good area utilisation and energy consumption and behaves well in image processing applications.

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Kassem, M. S., and K. Rowlands. "The quasi-strict topology on the space of quasi-multipliers of a B*-algebra." Mathematical Proceedings of the Cambridge Philosophical Society 101, no. 3 (May 1987): 555–66. http://dx.doi.org/10.1017/s0305004100066913.

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The notion of a left (right, double) multiplier may be regarded as a generalization of the concept of a multiplier to a non-commutative Banach algebra. Each of these is a special case of a more general object, namely that of a quasi-multiplier. The idea of a quasi-multiplier was first introduced by Akemann and Pedersen in ([1], §4), where they consider the quasi-multipliers of a C*-algebra. One of the defects of quasi-multipliers is that, at least a priori, there does not appear to be a way of multiplying them together. The general theory of quasi-multipliers of a Banach algebra A with an approximate identity was developed by McKennon in [5], and in particular he showed that the quasi-multipliers of a considerable class of Banach algebras could be multiplied. McKennon also introduced a locally convex topology γ on the space QM(A) of quasi-multipliers of A and derived some of the elementary properties of (QM(A), γ).

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4

Jamal, Sameerah. "Approximate Conservation Laws of Nonvariational Differential Equations." Mathematics 7, no. 7 (June 27, 2019): 574. http://dx.doi.org/10.3390/math7070574.

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The concept of an approximate multiplier (integrating factor) is introduced. Such multipliers are shown to give rise to approximate local conservation laws for differential equations that admit a small perturbation. We develop an explicit, algorithmic and efficient method to construct both the approximate multipliers and their corresponding approximate fluxes. Our method is applicable to equations with any number of independent and dependent variables, linear or nonlinear, is adaptable to deal with any order of perturbation and does not require the existence of a variational principle. Several important perturbed equations are presented to exemplify the method, such as the approximate KdV equation. Finally, a second treatment of approximate multipliers is discussed.

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5

Shirane, Kenta, Takahiro Yamamoto, and Hiroyuki Tomiyama. "A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 1 (March 1, 2021): 1. http://dx.doi.org/10.11591/ijres.v10.i1.pp1-10.

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In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.

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6

Esposito, Darjn, Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, and Nicola Petra. "Approximate Multipliers Based on New Approximate Compressors." IEEE Transactions on Circuits and Systems I: Regular Papers 65, no. 12 (December 2018): 4169–82. http://dx.doi.org/10.1109/tcsi.2018.2839266.

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7

Sureshbabu, J., and G. Saravanakumar. "A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging." Journal of Medical Imaging and Health Informatics 10, no. 4 (April 1, 2020): 814–21. http://dx.doi.org/10.1166/jmihi.2020.2936.

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In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to high-speed multipliers which are designed with less area that consume low power. The major constraints to be considered for an efficient multiplier design are propagation time delay and power dissipation, especially during the ideal time. An approximate recoding adder is proposed to reduce the existing booth multiplier's immensity. It increases the accuracy and reduces complexity through this technique; however, it has an issue with Power Delay Product (PDP) and power dissipation. To solve this problem, the proposed system is designed with a power gating based 16 × 16 bit Booth multiplier based on approximate recoding adder. It decreases the power dissipation and minimizes the length and width of the partial products for speeding up the multiplication process. The results obtained from the simulation show that the designed power gating based Radix multiplier circuits achieves better PDP, average power and area. The achieved results are compared with a Radix based multiplier, power gating CLA based multiplier and CLA based multiplier.

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8

Ghabraei, Samar, Morteza Rezaalipour, Masoud Dehyadegari, and Mahdi Nazm Bojnordi. "AxCEM: Designing Approximate Comparator-Enabled Multipliers." Journal of Low Power Electronics and Applications 10, no. 1 (March 1, 2020): 9. http://dx.doi.org/10.3390/jlpea10010009.

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Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often suggests employing approximate computing to improve the energy-efficiency, performance, and area of floating-point multipliers. Prior work has shown that employing hardware-oriented approximation for computing the mantissa product may result in significant system energy reduction at the cost of an acceptable computational error. This article examines the design of an approximate comparator used for preforming mantissa products in the floating-point multipliers. First, we illustrate the use of exact comparators for enhancing power, area, and delay of floating-point multipliers. Then, we explore the design space of approximate comparators for designing efficient approximate comparator-enabled multipliers (AxCEM). Our simulation results indicate that the proposed architecture can achieve a 66% reduction in power dissipation, another 66% reduction in die-area, and a 71% decrease in delay. As compared with the state-of-the-art approximate floating-point multipliers, the accuracy loss in DNN applications due to the proposed AxCEM is less than 0.06%.

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Malviya, Monika, and Prof Pankaj Vyas. "Review of Rounding Based Approximate Multiplier (ROBA) For Digital Signal Processing." International Journal on Recent and Innovation Trends in Computing and Communication 7, no. 4 (April 15, 2019): 04–07. http://dx.doi.org/10.17762/ijritcc.v7i4.5277.

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The fundamental idea of adjusting put together estimated multiplier depends with respect to adjusting of numbers. This multiplier can be connected for both marked and unsigned numbers. In this paper contemplated an Rounding Based Approximate Multiplier that is fast yet vitality effective. The methodology is to round the operands to the closest example of two. Along these lines the computational concentrated piece of the augmentation is excluded improving rate and vitality utilization at the cost of a little mistake. This methodology is appropriate to both marked and unsigned augmentations. The productivity of the ROBA multiplier is assessed by contrasting its execution and those of some rough and precise multipliers utilizing distinctive plan parameters.

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10

Miura, Takeshi, Go Hirasawa, and Sin-Ei Takahasi. "Stability of multipliers on Banach algebras." International Journal of Mathematics and Mathematical Sciences 2004, no. 45 (2004): 2377–81. http://dx.doi.org/10.1155/s0161171204402324.

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SupposeAis a Banach algebra without order. We show that an approximate multiplierT:A→Ais an exact multiplier. We also consider an approximate multiplierTon a Banach algebra which need not be without order. If, in addition,Tis approximately additive, then we prove the Hyers-Ulam-Rassias stability ofT.

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11

Senthilkumar, K. K., Kunaraj Kumarasamy, and Vaithiyanathan Dhandapani. "Approximate Multipliers Using Bio-Inspired Algorithm." Journal of Electrical Engineering & Technology 16, no. 1 (October 28, 2020): 559–68. http://dx.doi.org/10.1007/s42835-020-00564-w.

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12

Merhav, N., and R. Kresch. "Approximate convolution using DCT coefficient multipliers." IEEE Transactions on Circuits and Systems for Video Technology 8, no. 4 (1998): 378–85. http://dx.doi.org/10.1109/76.709404.

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13

Bodaghi, Abasalt, Madjid Eshaghi Gordji, and Kamal Paykan. "Approximate Multipliers And Approximate Double Centralizers: A fixed Point Approach." Analele Universitatii "Ovidius" Constanta - Seria Matematica 20, no. 3 (December 1, 2012): 21–32. http://dx.doi.org/10.2478/v10309-012-0052-1.

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AbstractIn the present paper, the Hyers-Ulam stability and also the super-stability of double centralizers and multipliers on Banach algebras are established by using a fixed point method. With this method, the condition of without order on Banach algebras is no longer necessary.

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14

Yang, Zhixi, Xianbin Li, and Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction." Journal of Circuits, Systems and Computers 29, no. 15 (June 30, 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.

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Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

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15

G, Navabharath Reddy, Sruti Setlam, V. Prakasam, and D. Kiran Kumar. "Approximate arithmetic circuits." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 3 (November 1, 2020): 183. http://dx.doi.org/10.11591/ijres.v9.i3.pp183-200.

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Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

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16

G., Suresh. "Approximate Compressors based Inexact Vedic Dadda Multipliers." HELIX 8, no. 1 (January 1, 2018): 2683–90. http://dx.doi.org/10.29042/2018-2683-2690.

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17

Sarwar, Syed Shakib, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, and Kaushik Roy. "Energy-Efficient Neural Computing with Approximate Multipliers." ACM Journal on Emerging Technologies in Computing Systems 14, no. 2 (July 27, 2018): 1–23. http://dx.doi.org/10.1145/3097264.

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18

Mazahir, Sana, Osman Hasan, Rehan Hafiz, and Muhammad Shafique. "Probabilistic Error Analysis of Approximate Recursive Multipliers." IEEE Transactions on Computers 66, no. 11 (November 1, 2017): 1982–90. http://dx.doi.org/10.1109/tc.2017.2709542.

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19

Ansari, Mohammad Saeed, Honglan Jiang, Bruce F. Cockburn, and Jie Han. "Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8, no. 3 (September 2018): 404–16. http://dx.doi.org/10.1109/jetcas.2018.2832204.

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20

Fang, Bao, Huaguo Liang, Dawen Xu, Maoxiang Yi, Yongxia Sheng, Cuiyun Jiang, Zhengfeng Huang, and Yingchun Lu. "Approximate multipliers based on a novel unbiased approximate 4-2 compressor." Integration 81 (November 2021): 17–24. http://dx.doi.org/10.1016/j.vlsi.2021.05.003.

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21

Tabrizchi, Sepehr, Atiyeh Panahi, Fazel Sharifi, Hamid Mahmoodi, and Abdel-Hameed A. Badawy. "Energy-Efficient Ternary Multipliers Using CNT Transistors." Electronics 9, no. 4 (April 14, 2020): 643. http://dx.doi.org/10.3390/electronics9040643.

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In recent decades, power consumption has become an essential factor in attracting the attention of integrated circuit (IC) designers. Multiple-valued logic (MVL) and approximate computing are some techniques that could be applied to integrated circuits to make power-efficient systems. By utilizing MVL-based circuits instead of binary logic, the information conveyed by digital signals increases, and this reduces the required interconnections and power consumption. On the other hand, approximate computing is a class of arithmetic computing used in systems where the accuracy of the computation can be traded-off for lower energy consumption. In this paper, we propose novel designs for exact and inexact ternary multipliers based on carbon-nanotube field-effect transistors (CNFETs). The unique characteristics of CNFETs make them a desirable alternative to MOSFETs. The simulations are conducted using Synopsys HSPICE. The proposed design is compared against existing ternary multipliers. The results show that the proposed exact multiplier reduces the energy consumption by up to 6 times, while the best inexact design improves energy efficiency by up to 35 time compared to the latest state-of-the-art methods. Using the imprecise multipliers for image processing provides evidence that these proposed designs are a low-power system with an acceptable error.

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Waris, Haroon, Chenghua Wang, and Weiqiang Liu. "Hybrid Low Radix Encoding-Based Approximate Booth Multipliers." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 12 (December 2020): 3367–71. http://dx.doi.org/10.1109/tcsii.2020.2975094.

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23

Lotrič, Uroš, and Patricio Bulić. "Applicability of approximate multipliers in hardware neural networks." Neurocomputing 96 (November 2012): 57–65. http://dx.doi.org/10.1016/j.neucom.2011.09.039.

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24

Liu, Weiqiang, Tian Cao, Peipei Yin, Yuying Zhu, Chenghua Wang, Earl E. Swartzlander, and Fabrizio Lombardi. "Design and Analysis of Approximate Redundant Binary Multipliers." IEEE Transactions on Computers 68, no. 6 (June 1, 2019): 804–19. http://dx.doi.org/10.1109/tc.2018.2890222.

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Venkatachalam, Suganthi, and Seok-Bum Ko. "Design of Power and Area Efficient Approximate Multipliers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 5 (May 2017): 1782–86. http://dx.doi.org/10.1109/tvlsi.2016.2643639.

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Dündar, G., F.-C. Hsu, and K. Rose. "Effects of Nonlinear Synapses on the Performance of Multilayer Neural Networks." Neural Computation 8, no. 5 (July 1996): 939–49. http://dx.doi.org/10.1162/neco.1996.8.5.939.

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The problems arising from the use of nonlinear multipliers in multilayer neural network synapse structures are discussed. The errors arising from the neglect of nonlinearities are shown and the effect of training in eliminating these errors is discussed. A method for predicting the final errors resulting from nonlinearities is described. Our approximate results are compared with the results from circuit simulations of an actual multiplier circuit.

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27

Leon, Vasileios, Theodora Paparouni, Evangelos Petrongonas, Dimitrios Soudris, and Kiamal Pekmestzi. "Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers." ACM Transactions on Embedded Computing Systems 20, no. 5 (July 2021): 1–21. http://dx.doi.org/10.1145/3448980.

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Approximate computing has emerged as a promising design alternative for delivering power-efficient systems and circuits by exploiting the inherent error resiliency of numerous applications. The current article aims to tackle the increased hardware cost of floating-point multiplication units, which prohibits their usage in embedded computing. We introduce AFMU (Approximate Floating-point MUltiplier), an area/power-efficient family of multipliers, which apply two approximation techniques in the resource-hungry mantissa multiplication and can be seamlessly extended to support dynamic configuration of the approximation levels via gating signals. AFMU offers large accuracy configuration margins, provides negligible logic overhead for dynamic configuration, and detects unexpected results that may arise due to the approximations. Our evaluation shows that AFMU delivers energy gains in the range 3.6%–53.5% for half-precision and 37.2%–82.4% for single-precision, in exchange for mean relative error around 0.05%–3.33% and 0.01%–2.20%, respectively. In comparison with state-of-the-art multipliers, AFMU exhibits up to 4–6× smaller error on average while delivering more energy-efficient computing. The evaluation in image processing shows that AFMU provides sufficient quality of service, i.e., more than 50 db PSNR and near 1 SSIM values, and up to 57.4% power reduction. When used in floating-point CNNs, the accuracy loss is small (or zero), i.e., up to 5.4% for MNIST and CIFAR-10, in exchange for up to 63.8% power gain.

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Strollo, Antonio Giuseppe Maria, Ettore Napoli, Davide De Caro, Nicola Petra, and Gennaro Di Meo. "Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 9 (September 2020): 3021–34. http://dx.doi.org/10.1109/tcsi.2020.2988353.

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GUO, Yi, Heming SUN, Ping LEI, and Shinji KIMURA. "Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, no. 9 (September 1, 2020): 1054–62. http://dx.doi.org/10.1587/transfun.2019kep0002.

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30

Hammad, Issam, and Kamal El-Sankary. "Impact of Approximate Multipliers on VGG Deep Learning Network." IEEE Access 6 (2018): 60438–44. http://dx.doi.org/10.1109/access.2018.2875376.

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Jiang, Honglan, Cong Liu, Fabrizio Lombardi, and Jie Han. "Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 1 (January 2019): 189–202. http://dx.doi.org/10.1109/tcsi.2018.2856245.

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Kim, Min Soo, Alberto A. Del Barrio, Leonardo Tavares Oliveira, Roman Hermida, and Nader Bagherzadeh. "Efficient Mitchell’s Approximate Log Multipliers for Convolutional Neural Networks." IEEE Transactions on Computers 68, no. 5 (May 1, 2019): 660–75. http://dx.doi.org/10.1109/tc.2018.2880742.

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Osta, Mario, Ali Ibrahim, Lucia Seminara, Hussein Chible, and Maurizio Valle. "Low Power Approximate Multipliers for Energy Efficient Data Processing." Journal of Low Power Electronics 14, no. 1 (March 1, 2018): 110–17. http://dx.doi.org/10.1166/jolpe.2018.1536.

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Zhu, Yuying, Weiqiang Liu, Peipei Yin, Tian Cao, Jie Han, and Fabrizio Lombardi. "Design, evaluation and application of approximate-truncated Booth multipliers." IET Circuits, Devices & Systems 14, no. 8 (November 1, 2020): 1305–17. http://dx.doi.org/10.1049/iet-cds.2019.0398.

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Shirzadeh, Samad, and Behjat Forouzandeh. "High accurate multipliers using new set of approximate compressors." AEU - International Journal of Electronics and Communications 138 (August 2021): 153778. http://dx.doi.org/10.1016/j.aeue.2021.153778.

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Guo, Chuliang, Li Zhang, Xian Zhou, Grace Li Zhang, Bing Li, Weikang Qian, Xunzhao Yin, and Cheng Zhuo. "A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (June 30, 2021): 1–16. http://dx.doi.org/10.1145/3446213.

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Multiplications have been commonly conducted in quantized CNNs, filters, and reconfigurable cores, and so on, which are widely deployed in mobile and embedded applications. Most multipliers are designed to perform multiplications with symmetric bit-widths, i.e., n - by n -bit multiplication. Such features would cause extra area overhead and performance loss when m - by n -bit multiplications ( m > n ) are deployed in the same hardware design, resulting in inefficient multiplication operations. It is highly desired and challenging to propose a reconfigurable multiplier design to accommodate operands with both symmetric and asymmetric bit-widths. In this work, we propose a reconfigurable approximate multiplier to support multiplications at various precisions, i.e., bit-widths. Unlike prior works of approximate adders assuming a uniform weight distribution with bit-wise independence, scenarios like a quantized CNN may have a centralized weight distribution and hence follow a Gaussian-like distribution with correlated adjacent bits. Thus, a new block-based approximate adder is also proposed as part of the multiplier to ensure energy-efficient operation with an awareness of the bit-wise correlation. Our experimental results show that the proposed approximate adder significantly reduces the error rate by 76% to 98% over a state-of-the-art approximate adder for Gaussian-like distribution scenarios. Evaluation results show that the proposed multiplier is 19% faster and 22% more power saving than a Xilinx multiplier IP at the same bit precision and achieves a 23.94-dB peak signal-to-noise ratio, which is comparable to the accurate one of 24.10 dB when deployed in a Gaussian filter for image processing tasks.

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YANG, Tongxin, Tomoaki UKEZONO, and Toshinori SATO. "Design and Analysis of Approximate Multipliers with a Tree Compressor." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 3 (March 1, 2019): 532–43. http://dx.doi.org/10.1587/transfun.e102.a.532.

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Leon, Vasileios, Georgios Zervakis, Dimitrios Soudris, and Kiamal Pekmestzi. "Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 3 (March 2018): 421–30. http://dx.doi.org/10.1109/tvlsi.2017.2767858.

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Ha, Minho, and Sunggu Lee. "Multipliers With Approximate 4–2 Compressors and Error Recovery Modules." IEEE Embedded Systems Letters 10, no. 1 (March 2018): 6–9. http://dx.doi.org/10.1109/les.2017.2746084.

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40

Saadat, Hassaan, Haseeb Bokhari, and Sri Parameswaran. "Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 11 (November 2018): 2623–35. http://dx.doi.org/10.1109/tcad.2018.2857262.

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Leon, Vasileios, Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris, and Kiamal Pekmestzi. "Walking through the Energy-Error Pareto Frontier of Approximate Multipliers." IEEE Micro 38, no. 4 (July 2018): 40–49. http://dx.doi.org/10.1109/mm.2018.043191124.

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Sudharani, B., and G. Sreenivasulu. "Design of high speed approximate multipliers with inexact compressor adder." International Journal of Advanced Technology and Engineering Exploration 8, no. 80 (July 31, 2021): 887–902. http://dx.doi.org/10.19101/ijatee.2021.874124.

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Esmali Nojehdeh, Mohammadreza, and Mustafa Altun. "Systematic synthesis of approximate adders and multipliers with accurate error calculations." Integration 70 (January 2020): 99–107. http://dx.doi.org/10.1016/j.vlsi.2019.10.001.

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Anusha, G., and P. Deepa. "Design of approximate adders and multipliers for error tolerant image processing." Microprocessors and Microsystems 72 (February 2020): 102940. http://dx.doi.org/10.1016/j.micpro.2019.102940.

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Liu, Weiqiang, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, and Fabrizio Lombardi. "Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing." IEEE Transactions on Computers 66, no. 8 (August 1, 2017): 1435–41. http://dx.doi.org/10.1109/tc.2017.2672976.

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Venkatachalam, Suganthi, Elizabeth Adams, Hyuk Jae Lee, and Seok-Bum Ko. "Design and Analysis of Area and Power Efficient Approximate Booth Multipliers." IEEE Transactions on Computers 68, no. 11 (November 1, 2019): 1697–703. http://dx.doi.org/10.1109/tc.2019.2926275.

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Staber, B., and J. Guilleminot. "Approximate Solutions of Lagrange Multipliers for Information-Theoretic Random Field Models." SIAM/ASA Journal on Uncertainty Quantification 3, no. 1 (January 2015): 599–621. http://dx.doi.org/10.1137/14099574x.

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Mrazek, Vojtech, Zdenek Vasicek, Lukas Sekanina, Honglan Jiang, and Jie Han. "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 11 (November 2018): 2572–76. http://dx.doi.org/10.1109/tvlsi.2018.2856362.

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Lin, Huaxin. "Fundamental approximate identities and quasi-multipliers of simple AF C∗-algebras." Journal of Functional Analysis 79, no. 1 (July 1988): 32–43. http://dx.doi.org/10.1016/0022-1236(88)90028-6.

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GUO, Yi, Heming SUN, Ping LEI, and Shinji KIMURA. "Design of Low-Cost Approximate Multipliers Based on Probability-Driven Inexact Compressors." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 12 (December 1, 2019): 1781–91. http://dx.doi.org/10.1587/transfun.e102.a.1781.

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