Journal articles: 'Application specific processors'

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Edwards, C. "Into the fastlane [application specific processors]." Engineering & Technology 2, no. 1 (January 1, 2007): 36–39. http://dx.doi.org/10.1049/et:20070104.

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Veidenbaum, A. "Guest Editor's Introduction: Application-Specific Processors." IEEE Micro 24, no. 3 (May 2004): 8–9. http://dx.doi.org/10.1109/mm.2004.10.

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Sergienko, Anatolij M., Vitalij O. Romankevich, and Pavlo A. Serhiienko. "Image buffering in application specific processors." Applied Aspects of Information Technology 5, no. 3 (October 25, 2022): 228–39. http://dx.doi.org/10.15276/aait.05.2022.16.

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In many digital image-processingapplications, which are implementedin field programmable gate arrays,the currently processed image's frames are stored in external dynamic memory.The performance of such an application dependson the dynamic memoryspeed and the necessaryrequests quantity during algorithm’sruntime. This performance is being optimized through field programmable gate arrays -implemented buffer memory usage.But there is no common method for the formal buffer memory synthesis with preset throughput, input and output data sequenceorderand minimizedhardwarecosts.In this article,the featuresof image input and processing based on Field Programmable Gate Arrayareconsidered.The methods of building buffer circuits in field programmable gate arrays, due to which the intensity of data exchanges with external memory is reduced, are analyzed. Themethod of synthesizing pipeline circuits with specified performance characteristics and the data sequence order is given, which is based on the mapping of the spatial synchronous data flows into the structure implemented in the field programmable gate arrays.A method of designing buffer schemes is proposed, which is based on the mapping of spatial synchronous data flows into local memory in the form of chains of pipeline registers.The method helpsto organize the data flow of at the input of built-in pipeline units of image processing, in which the data follow in a given order, andto minimize the amount of buffer memory.The method ensures the use of dynamically adjustable register delays built into the field programmable gate arrays, which increases the efficiency of buffering.Thismethod was tested during the development of an intelligent video camera. The embedded hardware implements a video image compression algorithm with a wide dynamic range according to the Retinexalgorithm. The same time it selects characteristic points in the image for the further pattern recognition.At the same time, multiple decimation of the frame is performed. Due to themultirate buffering of the image in the field programmable gate arrays,it was possible to avoid using of external dynamic memory

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Karkhanis, Tejas S., and James E. Smith. "Automated design of application specific superscalar processors." ACM SIGARCH Computer Architecture News 35, no. 2 (June 9, 2007): 402–11. http://dx.doi.org/10.1145/1273440.1250712.

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Jacome, M. F., and G. De Veciana. "Design challenges for new application specific processors." IEEE Design & Test of Computers 17, no. 2 (2000): 40–50. http://dx.doi.org/10.1109/54.844333.

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Doroshenko, A., and D. Ragozin. "Retargetable code generation for application-specific processors." Future Generation Computer Systems 21, no. 5 (May 2005): 679–85. http://dx.doi.org/10.1016/j.future.2004.05.008.

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Smith, Melissa C., and Kubilay Atasu. "Guest Editorial: Application Specific Processors and Architectures." Journal of Signal Processing Systems 77, no. 1-2 (August 7, 2014): 1–3. http://dx.doi.org/10.1007/s11265-014-0934-8.

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Palmer, R. P., and P. A. Rounce. "An architecture for application specific neural network processors." Computing & Control Engineering Journal 5, no. 6 (December 1, 1994): 260–64. http://dx.doi.org/10.1049/cce:19940603.

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Fei Sun, S. Ravi, A. Raghunathan, and N. K. Jha. "Application-specific heterogeneous multiprocessor synthesis using extensible processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (September 2006): 1589–602. http://dx.doi.org/10.1109/tcad.2005.858269.

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Dimond, R., O. Mencer, and W. Luk. "Application-specific customisation of multi-threaded soft processors." IEE Proceedings - Computers and Digital Techniques 153, no. 3 (2006): 173. http://dx.doi.org/10.1049/ip-cdt:20050177.

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Sun, Fei, Srivaths Ravi, Anand Raghunathan, and Niraj K. Jha. "A Scalable Synthesis Methodology for Application-Specific Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 11 (November 2006): 1175–88. http://dx.doi.org/10.1109/tvlsi.2006.886410.

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Ienne, Paolo, and Peter Petrov. "Guest Editorial Special Section on Application Specific Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 10 (October 2008): 1257–58. http://dx.doi.org/10.1109/tvlsi.2008.2005245.

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Bose, P. "EIC's Message: General-purpose versus application-specific processors." IEEE Micro 24, no. 3 (May 2004): 5. http://dx.doi.org/10.1109/mm.2004.8.

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Kirchhoff, Michael, Philipp Kerling, Detlef Streitferdt, and Wolfgang Fengler. "A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor." International Journal of Reconfigurable Computing 2019 (September 22, 2019): 1–14. http://dx.doi.org/10.1155/2019/4723838.

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Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

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Nedjah, Nadia, Lech Jóźwiak, and Luiza de Macedo Mourelle. "Application-specific processors and system-on-chips for embedded and pervasive applications." Microprocessors and Microsystems 37, no. 6-7 (August 2013): 672–73. http://dx.doi.org/10.1016/j.micpro.2013.08.004.

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Brisk, Philip, and Tulika Mitra. "Introduction to the special issue on application-specific processors." ACM Transactions on Embedded Computing Systems 13, no. 2 (September 2013): 1–3. http://dx.doi.org/10.1145/2514641.2514642.

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Goossens, G., J. Rabaey, J. Vandewalle, and H. De Man. "An efficient microcode compiler for application specific DSP processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 9 (1990): 925–37. http://dx.doi.org/10.1109/43.59069.

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Labrecque, Martin, Mark C. Jeffrey, and J. Gregory Steffan. "Application-specific signatures for transactional memory in soft processors." ACM Transactions on Reconfigurable Technology and Systems 4, no. 3 (August 2011): 1–14. http://dx.doi.org/10.1145/2000832.2000833.

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Nery, Alexandre S., Lech Jóźwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, and Felipe M. G. França. "Hardware reuse in modern application-specific processors and accelerators." Microprocessors and Microsystems 37, no. 6-7 (August 2013): 684–92. http://dx.doi.org/10.1016/j.micpro.2012.06.005.

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Pitkänen, Teemu, Jarno K. Tanskanen, Risto Mäkinen, and Jarmo Takala. "Parallel Memory Architecture for Application-Specific Instruction-Set Processors." Journal of Signal Processing Systems 57, no. 1 (April 26, 2008): 21–32. http://dx.doi.org/10.1007/s11265-008-0173-y.

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Srinivasan, V. Prasanna, and A. P. Shanthi. "A BBN-Based Framework for Design Space Pruning of Application Specific Instruction Processors." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650028. http://dx.doi.org/10.1142/s0218126616500286.

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During the synthesis phase of the embedded system design process, the designer has to take early decisions for selecting the optimal system components such as processors, memories, communication interfaces, etc. from the available huge design alternatives. In order to obtain the optimal design configurations from the available huge design alternatives, an efficient design space pruning technique that will ease the design space exploration (DSE) process is required. The knowledge about the target architectural parameters affecting the overall objectives of the system should be considered during the design, so that the search process for finding the optimal system configurations will be rapid and more efficient. The Bayesian belief network (BBN)-based modeling framework for design space pruning proposed in this paper attempts to resolve the existing limitation in imparting domain knowledge and provides a pioneering effort to support the designer during the process of application specific system design. The Xtensa customizable processor architecture from Tensilica and a very long instruction word (VLIW) processor architecture are considered as example target platforms to impart the domain knowledge for the proposed model. Case studies in support of the proposed model are presented in order to understand how BBN can be used for design space pruning by propagating the evidence and arriving at probabilistic inferences to ease the decision-making process. The results show that the design space reduces drastically from a few million design options available to just less than one hundred for Xtensa architecture and from a few billions of design options available to just few thousands for VLIW architecture. The work also validates the pruned design points for their optimality.

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Latifis, Ioannis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, and Francky Catthoor. "A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors." ACM Transactions on Design Automation of Electronic Systems 22, no. 2 (March 15, 2017): 1–28. http://dx.doi.org/10.1145/2996182.

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Petrov, P., and A. Orailoglu. "Application-specific instruction memory customizations for power-efficient embedded processors." IEEE Design & Test of Computers 20, no. 1 (January 2003): 18–25. http://dx.doi.org/10.1109/mdt.2003.1173049.

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Salmela, Perttu, Juho Antikainen, Teemu Pitkänen, Olli Silvén, and Jarmo Takala. "3G Long Term Evolution Baseband Processing with Application-Specific Processors." International Journal of Digital Multimedia Broadcasting 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/503130.

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Data rates in the upcoming 3G long term evolution (LTE) standard will be manifold when compared to the current universal mobile telecommunications system. Implementing receivers conforming with the high-capacity transmission techniques is challenging due to the complexity and computational requirements of algorithms. In this study, the software defined radio (SDR) is targeted and the four essential baseband functions of the 3G LTE receiver, namely, list sphere decoding, fast Fourier transform, QR decomposition, and turbo decoding, are addressed and the functions are implemented as application specific processors (ASPs). As a result, the design space that describes the essential computational challenges of 3G LTE receivers is clarified and estimates of area, power, and interprocessor communication buffer requirements are presented.

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Petrov, P., and A. Orailoglu. "Low-power branch target buffer for application-specific embedded processors." IEE Proceedings - Computers and Digital Techniques 152, no. 4 (2005): 482. http://dx.doi.org/10.1049/ip-cdt:20041101.

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Horváth, Péter, Gábor Hosszú, and Ferenc Kovács. "A proposed synthesis method for Application-Specific Instruction Set Processors." Microelectronics Journal 46, no. 3 (March 2015): 237–47. http://dx.doi.org/10.1016/j.mejo.2015.01.001.

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Cathy Qun Xu, Chun Jason Xue, Jingtong Hu, and E. H. M. Sha. "Optimizing Scheduling and Intercluster Connection for Application-Specific DSP Processors." IEEE Transactions on Signal Processing 57, no. 11 (November 2009): 4538–47. http://dx.doi.org/10.1109/tsp.2009.2024870.

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Li, Tuo, Muhammad Shafique, Jude Angelo Ambrose, Jorg Henkel, and Sri Parameswaran. "Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors." IEEE Transactions on Computers 66, no. 4 (April 1, 2017): 647–60. http://dx.doi.org/10.1109/tc.2016.2606378.

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Xiao, Chenglong, Emmanuel Casseau, Shanshan Wang, and Wanjun Liu. "Automatic custom instruction identification for application-specific instruction set processors." Microprocessors and Microsystems 38, no. 8 (November 2014): 1012–24. http://dx.doi.org/10.1016/j.micpro.2014.09.001.

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Potkonjak, M., K. Kim, and R. Karri. "Computer aided design of fault-tolerant application specific programmable processors." IEEE Transactions on Computers 49, no. 11 (2000): 1272–84. http://dx.doi.org/10.1109/12.895942.

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Radhakrishnan, S., H. Guo, S. Parameswaran, and A. Ignjatovic. "HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors." IET Computers & Digital Techniques 3, no. 1 (2009): 94. http://dx.doi.org/10.1049/iet-cdt:20080005.

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Ziebinski, Adam, and Stanwlaw Swierc. "Soft Core Processor Generated Based on the Machine Code of the Application." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650029. http://dx.doi.org/10.1142/s0218126616500298.

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Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4).

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Sharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (May 27, 2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.

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Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

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Nery, Alexandre S., Nadia Nedjah, Felipe M. G. França, Lech Jóźwiak, and Henk Corporaal. "Automatic complex instruction identification for efficient application mapping onto application-specific instruction set processors." Analog Integrated Circuits and Signal Processing 85, no. 1 (June 30, 2015): 139–58. http://dx.doi.org/10.1007/s10470-015-0585-0.

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Jan, Yahya, and Lech Jóźwiak. "Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors." VLSI Design 2012 (March 25, 2012): 1–20. http://dx.doi.org/10.1155/2012/794753.

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This paper is devoted to the design of communication and memory architectures of massively parallel hardware multiprocessors necessary for the implementation of highly demanding applications. We demonstrated that for the massively parallel hardware multiprocessors the traditionally used flat communication architectures and multi-port memories do not scale well, and the memory and communication network influence on both the throughput and circuit area dominates the processors influence. To resolve the problems and ensure scalability, we proposed to design highly optimized application-specific hierarchical and/or partitioned communication and memory architectures through exploring and exploiting the regularity and hierarchy of the actual data flows of a given application. Furthermore, we proposed some data distribution and related data mapping schemes in the shared (global) partitioned memories with the aim to eliminate the memory access conflicts, as well as, to ensure that our communication design strategies will be applicable. We incorporated these architecture synthesis strategies into our quality-driven model-based multi-processor design method and related automated architecture exploration framework. Using this framework, we performed a large series of experiments that demonstrate many various important features of the synthesized memory and communication architectures. They also demonstrate that our method and related framework are able to efficiently synthesize well scalable memory and communication architectures even for the high-end multiprocessors. The gains as high as 12-times in performance and 25-times in area can be obtained when using the hierarchical communication networks instead of the flat networks. However, for the high parallelism levels only the partitioned approach ensures the scalability in performance.

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Asif, Muhammad, Imtiaz A. Taj, S. M. Ziauddin, Maaz Bin Ahmad, and M. Tahir. "A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding." Scientific Programming 2015 (2015): 1–16. http://dx.doi.org/10.1155/2015/197843.

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One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB) level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

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37

Hannig, Frank, and Dirk Koch. "Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors." Journal of Signal Processing Systems 93, no. 12 (September 30, 2021): 1363–64. http://dx.doi.org/10.1007/s11265-021-01708-5.

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Jungeblut, Thorsten, Boris Hübener, Mario Porrmann, and Ulrich Rückert. "A systematic approach for optimized bypass configurations for application-specific embedded processors." ACM Transactions on Embedded Computing Systems 13, no. 2 (September 2013): 1–25. http://dx.doi.org/10.1145/2514641.2514645.

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Mulder, H., and R. J. Portier. "Cost-effective design of application specific VLIW processors using the SCARCE framework." ACM SIGMICRO Newsletter 20, no. 3 (August 1989): 35–42. http://dx.doi.org/10.1145/75395.75400.

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So, Hayden Kwok-Hay, and Warren J. Gross. "Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors." Journal of Signal Processing Systems 90, no. 1 (May 4, 2017): 1–2. http://dx.doi.org/10.1007/s11265-017-1247-5.

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Tward, Daniel J., Can Ceritoglu, Anthony Kolasny, Gregory M. Sturgeon, W. Paul Segars, Michael I. Miller, and J. Tilak Ratnanather. "Patient Specific Dosimetry Phantoms Using Multichannel LDDMM of the Whole Body." International Journal of Biomedical Imaging 2011 (2011): 1–9. http://dx.doi.org/10.1155/2011/481064.

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This paper describes an automated procedure for creating detailed patient-specific pediatric dosimetry phantoms from a small set of segmented organs in a child's CT scan. The algorithm involves full body mappings from adult template to pediatric images using multichannel large deformation diffeomorphic metric mapping (MC-LDDMM). The parallel implementation and performance of MC-LDDMM for this application is studied here for a sample of 4 pediatric patients, and from 1 to 24 processors. 93.84% of computation time is parallelized, and the efficiency of parallelization remains high until more than 8 processors are used. The performance of the algorithm was validated on a set of 24 male and 18 female pediatric patients. It was found to be accurate typically to within 1-2 voxels (2–4 mm) and robust across this large and variable data set.

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42

Melnyk, Anatoliy, and M. Majstrenko. "Оптимізаційне проектування спеціалізованих процесорів з використанням системи автоматичного синтезу та інструментальних засобів." Computer systems and network 1, no. 1 (February 23, 2016): 37–47. http://dx.doi.org/10.23939/csn2016.857.037.

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Kindratenko, Volodymyr V., Adam D. Myers, and Robert J. Brunner. "Implementation of the Two-Point Angular Correlation Function on a High-Performance Reconfigurable Computer." Scientific Programming 17, no. 3 (2009): 247–59. http://dx.doi.org/10.1155/2009/434735.

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We present a parallel implementation of an algorithm for calculating the two-point angular correlation function as applied in the field of computational cosmology. The algorithm has been specifically developed for a reconfigurable computer. Our implementation utilizes a microprocessor and two reconfigurable processors on a dual-MAP SRC-6 system. The two reconfigurable processors are used as two application-specific co-processors. Two independent computational kernels are simultaneously executed on the reconfigurable processors while data pre-fetching from disk and initial data pre-processing are executed on the microprocessor. The overall end-to-end algorithm execution speedup achieved by this implementation is over 90× as compared to a sequential implementation of the algorithm executed on a single 2.8 GHz Intel Xeon microprocessor.

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Orailoglu, Alex, and Laura Pozzi. "Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 12 (December 2009): 1786–87. http://dx.doi.org/10.1109/tcad.2009.2035481.

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Cherupalli, Hari, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori. "Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors." ACM SIGOPS Operating Systems Review 51, no. 2 (April 4, 2017): 3–16. http://dx.doi.org/10.1145/3093315.3037711.

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Cherupalli, Hari, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori. "Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors." ACM SIGPLAN Notices 52, no. 4 (May 12, 2017): 3–16. http://dx.doi.org/10.1145/3093336.3037711.

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Cherupalli, Hari, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori. "Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors." ACM SIGARCH Computer Architecture News 45, no. 1 (May 11, 2017): 3–16. http://dx.doi.org/10.1145/3093337.3037711.

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Sengupta, Anirban, and Mahendra Rathor. "Obfuscated Hardware Accelerators for Image Processing Filters—Application Specific and Functionally Reconfigurable Processors." IEEE Transactions on Consumer Electronics 66, no. 4 (November 2020): 386–95. http://dx.doi.org/10.1109/tce.2020.3027760.

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Nery, Alexandre S., Nadia Nedjah, Felipe M. G. França, and Lech Jóźwiak. "Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs." Microprocessors and Microsystems 37, no. 6-7 (August 2013): 739–49. http://dx.doi.org/10.1016/j.micpro.2012.06.006.

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Aubertin, Philippe, J. M. Pierre Langlois, and Yvon Savaria. "Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 11 (November 2012): 2031–43. http://dx.doi.org/10.1109/tvlsi.2011.2170204.

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Journal articles on the topic 'Application specific processors'

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