Relevant bibliographies by topics / Application specific processors

Academic literature on the topic 'Application specific processors'

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Published: 4 June 2021
Last updated: 11 March 2023

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Journal articles on the topic "Application specific processors"

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Edwards, C. "Into the fastlane [application specific processors]." Engineering & Technology 2, no. 1 (January 1, 2007): 36–39. http://dx.doi.org/10.1049/et:20070104.

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Veidenbaum, A. "Guest Editor's Introduction: Application-Specific Processors." IEEE Micro 24, no. 3 (May 2004): 8–9. http://dx.doi.org/10.1109/mm.2004.10.

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Sergienko, Anatolij M., Vitalij O. Romankevich, and Pavlo A. Serhiienko. "Image buffering in application specific processors." Applied Aspects of Information Technology 5, no. 3 (October 25, 2022): 228–39. http://dx.doi.org/10.15276/aait.05.2022.16.

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In many digital image-processingapplications, which are implementedin field programmable gate arrays,the currently processed image's frames are stored in external dynamic memory.The performance of such an application dependson the dynamic memoryspeed and the necessaryrequests quantity during algorithm’sruntime. This performance is being optimized through field programmable gate arrays -implemented buffer memory usage.But there is no common method for the formal buffer memory synthesis with preset throughput, input and output data sequenceorderand minimizedhardwarecosts.In this article,the featuresof image input and processing based on Field Programmable Gate Arrayareconsidered.The methods of building buffer circuits in field programmable gate arrays, due to which the intensity of data exchanges with external memory is reduced, are analyzed. Themethod of synthesizing pipeline circuits with specified performance characteristics and the data sequence order is given, which is based on the mapping of the spatial synchronous data flows into the structure implemented in the field programmable gate arrays.A method of designing buffer schemes is proposed, which is based on the mapping of spatial synchronous data flows into local memory in the form of chains of pipeline registers.The method helpsto organize the data flow of at the input of built-in pipeline units of image processing, in which the data follow in a given order, andto minimize the amount of buffer memory.The method ensures the use of dynamically adjustable register delays built into the field programmable gate arrays, which increases the efficiency of buffering.Thismethod was tested during the development of an intelligent video camera. The embedded hardware implements a video image compression algorithm with a wide dynamic range according to the Retinexalgorithm. The same time it selects characteristic points in the image for the further pattern recognition.At the same time, multiple decimation of the frame is performed. Due to themultirate buffering of the image in the field programmable gate arrays,it was possible to avoid using of external dynamic memory
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Karkhanis, Tejas S., and James E. Smith. "Automated design of application specific superscalar processors." ACM SIGARCH Computer Architecture News 35, no. 2 (June 9, 2007): 402–11. http://dx.doi.org/10.1145/1273440.1250712.

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Jacome, M. F., and G. De Veciana. "Design challenges for new application specific processors." IEEE Design & Test of Computers 17, no. 2 (2000): 40–50. http://dx.doi.org/10.1109/54.844333.

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Doroshenko, A., and D. Ragozin. "Retargetable code generation for application-specific processors." Future Generation Computer Systems 21, no. 5 (May 2005): 679–85. http://dx.doi.org/10.1016/j.future.2004.05.008.

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Smith, Melissa C., and Kubilay Atasu. "Guest Editorial: Application Specific Processors and Architectures." Journal of Signal Processing Systems 77, no. 1-2 (August 7, 2014): 1–3. http://dx.doi.org/10.1007/s11265-014-0934-8.

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Palmer, R. P., and P. A. Rounce. "An architecture for application specific neural network processors." Computing & Control Engineering Journal 5, no. 6 (December 1, 1994): 260–64. http://dx.doi.org/10.1049/cce:19940603.

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Fei Sun, S. Ravi, A. Raghunathan, and N. K. Jha. "Application-specific heterogeneous multiprocessor synthesis using extensible processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (September 2006): 1589–602. http://dx.doi.org/10.1109/tcad.2005.858269.

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Dimond, R., O. Mencer, and W. Luk. "Application-specific customisation of multi-threaded soft processors." IEE Proceedings - Computers and Digital Techniques 153, no. 3 (2006): 173. http://dx.doi.org/10.1049/ip-cdt:20050177.

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Dissertations / Theses on the topic "Application specific processors"

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Mutigwe, Charles. "Automatic synthesis of application-specific processors." Thesis, Bloemfontein : Central University of Technology, Free State, 2012. http://hdl.handle.net/11462/163.

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Thesis (D. Tech. (Engineering: Electrical)) -- Central University of technology, Free State, 2012
This thesis describes a method for the automatic generation of appli- cation speci_c processors. The thesis was organized into three sepa- rate but interrelated studies, which together provide: a justi_cation for the method used, a theory that supports the method, and a soft- ware application that realizes the method. The _rst study looked at how modern day microprocessors utilize their hardware resources and it proposed a metric, called core density, for measuring the utilization rate. The core density is a function of the microprocessor's instruction set and the application scheduled to run on that microprocessor. This study concluded that modern day microprocessors use their resources very ine_ciently and proposed the use of subset processors to exe- cute the same applications more e_ciently. The second study sought to provide a theoretical framework for the use of subset processors by developing a generic formal model of computer architecture. To demonstrate the model's versatility, it was used to describe a number of computer architecture components and entire computing systems. The third study describes the development of a set of software tools that enable the automatic generation of application speci_c proces- sors. The FiT toolkit automatically generates a unique Hardware Description Language (HDL) description of a processor based on an application binary _le and a parameterizable template of a generic mi- croprocessor. Area-optimized and performance-optimized custom soft processors were generated using the FiT toolkit and the utilization of the hardware resources by the custom soft processors was character- ized. The FiT toolkit was combined with an ANSI C compiler and a third-party tool for programming _eld-programmable gate arrays (FPGAs) to create an unconstrained C-to-silicon compiler.
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Lau, C. H. "Computational structures for application specific VLSI processors." Thesis, University of Edinburgh, 1989. http://hdl.handle.net/1842/12396.

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Nyländen, T. (Teemu). "Application specific programmable processors for reconfigurable self-powered devices." Doctoral thesis, Oulun yliopisto, 2018. http://urn.fi/urn:isbn:9789526218755.

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Abstract The current Internet of Things solutions for simple measurement and monitoring tasks are evolving into ubiquitous sensor networks that are constantly observing both our well being and the conditions of our living environment. The oncoming omnipresent wireless infrastructure is expected to feature artificial intelligence capabilities that can interpret human actions, gestures and even needs. All of this will require processing power on a par with and energy efficiency far beyond that of the current mobile devices. The current Internet of Things devices rely mostly on commercial low power off-the-shelf micro-controllers. Optimized solely for low power, while paying little attention to computing performance, the present solutions are far from achieving the energy efficiency, let alone, the compute capability requirements of the future Internet of Things solutions. Since this domain is application specific by nature, the use of general purpose processors for signal processing tasks is counterintuitive. Instead, dedicated accelerator based solutions are more likely to be able to meet these strict demands. This thesis proposes one potential solution for achieving the necessary low energy, as well as the flexibility and performance requirements of the Internet of Things domain in a cost effective manner using reconfigurable heterogeneous processing solutions. A novel graphics processing unit-style accelerator for the Internet of Things application domain is presented. Since the accelerator can be reconfigured, it can be used for most applications of the Internet of Things domain, as well as other application domains. The solution is assessed using two computer vision applications, and is demonstrated to achieve an excellent combination of performance and energy efficiency. The accelerator is designed using an efficient and rapid co-design flow of software and hardware, featuring ease of development characteristics close to commercial off-the-shelf solutions, which also enables cost-efficient design flow
Tiivistelmä Esineiden internet tulee muuttamaan tulevaisuudessa elinympäristömme täysin. Se tulee mahdollistamaan interaktiiviset ympäristöt nykyisten passiivisten ympäristöjen sijaan. Lisäksi elinympäristömme tulee reagoimaan tekoihimme ja puheeseemme sekä myös tunteisiimme. Tämä kaikkialla läsnä olevan langaton infrastruktuuri tulee vaatimaan ennennäkemätöntä laskentatehokkuutta yhdistettynä äärimmäiseen energiatehokkuuteen. Nykyiset esineiden internet ratkaisut nojaavat lähes täysin kaupallisiin "suoraan hyllyltä" saataviin yleiskäyttöisiin mikrokontrollereihin. Ne ovat kuitenkin optimoituja pelkästään matalan tehonkulutuksen näkökulmasta, eivätkä niinkään energiatehokkuuden, saati tulevaisuuden esineiden internetin vaatiman laskentatehon suhteen. Kuitenkin esineiden internet on lähtökohtaisesti sovelluskohtaista laskentaa vaativa, joten yleiskäyttöisten prosessoreiden käyttö signaalinkäsittelytehtäviin on epäloogista. Sen sijaan sovelluskohtaisten kiihdyttimien käyttö laskentaan, todennäköisesti mahdollistaisi tavoitellun vaatimustason saavuttamisen. Tämä väitöskirja esittelee yhden mahdollisen ratkaisun matalan energian kulutuksen, korkean suorituskyvyn ja joustavuuden yhdenaikaiseen saavuttamiseen kustannustehokkaalla tavalla, käyttäen uudelleenkonfiguroitavia heterogeenisiä prosessoriratkaisuja. Työssä esitellään uusi grafiikkaprosessori-tyylinen uudelleen konfiguroitava kiihdytin esineiden internet sovellusalueelle, jota pystytään hyödyntämään useimpien laskentatehoa vaativien sovellusten kanssa. Ehdotetun kiihdyttimen ominaisuuksia arvioidaan kahta konenäkösovellusta esimerkkinä käyttäen ja osoitetaan sen saavuttavan loistavan yhdistelmän energia tehokkuutta ja suorituskykyä. Kiihdytin suunnitellaan käyttäen tehokasta ja nopeaa ohjelmiston ja laitteiston yhteissuunnitteluketjua, jolla voidaan saavuttaa lähestulkoon kaupallisten "suoraan hyllyltä" saatavien prosessoreiden kehitystyön helppous, joka puolestaan mahdollistaa kustannustehokkaan kehitys- ja suunnittelutyön
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Glökler, Tilman Meyr Heinrich. "Design of energy-efficient application-specific instruction set processors /." Boston, Mass. [u.a.] : Kluwer Acad. Publ, 2004. http://www.loc.gov/catdir/enhancements/fy0820/2004041376-d.html.

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Hautala, I. (Ilkka). "From dataflow models to energy efficient application specific processors." Doctoral thesis, Oulun yliopisto, 2019. http://urn.fi/urn:isbn:9789526223681.

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Abstract The development of wireless networks has provided the necessary conditions for several new applications. The emergence of the virtual and augmented reality and the Internet of things and during the era of social media and streaming services, various demands related to functionality and performance have been set for mobile and wearable devices. Meeting these demands is complicated due to minimal energy budgets, which are characteristic of embedded devices. Lately, the energy efficiency of devices has been addressed by increasing parallelism and the use of application-specific hardware resources. This has been hindered by hardware development as well as software development because the conventional development methods are based on the use of low-level abstractions and sequential programming paradigms. On the other hand, deployment of high-level design methods is slowed down because of final solutions that are too much compromised when energy efficiency and performance are considered. This doctoral thesis introduces a model-driven framework for the development of signal processing systems that facilitates hardware and software co-design. The design flow exploits an easily customizable, re-programmable and energy-efficient processor template. The proposed design flow enables tailoring of multiple heterogeneous processing elements and the connections between them to the demands of an application. Application software is described by using high-level dataflow models, which enable the automatic synthesis of parallel applications for different multicore hardware platforms and speed up design space exploration. Suitability of the proposed design flow is demonstrated by using three different applications from different signal processing domains. The experiments showed that raising the level of abstraction has only a minor impact on performance. Video processing algorithms are selected to be the main application area in this thesis. The thesis proposes tailored and reprogrammable energy-efficient processing elements for video coding algorithms. The solutions are based on the use of multiple processing elements by exploiting the pipeline parallelism of the application, which is characteristic of many signal processing algorithms. Performance, power and area metrics for the designed solutions have been obtained using post-layout simulation models. In terms of energy efficiency, the proposed programmable processors form a new compromise solution between fixed hardware accelerators and conventional embedded processors for video coding
Tiivistelmä Langattomien verkkojen kehittyminen on luonut edellytykset useille uusille sovelluksille. Muiden muassa sosiaalisen media, suoratoistopalvelut, virtuaalitodellisuus ja esineiden internet asettavat kannettaville ja puettaville laitteille moninaisia toimintoihin, suorituskykyyn, energiankulutukseen ja fyysiseen muotoon liittyviä vaatimuksia. Yksi isoimmista haasteista on sulautettujen laitteiden energiankulutus. Laitteiden energiatehokkuutta on pyritty parantamaan rinnakkaislaskentaa ja räätälöityjä laskentaresursseja hyödyntämällä. Tämä puolestaan on vaikeuttanut niin laite- kuin sovelluskehitystä, koska laajassa käytössä olevat kehitystyökalut perustuvat matalan tason abstraktioihin ja hyödyntävät alun perin yksi ydinprosessoreille suunniteltuja ohjelmointikieliä. Korkean tason ja automatisoitujen kehitysmenetelmien käyttöönottoa on hidastanut aikaansaatujen järjestelmien puutteellinen suorituskyky ja laiteresurssien tehoton hyödyntäminen. Väitöskirja esittelee datavuopohjaiseen suunnitteluun perustuvan työkaluketjun, joka on tarkoitettu energiatehokkaiden signaalikäsittelyjärjestelmien toteuttamiseen. Työssä esiteltävä suunnitteluvuo pohjautuu laitteistoratkaisuissa räätälöitävään ja ohjelmoitavaan siirtoliipaistavaan prosessoritemplaattiin. Ehdotettu suunnitteluvuo mahdollistaa useiden heterogeenisten prosessoriytimien ja niiden välisten kytkentöjen räätälöimisen sovelluksien tarpeiden vaatimalla tavalla. Suunnitteluvuossa ohjelmistot kuvataan korkean tason datavuomallien avulla. Tämä mahdollistaa erityisesti rinnakkaista laskentaa sisältävän ohjelmiston automaattisen sovittamisen erilaisiin moniprosessorijärjestelmiin ja nopeuttaa erilaisten järjestelmätason ratkaisujen kartoittamista. Suunnitteluvuon käyttökelpoisuus osoitetaan käyttäen esimerkkinä kolmea eri signaalinkäsittelysovellusta. Tulokset osoittavat, että suunnittelumenetelmien abstraktiotasoa on mahdollista nostaa ilman merkittävää suorituskyvyn heikkenemistä. Väitöskirjan keskeinen sovellusalue on videonkoodaus. Työ esittelee videonkoodaukseen suunniteltuja energiatehokkaita ja uudelleenohjelmoitavia prosessoriytimiä. Ratkaisut perustuvat usean prosessoriytimen käyttämiseen hyödyntäen erityisesti videonkäsittelyalgoritmeille ominaista liukuhihnarinnakkaisuutta. Prosessorien virrankulutus, suorituskyky ja pinta-ala on analysoitu käyttämällä simulointimalleja, jotka huomioivat logiikkasolujen sijoittelun ja johdotuksen. Ehdotetut sovelluskohtaiset prosessoriratkaisut tarjoavat uuden energiatehokkaan kompromissiratkaisun tavanomaisten ohjelmoitavien prosessoreiden ja kiinteästi johdotettujen video-kiihdyttimien välille
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Sohl, Joar. "Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories." Doctoral thesis, Linköpings universitet, Datorteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-113702.

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Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced. Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs. Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow. More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain? Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance  with power efficiency and silicon cost that is comparable to ASICs. The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously. One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software. Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed. This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to generate code from.
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Franz, Jonathan D. Duren Russell Walker. "An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors." Waco, Tex. : Baylor University, 2008. http://hdl.handle.net/2104/5254.

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Lim, Wei Ming. "Design of application specific instruction set processors for the domain of GF(2'm)." Thesis, University of Sheffield, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.412439.

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Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

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Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.
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Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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Books on the topic "Application specific processors"

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Swartzlander, Earl E. Application Specific Processors. Boston, MA: Springer US, 1996.

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Swartzlander, Earl E., ed. Application Specific Processors. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4613-1457-8.

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E, Swartzlander Earl, ed. Application specific processors. Boston: Kluwer Academic, 1997.

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Embedded DSP processor design: Application specific instruction set processors. Amsterdam: Morgan Kaufmann, 2008.

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1952-, Richards M. A., Gadient Anthony J. 1960-, and Frank Geoffrey A. 1948-, eds. Rapid prototyping of application specific signal processors. Boston: Kluwer Academic Publishers, 1997.

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Plaks, Toomas P. Piecewise regular arrays: Application-specific computations. Australia: Gordon and Breach Science, 1999.

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Calif.) IEEE Symposium on Application Specific Processors (2008 Anaheim. 2008 Symposium on Application specific Processors: Anaheim, CA, 8-9 June 2008. Piscataway, NJ: IEEE, 2008.

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Lekkas, Panos C. Network Processors. New York: McGraw-Hill, 2007.

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International Conference on Application Specific Array Processors. (1993 Venice, Italy). Proceedings: The International Conference on Application Specific Array Processors : October 25-27, 1993, Venice, Italy. Los Alamitos, Calif: IEEE Computer Society, 1993.

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International Conference on Application Specific Array Processors. (8th 1994 San Francisco, Calif.). The International Conference on Application Specific Array Processors, August 22-24, 1994, San Francisco, California: Proceedings. Los Alamitos, Calif: IEEE Computer Society Press, 1994.

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Book chapters on the topic "Application specific processors"

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Mitra, Tulika. "Application-Specific Processors." In Handbook of Hardware/Software Codesign, 377–409. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_13.

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Mitra, Tulika. "Application-Specific Processors." In Handbook of Hardware/Software Codesign, 1–33. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_13-1.

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Henkel, Jörg, Sri Parameswaran, and Newton Cheung. "Application-Specific Embedded Processors." In Designing Embedded Processors, 3–23. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_1.

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Liu, Dake, and Jian Wang. "Application Specific Instruction Set DSP Processors." In Handbook of Signal Processing Systems, 671–706. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6859-2_21.

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Liu, Dake. "Application Specific Instruction Set DSP Processors." In Handbook of Signal Processing Systems, 415–47. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6345-1_16.

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Qin, Wei, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David August, Kurt Keutzer, Sharad Malik, and Li-Shiuan Peh. "Design Tools for Application Specific Embedded Processors." In Embedded Software, 319–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45828-x_24.

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Ferger, Max, and Michael Hübner. "Instruction Set Optimization for Application Specific Processors." In Lecture Notes in Computer Science, 268–74. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05960-0_28.

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Sergiyenko, Anatolij, Oleg Maslennikow, Piotr Ratuszniak, Natalia Maslennikowa, and Adam Tomas. "Application Specific Processors for the Autoregressive Signal Analysis." In Parallel Processing and Applied Mathematics, 80–86. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-14390-8_9.

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Labrecque, Martin, Mark Jeffrey, and J. Gregory Steffan. "Application-Specific Signatures for Transactional Memory in Soft Processors." In Lecture Notes in Computer Science, 42–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12133-3_7.

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Cao, Zhen, Yuan Dong, and Shengyuan Wang. "Compiler Backend Generation for Application Specific Instruction Set Processors." In Programming Languages and Systems, 121–36. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-25318-8_12.

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Conference papers on the topic "Application specific processors"

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Rashid, Muhammad, Ludovic Apvrille, and Renaud Pacalet. "Application Specific Processors for Multimedia Applications." In 2008 IEEE 11th International Conference on Computational Science and Engineering (CSE). IEEE, 2008. http://dx.doi.org/10.1109/cse.2008.26.

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"Session 6: Application-specific processors." In 2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2010. http://dx.doi.org/10.1109/asap.2010.5540990.

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Stechele, Walter. "Session 3: Application-specific processors." In 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, 2015. http://dx.doi.org/10.1109/dasip.2015.7367248.

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Kim, Kyosun, Ramesh Karri, and Miodrag Potkonjak. "Synthesis of application specific programmable processors." In the 34th annual conference. New York, New York, USA: ACM Press, 1997. http://dx.doi.org/10.1145/266021.266164.

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Goodwin, David, and Darin Petkov. "Automatic generation of application specific processors." In the international conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/951710.951730.

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Hinkelmann, Heiko, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Gotz Kappen, and Tobias G. Noll. "SPP1148 booth: Application-specific reconfigurable processors." In 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4629958.

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Ali, Muhammad, and Diana Gohringer. "Application Specific Instruction-Set Processors for Machine Learning Applications." In 2022 International Conference on Field-Programmable Technology (ICFPT). IEEE, 2022. http://dx.doi.org/10.1109/icfpt56656.2022.9974187.

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Lin, Hai, Guangyu Sun, Yunsi Fei, Yuan Xie, and Anand Sivasubramaniam. "Thermal-aware Design Considerations for Application-Specific Instruction Set Processor." In 2008 Symposium on Application Specific Processors (SASP). IEEE, 2008. http://dx.doi.org/10.1109/sasp.2008.4570787.

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Huang, Po-Kuan, Matin Hashemi, and Soheil Ghiasi. "System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis." In 2008 Symposium on Application Specific Processors (SASP). IEEE, 2008. http://dx.doi.org/10.1109/sasp.2008.4570792.

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Auguin, M., F. Boeri, C. Carriere, and G. Menez. "Incremental synthesis of application domain specific processors." In Proceedings of ICASSP '93. IEEE, 1993. http://dx.doi.org/10.1109/icassp.1993.319146.

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Reports on the topic "Application specific processors"

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LOCKHEED SANDERS INC NASHUA NH. Rapid Prototyping of Application Specific Signal Processors (RASSP). Fort Belvoir, VA: Defense Technical Information Center, December 1994. http://dx.doi.org/10.21236/ada293290.

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Agule, George J., Stephen M. Lorusso, Kelley J. Arsenault, Paul N. Bompastore, and Robert V. Bryant. Rapid Prototyping of Application Specific Signal Processors (RASSP). Fort Belvoir, VA: Defense Technical Information Center, October 1992. http://dx.doi.org/10.21236/ada256251.

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LOCKHEED SANDERS INC NASHUA NH. Rapid Prototyping of Application Specific Signal Processors (RASSP). Fort Belvoir, VA: Defense Technical Information Center, December 1993. http://dx.doi.org/10.21236/ada274324.

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Gadient, Anthony, Mark A. Richards, and Geoffrey A. Frank. Rapid-Prototyping of Application Specific Signal Processors (RASSP) Education and Facilitation. Fort Belvoir, VA: Defense Technical Information Center, December 2000. http://dx.doi.org/10.21236/ada417705.

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Pag, F., M. Jesper, U. Jordan, W. Gruber-Glatzl, and J. Fluch. Reference applications for renewable heat. IEA SHC Task 64, January 2021. http://dx.doi.org/10.18777/ieashc-task64-2021-0002.

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There is a high degree of freedom and flexibility in the way to integrate renewable process heat in industrial processes. Nearly in every industrial or commercial application various heat sinks can be found, which are suitable to be supplied by renewable heat, e.g. from solar thermal, heat pumps, biomass or others. But in contrast to conventional fossil fuel powered heating systems, most renewable heating technologies are more sensitive to the requirements defined by the specific demand of the industrial company. Fossil fuel-based systems benefit from their indifference to process temperatures in terms of energy efficiency, their flexibility with respect to part-load as well as on-off operation, and the fuel as a (unlimited) chemical storage. In contrast, the required temperature and the temporal course of the heat demand over the year determine whether a certain regenerative heat generator is technically feasible at all or at least significantly influence parameters like efficiency or coverage rate.
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Bobashev, Georgiy, John Holloway, Eric Solano, and Boris Gutkin. A Control Theory Model of Smoking. RTI Press, June 2017. http://dx.doi.org/10.3768/rtipress.2017.op.0040.1706.

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We present a heuristic control theory model that describes smoking under restricted and unrestricted access to cigarettes. The model is based on the allostasis theory and uses a formal representation of a multiscale opponent process. The model simulates smoking behavior of an individual and produces both short-term (“loading up” after not smoking for a while) and long-term smoking patterns (e.g., gradual transition from a few cigarettes to one pack a day). By introducing a formal representation of withdrawal- and craving-like processes, the model produces gradual increases over time in withdrawal- and craving-like signals associated with abstinence and shows that after 3 months of abstinence, craving disappears. The model was programmed as a computer application allowing users to select simulation scenarios. The application links images of brain regions that are activated during the binge/intoxication, withdrawal, or craving with corresponding simulated states. The model was calibrated to represent smoking patterns described in peer-reviewed literature; however, it is generic enough to be adapted to other drugs, including cocaine and opioids. Although the model does not mechanistically describe specific neurobiological processes, it can be useful in prevention and treatment practices as an illustration of drug-using behaviors and expected dynamics of withdrawal and craving during abstinence.
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Холошин, Ігор Віталійович, Ірина Миколаївна Варфоломєєва, Олена Вікторівна Ганчук, Ольга Володимирівна Бондаренко, and Андрій Валерійович Пікільняк. Pedagogical techniques of Earth remote sensing data application into modern school practice. CEUR-WS.org, 2018. http://dx.doi.org/10.31812/123456789/3257.

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Abstract. The article dwells upon the Earth remote sensing data as one of the basic directions of Geo-Information Science, a unique source of information on processes and phenomena occurring in almost all spheres of the Earth geographic shell (atmosphere, hydrosphere, lithosphere, etc.). The authors argue that the use of aerospace images by means of the information and communication technologies involvement in the learning process allows not only to increase the information context value of learning, but also contributes to the formation of students’ cognitive interest in such disciplines as geography, biology, history, physics, computer science, etc. It has been grounded that remote sensing data form students’ spatial, temporal and qualitative concepts, sensory support for the perception, knowledge and explanation of the specifics of objects and phenomena of geographical reality, which, in its turn, provides an increase in the level of educational achievements. The techniques of aerospace images application into the modern school practice have been analyzed and illustrated in the examples: from using them as visual aids, to realization of practical and research orientation of training on the basis of remote sensing data. Particular attention is paid to the practical component of the Earth remote sensing implementation into the modern school practice with the help of information and communication technologies.
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Kholoshyn, Ihor V., Iryna M. Varfolomyeyeva, Olena V. Hanchuk, Olga V. Bondarenko, and Andrey V. Pikilnyak. Pedagogical techniques of Earth remote sensing data application into modern school practice. [б. в.], September 2019. http://dx.doi.org/10.31812/123456789/3262.

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The article dwells upon the Earth remote sensing data as one of the basic directions of Geo-Information Science, a unique source of information on processes and phenomena occurring in almost all spheres of the Earth geographic shell (atmosphere, hydrosphere, lithosphere, etc.). The authors argue that the use of aerospace images by means of the information and communication technologies involvement in the learning process allows not only to increase the information context value of learning, but also contributes to the formation of students’ cognitive interest in such disciplines as geography, biology, history, physics, computer science, etc. It has been grounded that remote sensing data form students’ spatial, temporal and qualitative concepts, sensory support for the perception, knowledge and explanation of the specifics of objects and phenomena of geographical reality, which, in its turn, provides an increase in the level of educational achievements. The techniques of aerospace images application into the modern school practice have been analyzed and illustrated in the examples: from using them as visual aids, to realization of practical and research orientation of training on the basis of remote sensing data. Particular attention is paid to the practical component of the Earth remote sensing implementation into the modern school practice with the help of information and communication technologies.
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Suir, Glenn, Molly Reif, and Christina Saltus. Remote sensing capabilities to support EWN® projects : an R&D approach to improve project efficiencies and quantify performance. Engineer Research and Development Center (U.S.), August 2022. http://dx.doi.org/10.21079/11681/45241.

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Engineering With Nature (EWN®) is a US Army Corps of Engineers (USACE) Initiative and Program that promotes more sustainable practices for delivering economic, environmental, and social benefits through collaborative processes. As the number and variety of EWN® projects continue to grow and evolve, there is an increasing opportunity to improve how to quantify their benefits and communicate them to the public. Recent advancements in remote sensing technologies are significant for EWN® because they can provide project-relevant detail across a large areal extent, in which traditional survey methods may be complex due to site access limitations. These technologies encompass a suite of spatial and temporal data collection and processing techniques used to characterize Earth's surface properties and conditions that would otherwise be difficult to assess. This document aims to describe the general underpinnings and utility of remote sensing technologies and applications for use: (1) in specific phases of the EWN® project life cycle; (2) with specific EWN® project types; and (3) in the quantification and assessment of project implementation, performance, and benefits.
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Eshed, Yuval, and John Bowman. Harnessing Fine Scale Tuning of Endogenous Plant Regulatory Processes for Manipulation of Organ Growth. United States Department of Agriculture, 2005. http://dx.doi.org/10.32747/2005.7696519.bard.

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Background and objectives: Manipulation of plant organ growth is one of the primary reasons for the success of mankind allowing increasing amounts of food for human and livestock consumption. In contrast with the successful selection for desirable growth characteristics using plant breeding, transgenic manipulations with single genes has met limited success. While breeding is based on accumulation of many small alterations of growth, usually arise from slight changes in expression patterns, transgenic manipulations are primarily based on drastic, non-specific up-regulation or knock down of genes that can exert different effects during different stages of development. To successfully harness transgenic manipulation to attain desirable plant growth traits we require the tools to subtly regulate the temporal and spatial activity of plant growth genes. Polar morphology along the adaxial/abaxial axis characterizes lateral organs of all plants. Juxtaposition of two cell types along this axis is a prerequisite of laminar growth induction. In the study summarized here, we addressed the following questions: Can we identify and harness components of the organ polarity establishment pathway for prolonged growth? Can we identify specific regulatory sequences allowing spatial and temporal manipulation in various stages of organ development? Can we identify genes associated with YABBY-induced growth alterations? Major conclusions and implications: We showed that regulated expression, both spatially and temporally of either organ polarity factors such as the YABBY genes, or the organ maturation program such as the CIN-TCPs can stimulate substantial growth of leaves and floral organs. Promoters for such fine manipulation could be identified by comparison of non-coding sequences of KAN1, where a highly conserved domain was found within the second intron, or by examination of multiple 5” regions of genes showing transient expression along leaf ontogeny. These promoters illustrate the context dependent action of any gene we examined thus far, and facilitate fine tuning of the complex growth process. Implications, both scientific and agricultural. The present study was carried out on the model organism Arabidopsis, and the broad application of its findings were tested in the tomato crop. We learned that all central regulators of organ polarity are functionally conserved, probably in all flowering plants. Thus, with minor modifications, the rules and mechanisms outlined in this work are likely to be general.
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