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Journal articles on the topic 'Application-specific integrated circuits'

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Published: 4 June 2021
Last updated: 29 July 2024

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1

Mijuskovic, Dejan. "Clock distribution in application specific integrated circuits." Microelectronics Journal 18, no. 4 (July 1987): 15–27. http://dx.doi.org/10.1016/s0026-2692(87)80370-1.

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2

J A, Akshay. "Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 4047–58. http://dx.doi.org/10.22214/ijraset.2023.52570.

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Abstract Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.
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3

Jiménez Flores, Armando, Maximino Peña Guerrero, and Jose J. Negrete Redondo. "Application‐specific integrated circuits based on reconfigurable logic." Journal of the Acoustical Society of America 128, no. 4 (October 2010): 2381. http://dx.doi.org/10.1121/1.3508470.

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4

Davison, Chris. "The test needs of application-specific integrated circuits." Quality and Reliability Engineering International 2, no. 3 (July 1986): 159–64. http://dx.doi.org/10.1002/qre.4680020305.

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5

Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.
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6

York, Trevor A. "Book Review: An Introduction to Application Specific Integrated Circuits." International Journal of Electrical Engineering & Education 29, no. 3 (July 1992): 276. http://dx.doi.org/10.1177/002072099202900314.

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7

Tonge, J. D. "The Design Process for Application Specific Integrated Circuits (ASICS)." Microelectronics International 6, no. 1 (January 1989): 5–7. http://dx.doi.org/10.1108/eb044349.

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8

Penn, M. G. "Impact and opportunities for application specific integrated circuits (ASICs)." IEE Proceedings E Computers and Digital Techniques 132, no. 2 (1985): 130. http://dx.doi.org/10.1049/ip-e.1985.0019.

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9

Penn, M. G. "Impact and opportunities for application specific integrated circuits (ASICs)." IEE Proceedings I Solid State and Electron Devices 132, no. 2 (1985): 130. http://dx.doi.org/10.1049/ip-i-1.1985.0026.

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10

He, Qi. "Advanced Integrated Circuit Manufacturing Technology Process Industry Development." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 402–7. http://dx.doi.org/10.54097/hset.v71i.14606.

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Integrated circuits are circuits with specific functions that are integrated together by semiconductor processes and are a new type of semiconductor device developed in the late 1950s through the 1960s. Integrated circuits are the foundation of information development and the benchmark for high quality development of national economy. This paper introduces the concept of integrated circuits as well as the integrated circuit process, and the application areas of integrated circuits, which account for an expanding and growing share of information, communication, consumer electronics, automotive electronics, medical electronics and other consumer areas. It discusses China's future IC process development path by combining the IC production process and design process, industrial development, design process and preparation limitations, and proposes relevant suggestions and strategies by speculating on the future development of the process.
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11

DJAHANSHAHI, HORMOZ, MAJID AHMADI, GRAHAM A. JULLIEN, and WILLIAM C. MILLER. "NEURAL NETWORK INTEGRATED CIRCUITS WITH SINGLE-BLOCK MIXED SIGNAL ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (October 1998): 589–604. http://dx.doi.org/10.1142/s0218126698000377.

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This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular Arrays of a nonlinearly-loaded multiplier block form the core of multi-layer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Salient features of the present architecture, such as modularity and reduced interconnection problems and areas are highlighted and circuit design and improvements are presented for its universal building block. Other design issues such as supply voltage and power reduction and pin limitations are discussed together with experimental results.
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12

Abraitis, Vidas, and Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA." Solid State Phenomena 144 (September 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.

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Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.
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13

Evmorfopoulos, N. E., and J. N. Avaritsiotis. "An Adaptive Digital Fuzzy Architecture for Application-Specific Integrated Circuits." Active and Passive Electronic Components 25, no. 4 (2002): 289–306. http://dx.doi.org/10.1080/08827510214374.

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A generic fuzzy logic system implementation in digital hardware is presented in this paper. The architecture developed is oriented to Application-Specific Integrated Circuits (ASICs), and its functionality is demonstrated through a typical ASIC for a simple control application. Furthermore, a distributed adaptation scheme is proposed for real-time environments. Performance/area tradeoffs for VLSI implementation are also discussed.
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14

Lachartre, D., and F. Feinstein. "Application specific integrated circuits for ANTARES offshore front-end electronics." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 442, no. 1-3 (March 2000): 99–104. http://dx.doi.org/10.1016/s0168-9002(99)01205-x.

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15

Renner, F. M., K. J. Hoffmann, R. Markert, and M. Glesner. "Design methodology of application specific integrated circuits for mechatronic systems." Microprocessors and Microsystems 24, no. 2 (April 2000): 95–103. http://dx.doi.org/10.1016/s0141-9331(99)00071-x.

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16

Usenko, E. A. "Modern Application-Specific Integrated Circuits for Resistive Plate Chambers (Review)." Instruments and Experimental Techniques 65, no. 6 (December 2022): 865–77. http://dx.doi.org/10.1134/s0020441222050293.

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17

Maria, Marti. "Prelinearization Stages on Color-Management Application-Specific Integrated Circuits (ASICs)." NIP & Digital Fabrication Conference 24, no. 1 (January 1, 2008): 627–30. http://dx.doi.org/10.2352/issn.2169-4451.2008.24.1.art00044_2.

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18

Basiladze, S. G. "Application specific integrated circuits for ionizing-radiation detectors (review, part 1)." Instruments and Experimental Techniques 59, no. 1 (January 2016): 1–52. http://dx.doi.org/10.1134/s0020441216010280.

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19

Basiladze, S. G. "Application specific integrated circuits in radiation measuring systems (Review, Part 2)." Instruments and Experimental Techniques 59, no. 2 (March 2016): 163–95. http://dx.doi.org/10.1134/s0020441216020305.

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20

Piso, D., and P. Veiga-Crespo. "Application specific integrated circuits in implantable sensors for monitoring intraocular pressure." Archivos de la Sociedad Española de Oftalmología (English Edition) 86, no. 10 (October 2011): 311–13. http://dx.doi.org/10.1016/j.oftale.2012.02.007.

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21

Ismaeel, A. A., R. Mathew, and T. John. "Structurally self-testable data path synthesis of application specific integrated circuits." Computers & Electrical Engineering 22, no. 4 (July 1996): 275–91. http://dx.doi.org/10.1016/0045-7906(96)00006-7.

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22

Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, and Scott Morton. "Low-level logic fault testing ASIC simulation environment." World Journal of Engineering 11, no. 3 (June 1, 2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.

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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.
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23

Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (November 17, 2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of CMOS device, and the combined circuit design and sequential logic circuit design principle of dynamic and static CMOS are explained in detail. Then, the application principle of CMOS technology in GPU is analyzed, and its specific application in GPU acceleration algorithm is analyzed. Finally, the application of CMOS technology in integrated circuits and its application and acceleration effect are summarized.
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24

Piso, Daniel, Patricia Veiga-Crespo, and Elena Vecino. "Modern Monitoring Intraocular Pressure Sensing Devices Based on Application Specific Integrated Circuits." Journal of Biomaterials and Nanobiotechnology 03, no. 02 (2012): 301–9. http://dx.doi.org/10.4236/jbnb.2012.322037.

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25

Abbasi. "APPLICATION SPECIFIC INTEGRATED CIRCUITS DESIGN AND IMPLEMENTATION OF RADEMACHER AND WALSH FUNCTIONS." American Journal of Engineering and Applied Sciences 6, no. 4 (April 1, 2013): 360–68. http://dx.doi.org/10.3844/ajeassp.2013.360.368.

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26

Baze, M. P., W. G. Bartholet, J. C. Braatz, and T. A. Dao. "Single event upset test structures for digital CMOS application specific integrated circuits." IEEE Transactions on Nuclear Science 40, no. 6 (1993): 1703–8. http://dx.doi.org/10.1109/23.273490.

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27

Saeki, T., K. Minami, H. Yoshida, and H. Suzuki. "A direct-skew-detect synchronous mirror delay for application-specific integrated circuits." IEEE Journal of Solid-State Circuits 34, no. 3 (March 1999): 372–79. http://dx.doi.org/10.1109/4.748189.

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28

Zhao, Chun, Ce Zhou Zhao, and Bin Da. "A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools." Advanced Materials Research 569 (September 2012): 273–76. http://dx.doi.org/10.4028/www.scientific.net/amr.569.273.

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The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.
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29

Ilijin, Sandra, and Predrag Petkovic. "Implementation of control logic in the scoreboard of tennis." Serbian Journal of Electrical Engineering 12, no. 2 (2015): 219–36. http://dx.doi.org/10.2298/sjee1502219i.

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This paper presents one original solution of control logic for scoreboard in tennis match. The main goal is to simplify the process of recording points. Instead of using six buttons the chair umpire (referee) will use only two control buttons or a joystick to assign a point to a player. The proposed system takes care of all other data processing. The system is designed in Application Specific Integrated Circuits (ASIC) and Standard Application Specific Integrated Circuits (SASIC) technology to demonstrate similarities and differences between two design technologies. Finally it is realized on FPGA type EP2C35F672C6 from Cyclone II Altera?s family.
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30

Paraskevopoulos, D. E., and C. F. Fey. "Studies in LSI technology economics. III. Design schedules for application-specific integrated circuits." IEEE Journal of Solid-State Circuits 22, no. 2 (April 1987): 223–29. http://dx.doi.org/10.1109/jssc.1987.1052706.

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31

Bouldin, D., W. Snapp, P. Haug, D. Sunderland, R. Brees, C. Sechen, and W. Dai. "ASIC by Design - Automated design of digital signal processing application-specific integrated circuits." IEEE Circuits and Devices Magazine 20, no. 4 (July 2004): 17–21. http://dx.doi.org/10.1109/mcd.2004.1317946.

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32

Rodrigues, Francisco, Carla Rodrigues, João Santos, Cláudio Rodrigues, and António Teixeira. "Photonic Integrated Circuits for Passive Optical Networks: Outlook and Case Study of Integrated Quasi-Coherent Receiver." Photonics 10, no. 2 (February 8, 2023): 182. http://dx.doi.org/10.3390/photonics10020182.

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Photonic Integrated Circuits (PICs) are taking a major role in the telecommunications and datacenter markets. The increased complexity of coexisting and fast evolving standards for Passive Optical Networks (PONs) suggests the introduction of PICs will be the next step in PON related optoelectronics. The PICs ecosystem has greatly matured in the past years, becoming a solution that can cope with the requirements of industry and academia, and presenting the flexibility of combining multiple platforms available towards viable commercial solutions. In this review, the evolution of PONs and PICs is presented, with a focus on the optoelectronic integration of PICs for PONs and coherent PONs. To demonstrate the potential of PICs and their combination with electronics, a quasi-coherent receiver based on co-hosted PIC and Application Specific Integrated Circuit (ASIC) is presented and characterized.
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33

Kadlubowski, L. A., and P. Kmon. "Multichannel integrated circuit for time-based measurements in 28 nm CMOS." Journal of Instrumentation 19, no. 02 (February 1, 2024): C02004. http://dx.doi.org/10.1088/1748-0221/19/02/c02004.

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Abstract This paper discusses the application-specific integrated circuit prototype dedicated to readout of hybrid pixel X-ray detectors. The circuit is fabricated in 28 nm CMOS technology and occupies 1.1 × 1.1 mm2 of silicon area. Each of 8 × 4 pixels present in the prototype includes an analog front-end and a digital block with two ring oscillators and their supporting circuits. The circuit can operate in single-photon counting mode or time-based measurement mode. The paper discusses in detail the design decisions that influenced the final in-pixel ring oscillator architecture and layout. Measurement results are presented which demonstrate the performance of ring oscillators as well as regular operating modes of the chip: single photon counting and time-over-threshold measurement.
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34

Lee, Min Su, and Hee Chul Lee. "Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits." Journal of the Korean Physical Society 61, no. 10 (November 2012): 1670–74. http://dx.doi.org/10.3938/jkps.61.1670.

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35

Seitz, Peter. "Smart sensing using custom photo-application-specific integrated circuits and charge-coupled device technology." Optical Engineering 34, no. 8 (August 1, 1995): 2299. http://dx.doi.org/10.1117/12.200595.

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36

Allman, S. A., A. M. Gole, A. Neufeld, and E. Dirks. "Application specific integrated circuits for the transformation from three phase AC to DQZ coordinates." IEEE Transactions on Power Delivery 3, no. 4 (1988): 1523–29. http://dx.doi.org/10.1109/61.193951.

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37

Fey, C. F., and D. E. Paraskevopoulos. "A techno-economic assessment of application-specific integrated circuits: Current status and future trends." Proceedings of the IEEE 75, no. 6 (1987): 829–41. http://dx.doi.org/10.1109/proc.1987.13804.

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38

Ikedo, Tsuneo. "Design and performance evaluation of a pixel cache implemented within application- specific integrated circuits." Visual Computer 12, no. 5 (June 1, 1996): 215–33. http://dx.doi.org/10.1007/s003710050060.

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39

Jain, V., D. Pramanik, M. Weling, C. Gabriel, D. Baker, W. Boardman, and J. Eakin. "A 0.6 micron triple level metal process for high performance application specific integrated circuits." Microelectronics Journal 25, no. 4 (June 1994): xviii—xxv. http://dx.doi.org/10.1016/0026-2692(94)90174-0.

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40

Ikedo, Tsuneo. "Design and performance evaluation of a pixel cache implemented within application-specific integrated circuits." Visual Computer 12, no. 5 (May 1996): 215–33. http://dx.doi.org/10.1007/bf01782236.

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41

Paramasivam, Rengaprabhu, Venkatasubramanian Adhinarayanan, and Seetharaman Gopalakrishnan. "Field Programmable Gate Arrays and Application Specific Integrated Circuits Implementation of COordinate Rotation DIgital Computer Using Wave-Pipelined Circuits." Advanced Science Letters 20, no. 10 (October 1, 2014): 2234–38. http://dx.doi.org/10.1166/asl.2014.5706.

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42

Siddesh, K. B., S. Roopa, Parveen B. A. Farzana, and T. Tanuja. "Design of duty cycle correction circuit using ASIC implementation for high speed communication." i-manager’s Journal on Electronics Engineering 13, no. 3 (2023): 33. http://dx.doi.org/10.26634/jele.13.3.19969.

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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.
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43

Kavehei, O., A. Iqbal, Y. S. Kim, K. Eshraghian, S. F. Al-Sarawi, and D. Abbott. "The fourth element: characteristics, modelling and electromagnetic theory of the memristor." Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 466, no. 2120 (March 17, 2010): 2175–202. http://dx.doi.org/10.1098/rspa.2009.0553.

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In 2008, researchers at the Hewlett–Packard (HP) laboratories published a paper in Nature reporting the development of a new basic circuit element that completes the missing link between charge and flux linkage, which was postulated by Chua in 1971 (Chua 1971 IEEE Trans. Circuit Theory 18 , 507–519 ( doi:10.1109/TCT.1971.1083337 )). The HP memristor is based on a nanometre scale TiO 2 thin film, containing a— doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and non-volatile RAM, they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application-specific integrated circuits and field programmable gate arrays. A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for integrated circuits. This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell’s equations. We also review Chua’s arguments based on electromagnetic theory.
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44

Pinho, Cátia, Francisco Rodrigues, Ana Maia Tavares, Carla Rodrigues, Cláudio Emanuel Rodrigues, and António Teixeira. "Photonic Integrated Circuits for NGPON2 ONU Transceivers (Invited)." Applied Sciences 10, no. 11 (June 10, 2020): 4024. http://dx.doi.org/10.3390/app10114024.

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The development of photonic integrated circuits (PIC) for access network applications, such as passive optical networks (PON), constitutes a very attractive ecosystem due to PON’s potential mass market. The implementation of PIC solutions in this context is expected to facilitate the possibility of increasing the complexity and functionalities of devices at a potentially lower cost. We present a review addressing the prominent access network market requirements and the main restrictions stemming from its specific field of application. Higher focus is given to PON devices for the optical network unit (ONU) and the implications of designing a device ready for market by discussing its various perspectives in terms of technology and cost. The discussed PIC solutions/approaches in this paper are mainly based on indium phosphide (InP) technology, due to its monolithic integration capabilities. A comprehensive set of guidelines considering the current technology limitations, benefits, and processes are presented. Additionally, key current approaches and efforts are analyzed for PON next generations, such as next-generation PON 2 (NGPON2) and high-speed PON (HSP).
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45

Rydygier, Przemysław, Władysław Dąbrowski, Tomasz Fiutowski, and Piotr Wiącek. "Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 399–404. http://dx.doi.org/10.2478/v10177-010-0053-9.

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Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode ArraysIn the paper we present the design and test results of an integrated circuit combining a sample&hold circuit and an analogue multiplexer. The circuit has been designed as a building block for a multi-channel Application Specific Integrated Circuit (ASIC) for recording signals from alive neuronal tissue using high-density micro-electrode arrays (MEAs). The design is optimised with respect to critical requirements for such applications, i.e. short sampling time, low power dissipation, good linearity and high dynamic range. Presented design comprises sample&hold circuits with class AB operational amplifier, novel shift register, which allows minimising cross-coupling of the clock signal and control logic. The circuit has been designed in 0.35μm CMOS process and has been successfully implemented in a prototype multi-channel ASIC.
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46

Hobday, Michael. "Semiconductor technology and the newly industrializing countries: The diffusion of ASICs (Application Specific Integrated Circuits)." World Development 19, no. 4 (April 1991): 375–97. http://dx.doi.org/10.1016/0305-750x(91)90184-j.

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47

Patel, Ambresh, and Ritesh Sadiwala. "Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 14, no. 02 (June 30, 2022): 202–5. http://dx.doi.org/10.18090/samriddhi.v14i02.13.

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With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dynamic CMOS architecture with stack transistor. With certain area and delay considerations, these strategies are utilized to diminish both types of power dissipation in the CMOS logic designs.
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48

Denny, Barbara, and Richard Bennett. "8.4.1 One Engineering Process – Integrated!" INCOSE International Symposium 10, no. 1 (July 2000): 557–64. http://dx.doi.org/10.1002/j.2334-5837.2000.tb00425.x.

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AbstractProcess definition is not new at Rockwell Collins. Processes have been documented and repeatedly updated throughout the Rockwell Collins history. Process variations have existed due to the number of disciplines, Business Units, degree of adherence, level of senior management support, customer influence, etc. During the past two years Rockwell Collins has documented an enterprise level standard engineering process framework. The resulting Engineering Technical Consistent Process (ETCP) addresses the disciplines of Systems Engineering, Software Engineering, Hardware Engineering and Application Specific Integrated Circuits (ASIC) Engineering and is one of a suite of enterprise level processes that encompass the full business lifecycle.
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49

Singh, Vimlesh, Priyanka Bansal, and P. K.Singhal. "Microstrip line Antenna Fabrication Material." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 340. http://dx.doi.org/10.14419/ijet.v7i2.8.10437.

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This paper presents an extensive survey of electromagnetic materials used for antenna fabrication, which find application in Civilian life as well as defense life. When a densely packed microwave integrated circuit is designed, it requires protection from higher power transient because of specific polarization and frequency response. To meet specification of such kind of microwave circuits it is desired to exploit properties of fabricating materials, which are not found in nature but can be prepared with specific proportion of chemical element combination. This study provides in-depth responses of materials toward electromagnetic wave's characteristics such as dielectric, flexible electronics, electrical and thermal properties, which have vast potential in communication engineering.
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50

Ranjan, Rajeev, Pablo Mendoza Ponce, Wolf Lukas Hellweg, Alexandros Kyrmanidis, Lait Abu Saleh, Dietmar Schroeder, and Wolfgang H. Krautschneider. "Integrated Circuit with Memristor Emulator Array and Neuron Circuits for Biologically Inspired Neuromorphic Pattern Recognition." Journal of Circuits, Systems and Computers 26, no. 11 (May 31, 2017): 1750183. http://dx.doi.org/10.1142/s0218126617501833.

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This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88[Formula: see text]ns to 4.99[Formula: see text][Formula: see text]s (200[Formula: see text]k[Formula: see text] to 204.8[Formula: see text]M[Formula: see text]) and other four having conductance ranging from 195[Formula: see text]ns to 190[Formula: see text][Formula: see text]s (5.2[Formula: see text]k[Formula: see text] to 5.12[Formula: see text]M[Formula: see text]). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350[Formula: see text]nm process.
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