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Journal articles on the topic 'Application specific instruction-set processor (ASIP)'

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Published: 4 June 2021

Last updated: 7 February 2022

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1

Imai, Masaharu, Yoshinori Takeuchi, Keishi Sakanushi, and Nagisa Ishiura. "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)." IPSJ Transactions on System LSI Design Methodology 3 (2010): 161–78. http://dx.doi.org/10.2197/ipsjtsldm.3.161.

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2

Sharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (May 27, 2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.

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Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

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3

Xin, Yao, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song, and Theodore W. Berger. "An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics." IEEE/ACM Transactions on Computational Biology and Bioinformatics 12, no. 5 (September 1, 2015): 1034–47. http://dx.doi.org/10.1109/tcbb.2015.2440248.

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4

Safaei Mehrabani, Yavar. "Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm." International Journal of Electronics Letters 7, no. 2 (May 25, 2018): 154–65. http://dx.doi.org/10.1080/21681724.2018.1477182.

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Zhang, Diandian, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd Ascheid, Rainer Leupers, and Bart Vanthournout. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (January 2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.

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Spinlocks are a common technique in Multi-Processor Systems-on-Chip (MPSoCs) to protect shared resources and prevent data corruption. Without a priori application knowledge, the control of spinlocks is often highly random which can degrade the system performance significantly. To improve this, a centralized control mechanism for spinlocks is proposed in this paper, which utilizes application-specific information during spinlock control. The complete control flow is presented, which starts from integrating high-level user-defined information down to a low-level realization of the control. An Application-Specific Instruction-set Processor (ASIP) called OSIP, which was originally designed for task scheduling and mapping, is extended to support this mechanism. The case studies demonstrate the high efficiency of the proposed approach and at the same time highlight the efficiency and flexibility advantages of using an ASIP as the system controller in MPSoCs.

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6

Iwaizumi, Hiroki, Shingo Yoshizawa, and Yoshikazu Miyanaga. "A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems." VLSI Design 2013 (March 18, 2013): 1–10. http://dx.doi.org/10.1155/2013/625019.

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A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs) and arithmetic instructions specialized in complex matrix operations.

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7

Qiao, Wan, and Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths." MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.

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In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.

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8

Wong, Tingh Wee, Bryan Ng, and Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem." Advanced Materials Research 403-408 (November 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.

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The emergence of Application-specific Instruction-set Processor (ASIP) has encouraged the proliferation of tool-chains used to streamline its design flow. One of the features much sought-after in these tool-chains is notably the automatic generation of Application-specific Functional Units (AFUs) which, in turn, involves the custom instruction generation as a crucial step. Whereupon an additional step is assumed to pipeline the patterns identified for fulfilling the I/O constraint, custom instructions that correspond to maximal valid subgraphs are mostly beneficial to the speedup gain. Therefore, we present in this paper a propositional satisfiability approach to efficiently identify the custom instructions which contain a large number of valid nodes. Our approach is different substantially from the previous works where it uses an edge classification method to reduce the search space for convexity checking. The experiment results show that our method can, in a matter of few seconds, identify a set of custom instructions that speed up the application to a few times faster.

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9

Fischer, Dirk, Jürgen Teich, Ralph Weper, and Michael Thies. "BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs." Journal of Circuits, Systems and Computers 12, no. 03 (June 2003): 353–75. http://dx.doi.org/10.1142/s0218126603000799.

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With the term Architecture/Compiler Co-exploration, we denote the problem of simultaneously optimizing an application-specific instruction set processor (ASIP) architecture as well as its generated compiler. In this paper, we characterize the design space of both compiler frontend (intermediate code optimization) and backend (changes of the machine model) and present the workflow of our framework BUILDABONG. The project consists of four phases: (a) architecture entry and composition, (b) automatic simulator generation, (c) compiler generation (in particular, retargeting), and (d) automatic architecture/compiler design space exploration. We demonstrate the feasibility of our approach by a detailed case study.

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10

Ahmed, O., S. Areibi, and G. Grewal. "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm." International Journal of Reconfigurable Computing 2013 (2013): 1–33. http://dx.doi.org/10.1155/2013/681894.

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Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP) implementation and two pure Register-Transfer Level (RTL) implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on an Xeon processor.

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11

Salmela, Perttu, Adrian Burian, Tuomas Järvinen, Aki Happonen, and Jarmo Henrik Takala. "Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations." ISRN Signal Processing 2011 (February 16, 2011): 1–8. http://dx.doi.org/10.5402/2011/615934.

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Baseband functions like channel estimation and symbol detection of sophisticated telecommunications systems require matrix operations, which apply highly nonlinear operations like division or square root. In this paper, a scalable low-complexity approximation method of the inverse square root is developed and applied in Cholesky and QR decompositions. Computation is derived by exploiting the binary representation of the fixedpoint numbers and by substituting the highly nonlinear inverse square root operation with a more implementation appropriate function. Low complexity is obtained since the proposed method does not use large multipliers or look-up tables (LUT). Due to the scalability, the approximation accuracy can be adjusted according to the targeted application. The method is applied also as an accelerating unit of an application-specific instruction-set processor (ASIP) and as a software routine of a conventional DSP. As a result, the method can accelerate any fixed-point system where cost-efficiency and low power consumption are of high importance, and coarse approximation of inverse square root operation is required.

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12

CATANIA, VINCENZO, MAURIZIO PALESI, and DAVIDE PATTI. "ANALYSIS AND TOOLS FOR THE DESIGN OF VLIW EMBEDDED SYSTEMS IN A MULTI-OBJECTIVE SCENARIO." Journal of Circuits, Systems and Computers 16, no. 05 (October 2007): 819–46. http://dx.doi.org/10.1142/s0218126607003915.

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The use of Application-Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case the ASIP specialization involves a complex interaction between hardware- and software-related issues. In this paper we propose tools and methodologies to cope efficiently with this complexity from a multi-objective perspective. We present EPIC-Explorer, an open platform for estimation and system-level exploration of an EPIC/VLIW architecture. We first analyze the possible design objectives, showing that it is necessary, given the fundamental role played by the VLIW compiler in instruction scheduling, to evaluate the appropriateness of ILP-oriented compilation on a case-by-case basis. Then, in the architecture exploration phase, we will use a multi-objective genetic approach to obtain a set of Pareto-optimal configurations. Finally, by clustering the configurations thus obtained, we extract those representing possible trade-offs between the objectives, which are used as a starting point for evaluation via more accurate estimation models at a subsequent stage in the design flow.

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13

Urban, Roberto, Heinrich T. Vierhaus, Mario Schölzel, Enrico Altmann, and Horst Seelig. "Non-Cyclic Design Space Exploration for ASIPs — Compiler-Centered Microprocessor Design (CoMet)." Journal of Circuits, Systems and Computers 25, no. 03 (December 28, 2015): 1640012. http://dx.doi.org/10.1142/s0218126616400120.

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The CoMet approach on designing application specific instruction set processors (ASIPs) is targeting a non-cyclic design space exploration (DSE). The design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate code can be simulated and profiled. Based on that profiling information, it can be further transformed to an optimized or refined intermediate code. The whole transformation process is implemented in a GUI-based design tool, whose main component is a configurable simulator for intermediate codes. It will be shown how the configurable intermediate code simulator is used and how the intermediate code transformation and the VHDL generation of the ASIP model will work in the CoMet tool.

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14

Meloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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15

Kammler, David, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, and Heinrich Meyr. "Automatic Generation of Memory Interfaces for ASIPs." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 1–23. http://dx.doi.org/10.4018/jertcs.2010070101.

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With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture-specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or memory controllers, slowing down the design-space exploration regarding the memory architecture. To overcome this drawback, the authors extend RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols. The feasibility of this approach is demonstrated in real-life case studies, including a design space exploration for a banked memory system.

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16

Yoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India." Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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17

Radhakrishnan, S., H. Guo, S. Parameswaran, and A. Ignjatovic. "HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors." IET Computers & Digital Techniques 3, no. 1 (2009): 94. http://dx.doi.org/10.1049/iet-cdt:20080005.

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18

Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

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19

Antikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector." EURASIP Journal on Embedded Systems 2007 (2007): 1–14. http://dx.doi.org/10.1155/2007/54173.

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Antikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector." EURASIP Journal on Embedded Systems 2007, no. 1 (2007): 054173. http://dx.doi.org/10.1186/1687-3963-2007-054173.

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21

Sisto, A., L. Pilato, R. Serventi, S. Saponara, and L. Fanucci. "Application specific instruction set processor for sensor conditioning in automotive applications." Microprocessors and Microsystems 47 (November 2016): 375–84. http://dx.doi.org/10.1016/j.micpro.2016.10.001.

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22

Saponara, Sergio, Luca Fanucci, Stefano Marsi, Giovanni Ramponi, David Kammler, and Ernst Martin Witte. "Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 7 (July 2007): 596–600. http://dx.doi.org/10.1109/tcsii.2007.896778.

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23

Peters, H., R. Sethuraman, A. Beric, P. Meuwissen, S. Balakrishnan, C. A. A. Pinto, W. Kruijtzer, et al. "Application specific instruction-set processor template for motion estimation in video applications." IEEE Transactions on Circuits and Systems for Video Technology 15, no. 4 (April 2005): 508–27. http://dx.doi.org/10.1109/tcsvt.2005.844462.

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24

Hoffmann, A., T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr. "A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 11 (2001): 1338–54. http://dx.doi.org/10.1109/43.959863.

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25

Choi, Seung-Hyun, Tae-Moon Roh, Yong Ho Song, and Seong-Won Lee. "Design of an application specific instruction set processor for a universal bitstream codec." IEICE Electronics Express 11, no. 24 (2014): 20141047. http://dx.doi.org/10.1587/elex.11.20141047.

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26

Zhaohui Liu, K. Dickson, and J. V. McCanny. "Application-specific instruction set processor for SoC implementation of modern signal processing algorithms." IEEE Transactions on Circuits and Systems I: Regular Papers 52, no. 4 (April 2005): 755–65. http://dx.doi.org/10.1109/tcsi.2005.844109.

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27

Mbaye, Mame Maria, Normand Bélanger, Yvon Savaria, and Samuel Pierre. "A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration." Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 47, no. 3 (March 27, 2007): 297–315. http://dx.doi.org/10.1007/s11265-007-0050-0.

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28

Bytyn, Andreas, Rainer Leupers, and Gerd Ascheid. "ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs." IEEE Open Journal of Circuits and Systems 2 (2021): 3–15. http://dx.doi.org/10.1109/ojcas.2020.3037758.

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29

Mooney, James, Abdulhussain E. Mahdi, and Mark Halton. "Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 1 (January 2013): 243–54. http://dx.doi.org/10.1109/tcsi.2012.2215783.

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30

Heo, Ingoo, Minsu Kim, Yongje Lee, Changho Choi, Jinyong Lee, Brent Byunghoon Kang, and Yunheung Paek. "Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines." ACM Transactions on Design Automation of Electronic Systems 20, no. 4 (September 28, 2015): 1–32. http://dx.doi.org/10.1145/2746238.

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31

ZHANG, Yuli, Jun HAN, Xinqian WENG, Zhongzhu HE, and Xiaoyang ZENG. "Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm." IEICE Transactions on Electronics E95.C, no. 8 (2012): 1415–26. http://dx.doi.org/10.1587/transele.e95.c.1415.

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32

Tamagnone, M., M. Martina, and G. Masera. "An application specific instruction set processor based implementation for signal detection in multiple antenna systems." Microprocessors and Microsystems 36, no. 3 (May 2012): 245–56. http://dx.doi.org/10.1016/j.micpro.2011.11.003.

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XIAO, Shanlin, Tsuyoshi ISSHIKI, Dongju LI, and Hiroaki KUNIEDA. "Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A, no. 7 (2017): 1384–95. http://dx.doi.org/10.1587/transfun.e100.a.1384.

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Guan, Xuan, Yunsi Fei, and Hai Lin. "Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 3 (March 2012): 551–63. http://dx.doi.org/10.1109/tvlsi.2011.2105512.

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Lin, Hai, and Yunsi Fei. "Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design." ACM Transactions on Design Automation of Electronic Systems 17, no. 4 (October 2012): 1–20. http://dx.doi.org/10.1145/2348839.2348843.

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Abdel All, Mahmoud, Hanan M. Hassan, Medhat Hamdy, Omar A. Nasr, Karim Mohamed, and Ahmed F. Shalash. "Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor." IET Circuits, Devices & Systems 9, no. 3 (May 2015): 191–203. http://dx.doi.org/10.1049/iet-cds.2014.0046.

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37

K.Jain, M., and Deepak Gour. "Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor." International Journal of Computer Applications 43, no. 5 (April 30, 2012): 14–19. http://dx.doi.org/10.5120/6098-8290.

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38

Ziebinski, Adam, and Stanwlaw Swierc. "Soft Core Processor Generated Based on the Machine Code of the Application." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650029. http://dx.doi.org/10.1142/s0218126616500298.

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Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4).

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Salmela, Perttu, Harri Sorokin, and Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation." VLSI Design 2008 (December 22, 2008): 1–17. http://dx.doi.org/10.1155/2008/319095.

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In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.

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40

Zhang, Diandian, Han Zhang, Jeronimo Castrillon, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, and Rainer Leupers. "Optimized Communication Architecture of MPSoCs with a Hardware Scheduler." International Journal of Embedded and Real-Time Communication Systems 2, no. 3 (July 2011): 1–20. http://dx.doi.org/10.4018/jertcs.2011070101.

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Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, the authors highlight the vital importance of the communication architecture for OSIP-based systems and optimize the communication architecture. Furthermore, the effects of OSIP and the communication architecture are investigated jointly from the system point of view, based on a broad case study for a real life application (H.264) and a synthetic benchmark application.

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Venkanna, Mood, and Rameshwar Rao. "Static Worst-Case Execution Time Optimization using DPSO for ASIP Architecture." Ingeniería Solidaria 14, no. 25 (May 1, 2018): 1–11. http://dx.doi.org/10.16925/.v14i0.2230.

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Introduction: The application of specific instructions significantly improves energy, performance, and code size of configurable processors. The design of these instructions is performed by the conversion of patterns related to application-specific operations into effective complex instructions. This research was presented at the icitkm Conference, University of Delhi, India in 2017.Methods: Static analysis was a prominent research method during late the 1980’s. However, end-to-end measurements consist of a standard approach in industrial settings. Both static analysis tools perform at a high-level in order to determine the program structure, which works on source code, or is executable in a disassembled binary. It is possible to work at a low-level if the real hardware timing information for the executable task has the desired features.Results: We experimented, tested and evaluated using a H.264 encoder application that uses nine cis, covering most of the computation intensive kernels. Multimedia applications are frequently subject to hard real time constraints in the field of computer vision. The H.264 encoder consists of complicated control flow with more number of decisions and nested loops. The parameters evaluated were different numbers of A partitions (300 slices on a Xilinx Virtex 7each), reconfiguration bandwidths, as well as relations of cpu frequency and fabric frequency fCPU/ffabric. ffabric remains constant at 100MHz, and we selected a multiplicity of its values for fCPU that resemble realistic units. Note that while we anticipate the wcet in seconds (wcetcycles/ f CPU) to be lower (better) with higher fCPU, the wcet cycles increase (at a constant ffabric) because hardware cis perform less computations on the reconfigurable fabric within one cpu cycle.Conclusions: The method is similar to tree hybridization and path-based methods which are less precise, and to the global ipet method, which is more precise. Optimization is evaluated with the Discrete Particle Swarm Optimization (dpso) algorithm for wcet. For several real-world applications involving embedded processors, the proposed technique develops improved instruction sets in comparison to native instruction sets.Originality: For wcet estimation, flow analysis, low-level analysis and calculation phases of the program need to be considered. Flow analysis phase or the high-level of analysis helps to extract the program’s dynamic behavior that gives information on functions being called, number of loop iteration, dependencies among if-statements, etc. This is due to the fact that the analysis is unaware of the execution path corresponding to the longest execution time.Limitations: This path is executed within a kernel iteration that relies upon the nature of mb, either i-mb or p-mb, determined by the motion estimation kernel, that is, its’ input depends on the i-mb and p-mb paths ,which also contain separate cis leading to the instability of the worst-case path, that is, adding more partitions to the current worst-case path can result in the other path becoming the worst case. The pipeline stalls for the reconfiguration delay and continues when entering the kernel once the reconfiguration process finishes.

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Bispo, João, Nuno Paulino, João M. P. Cardoso, and João Canas Ferreira. "Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units." International Journal of Reconfigurable Computing 2013 (2013): 1–20. http://dx.doi.org/10.1155/2013/340316.

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The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. The proposed approach considers offline partitioning and mapping stages without ignoring their future runtime applicability. We present a toolchain that automatically extracts specific trace-based loops, called Megablocks, from MicroBlaze instruction traces and generates an RPU for executing those loops. Our hardware infrastructure is able to move loop execution from the microprocessor to the RPU transparently, at runtime, and without changing the executable binaries. The toolchain and the system are fully operational. Three FPGA implementations of the system, differing in the hardware interfaces used, were tested and evaluated with a set of 15 application kernels. Speedups ranging from 1.26 to 3.69 were achieved for the best alternative using a MicroBlaze processor with local memory.

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Sugiura, Tomoki, Masaharu Imai, Jaehoon Yu, and Yoshinori Takeuchi. "A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems." Journal of Information Processing 25 (2017): 210–19. http://dx.doi.org/10.2197/ipsjjip.25.210.

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Vishnoi, U., and T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies." Advances in Radio Science 10 (September 18, 2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.

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Abstract. The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz−1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

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Vassiliadis, N., A. Chormoviti, N. Kavvadias, and S. Nikolaidis. "THE EFFECT OF DATA-REUSE TRANSFORMATIONS ON MULTIMEDIA APPLICATIONS FOR APPLICATION SPECIFIC PROCESSORS." International Journal of Computing, August 1, 2014, 102–9. http://dx.doi.org/10.47839/ijc.4.3.369.

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Multimedia applications are characterized by a high number of data transfers and storage operations. Appropriate transformations can be applied at the algorithmic level to improve crucial implementation characteristics. In this paper, the effect of data-reuse transformations on power consumption and performance of multimedia applications, realized on an Application Specific Instruction set Processor (ASIP), is examined. An ASIP for multimedia applications designed based on a complete methodology is used to evaluate this effect. Results prove the efficiency of the ASIP solution and indicate benefits from the use of the data-reuse transformations in terms of energy consumption and performance. Also, preliminary results from the exploitation of instruction buffering technique to reduce the energy consumption of the ASIP are presented.

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Janwa, Naresh Kumar, and Dr Manoj Kumar Jain. "Identification of Research Gaps in an Efficient Designing of Application Specific Instruction Set Processor (ASIP) for Neural Prosthetics." SSRN Electronic Journal, 2019. http://dx.doi.org/10.2139/ssrn.3349573.

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Gerlach, Lukas, Guillermo Payá-Vayá, and Holger Blume. "A Survey on Application Specific Processor Architectures for Digital Hearing Aids." Journal of Signal Processing Systems, March 20, 2021. http://dx.doi.org/10.1007/s11265-021-01648-0.

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AbstractOn the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors. Special attention is given to the increasingly common application-specific instruction-set processors (ASIPs). The main focus of this paper lies on hardware-related aspects such as the processor architecture, the interfaces, the application specific integrated circuit (ASIC) technology, and the operating conditions. The different hearing aid implementations are compared in terms of power consumption, silicon area, and computing performance for the algorithms used. Challenges for the design of future hearing aid processors are discussed based on current trends and developments.

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"Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPS) [Book Review]." IEEE Circuits and Devices Magazine 22, no. 2 (March 2006): 31. http://dx.doi.org/10.1109/mcd.2006.1615247.

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Rizk, Mostafa, Amer Baghdadi, Michel Jézéquel, Youssef Atat, and Yasser Mohanna. "NISC-based MIMO MMSE Detector." Journal of Circuits, Systems and Computers, September 2, 2020, 2150069. http://dx.doi.org/10.1142/s0218126621500699.

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Several application-specific processor design approaches have been proposed and investigated to cope with the emerging flexibility requirements jointly associated with the maximum performance efficiency and minimum implementation area and power consumption. Dynamic scheduling of a set of instructions generally leads to an overhead related to instruction decoding. To mitigate this overhead, other approaches have been proposed using static scheduling of datapath control signals. In this context, No-Instruction-Set-Computer (NISC) concept have been introduced considering that a dedicated processor to a specific application does not need an instruction set especially when it is programmed by its designers and not by its users. In this paper, the hardware architecture design of flexible NISC-based architecture design dedicated for minimum mean-squared error (MMSE) linear detection is presented. The devised design, which is used in iterative turbo-receiver, fulfills the performance requirements of emergent wireless communication standards with throughput reaching that of LTE-Advanced. FPGA hardware implementation of the detector architecture achieves a maximum throughput of 115.8 Mega symbols per second for [Formula: see text] and 6.4 Mega symbols per second for [Formula: see text] MIMO systems for an operating clock frequency of 202.67[Formula: see text]MHz.

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"Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (November 10, 2019): 4557–61. http://dx.doi.org/10.35940/ijitee.a4899.119119.

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Many processors have evolved in the past century; Out of which, Reduced Instruction set Computing (RISC) processors are well known for their ease of use. The next in line was the Microprocessor without Interlocked pipelining stages (MIPS) RISC based architecture. Less number of instructions, good amount of registers makes these processors a boon to use. Often times, MIPS processors loose the battle against their contenders due to lack of speed. Hence, there is a sheer necessity in designing a more robust system that has all the advantages of MIPS. Over time, there have been designs that could solve the power drawbacks and the area optimizations. However, performance criterion is mostly neglected. This paper emphasizes on the performance metric of pipelined 32-bit MIPS microprocessor. This processor supports RISC architecture and has been designed under Harvard architecture. Pipelining technique is used to solve the problem of low performance and achieve smaller execution times. The processor has four pipes. Pipes are the structures which store data. Pipes can be viewed as register banks. These pipes are generally used to store the intermediate data. The design contains various modules like ALU, Instruction fetch register, Execution unit, Memory, Program counter (PC). Verilog HDL has been used to implement the design. The software used is Xilinx ISE for design and ISIM simulator has been used for simulation purposes. The applications of this MIPS microprocessor are abundant. MIPS microprocessor can be used to carry out the fundamental tasks and an application specific core/IP/processor can be designed and combined with MIPS. This facilitates in meeting the goals of high performance, lower time-to-market and cost- effectiveness. Some application specific uses can be for music systems, PDA, Image processing etc.

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