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Journal articles on the topic 'ANALYSIS OF CMOS'

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Published: 16 January 2024

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1

LIAO, HAIFANG, WAYNE WEI-MING DAI, and RUI WANG. "A NEW CMOS DRIVER MODEL FOR TRANSIENT ANALYSIS AND POWER DISSIPATION ANALYSIS." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 269–85. http://dx.doi.org/10.1142/s0129156496000116.

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While most transient analysis techniques of interconnect networks ignore the nonlinearity of the driving gates, most CMOS driver models do not take into account the distributed loads. In this paper, we propose a new CMOS driver model which can handle distributed-lumped loads for transient analysis and power dissipation analysis. The output current of the CMOS driver is represented by a linear-quadratic-exponential piecewise model, taking into account the slope of the input signal, nonlinear effects of the driver and interconnect effects of the load. The CMOS transient leakage (short-circuit) current, thus short-circuit power dissipation, can be accurately evaluated. The model provides accuracy comparable to that of SPICE3e2 with one or two orders of magnitude less computing time.

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2

Cheyette, Oren. "OAS Analysis for CMOs." Journal of Portfolio Management 20, no. 4 (July 31, 1994): 53–66. http://dx.doi.org/10.3905/jpm.1994.409485.

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3

Jomaah, Jalal, Majida Fadlallah, and Gerard Ghibaudo. "Low Frequency Noise Analysis in Advanced CMOS Devices." Advanced Materials Research 324 (August 2011): 441–44. http://dx.doi.org/10.4028/www.scientific.net/amr.324.441.

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A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are illustrated through experimental data obtained on advanced CMOS generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown.

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4

Sheikh, Shireen T. "Comparative Analysis of CMOS OTA." IOSR journal of VLSI and Signal Processing 1, no. 3 (2012): 01–05. http://dx.doi.org/10.9790/4200-0130105.

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5

Schmitt-Landsiedel, D. "Yield Analysis of CMOS Ics." Solid State Phenomena 57-58 (July 1997): 327–36. http://dx.doi.org/10.4028/www.scientific.net/ssp.57-58.327.

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6

Dimitrijev, S., and N. Stojadinović. "Analysis of CMOS transistor instabilities." Solid-State Electronics 30, no. 10 (October 1987): 991–1003. http://dx.doi.org/10.1016/0038-1101(87)90090-6.

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7

Gajare, Milind, and Shedge D.K. "CMOS Trans Conductance based Instrumentation Amplifier for Various Biomedical Signal Analysis." NeuroQuantology 20, no. 5 (April 30, 2022): 53–60. http://dx.doi.org/10.14704/nq.2022.20.5.nq22148.

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Feed forward design techniques for the Trans-conductance operational amplifier removes the barriers of operating frequencies. It is now possible to design amplifiers with large the Trans-conductance that operates at Giga hertz frequency range. There are several Trans-conductance amplifiers used to design a medical and Industrial application that helps in processing various bio medical signals such as Electrocardiographs, Electroencephalographs, Electromyograms and several others. The proposed paper shows the implementation of an instrumentation amplifier using CMOS based the Trans-conductance operational amplifiers also the processing of biomedical ECG, EEG and EMG signals. The CMOS process technology helps to integrate complex circuits on minimal surface area. The Trans-conductance instrumentation operational amplifiers has features includes noise reduction, low DC offset, High output impedance and Common Mode rejection Ratio values. The circuit implementation and simulations has been done on Electronic Design and Automation tool with 0.13μm CMOS process technology.

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8

Yao, Hong Tao, Zi Qiang Wang, Yuan Bao Gu, and Zhen Gang Jiang. "Analysis of Black Level Calibration Algorithm for CIS." Applied Mechanics and Materials 599-601 (August 2014): 1397–402. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.1397.

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This paper presents the structure and the operational principle of CMOS image sensors. And then the reason is illuminated for producing dark current and black level of CMOS image sensors. It is necessary to calibrate dark current and black level to improve quality of CMOS image sensors. The dark current is corrected by optimizing pixel structure, perfecting technology, improving 6layout, and correction double sample. But these ways do not calibrate black level. So, it is important to calibrate black level using black level calibration algorithm in the stage of image processing.

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9

Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

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10

Cho, Won-ho, and Ki-sang Hong. "Affine Motion Based CMOS Distortion Analysis and CMOS Digital Image Stabilization." IEEE Transactions on Consumer Electronics 53, no. 3 (August 2007): 833–41. http://dx.doi.org/10.1109/tce.2007.4341553.

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11

Xiong, Qi, Shao Hua Zhou, and Jiang Ping Zeng. "The Analysis of Device Model in CMOS Integrated Temperature Sensor." Advanced Materials Research 986-987 (July 2014): 1600–1605. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1600.

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According to the requirement of the CMOS integrated temperature sensor on the device, we analyzed the sub-threshold model of MOS device and the bipolar device under MOS technology. We found the latter is more suitable for a components of CMOS integrated temperature sensor devices. Therefore, we analyzed the influence of the substrate PNP tube’s piezoelectric effect on temperature sensor and compared different types of resistance that lays a theoretical basis for the design of CMOS integrated temperature sensor.

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12

Prof. Nikhil Surkar. "Design and Analysis of Optimized Fin-FETs." International Journal of New Practices in Management and Engineering 4, no. 04 (December 31, 2015): 01–06. http://dx.doi.org/10.17762/ijnpme.v4i04.39.

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Semiconductor industry greatly depends on CMOS technology and now needs competent technology with handful benefits. This paper examines and analyzes the modern FINFET technology. This analysis is performed through 9 stages Ring Oscillator equipped with FINFET. Performance is analyzed by comparing the proposed structure with CMOS based 9 stage Ring Oscillator at the nano-scale level of abstraction.

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13

Mun, Hye Jin, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang. "Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary." Journal of Nanoscience and Nanotechnology 20, no. 11 (November 1, 2020): 6616–21. http://dx.doi.org/10.1166/jnn.2020.18769.

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In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

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14

Le, H. P., A. Zayegh, and J. Singh. "Performance analysis of optimised CMOS comparator." Electronics Letters 39, no. 11 (2003): 833. http://dx.doi.org/10.1049/el:20030546.

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15

Zhao, Zhixing, Sebastian Magierowski, and Leonid Belostotski. "Linearity Analysis of CMOS Parametric Upconverters." IEEE Access 8 (2020): 190906–21. http://dx.doi.org/10.1109/access.2020.3032397.

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16

Verhelst, M., and B. Murmann. "Area scaling analysis of CMOS ADCs." Electronics Letters 48, no. 6 (2012): 314. http://dx.doi.org/10.1049/el.2012.0253.

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17

Kress, Rainer, Elmar Melcher, Reiner Hartenstein, and Michel Dana. "CMOS interconnect modelling for timing analysis." Microprocessing and Microprogramming 37, no. 1-5 (January 1993): 7–10. http://dx.doi.org/10.1016/0165-6074(93)90004-5.

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18

bin Rosly, Hasrul Nisham, Mamun bin Ibne Reaz, Noorfazila Kamal, and Fazida Hanim Hashim. "Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application." Applied Mechanics and Materials 833 (April 2016): 111–18. http://dx.doi.org/10.4028/www.scientific.net/amm.833.111.

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Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.

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19

Sharma, Prakash. "Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (January 31, 2022): 732–37. http://dx.doi.org/10.22214/ijraset.2022.39908.

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Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

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20

Lee, Sangho, and Edwin W. Greeneich. "CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization." VLSI Design 15, no. 3 (January 1, 2002): 619–28. http://dx.doi.org/10.1080/1065514021000012237.

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Efficient, generalized delay and power equations are proposed for large scale CMOS circuit analysis and optimization achieved by transistor and interconnect wire minimization. The proposed model equations are used to analyze the entire power-delay trade-off with less complexity and faster computation time. New equations can be adopted to perform the optimization of transistor and interconnect wire size concurrently. A single stage CMOS circuit and a clock generation block fabricated in 0.48 um CMOS process are given as experimental examples.

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21

Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.

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22

Li, Ming Jing, Yu Bing Dong, and Guang Liang Cheng. "Multiple CMOS Intersection Measuring System Modeling and Analysis." Advanced Materials Research 614-615 (December 2012): 1299–302. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1299.

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Multiple high speed CMOS cameras composing intersection system to splice large effect field of view(EFV). The key problem of system is how to locate multiple CMOS cameras in suitable position. Effect field of view was determined according to size, quantity and dispersion area of objects, so to determine camera position located on below, both sides and ahead to moving targets. This paper analyzes effect splicing field of view, operating range etc through establishing mathematical model and MATLAB simulation. Location method of system has advantage of flexibility splicing, convenient adjustment, high reliability and high performance-price ratio.

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23

Zhang, Yichen. "Comparative analysis of logic gates based on CMOS, FINFET, and CNFET: Characteristics and simulation insights." Theoretical and Natural Science 26, no. 1 (December 20, 2023): 44–53. http://dx.doi.org/10.54254/2753-8818/26/20241011.

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In the evolution of integrated circuit technology, chip size and performance enhancement stand as paramount and challenging domains of progress. Yet, a dearth of foundational simulations and comparisons for introductory purposes exists. Consequently, this study delves into an introduction of distinct advanced integrated circuit (IC) technologies: CMOS, FinFET, and CNTFET, dissecting their merits and limitations. Subsequently, a preliminary simulation is executed to authenticate specific characteristics inherent to these IC technologies. Discoveries indicate that as IC transistors scale down, there are marked improvements in transistor performance, encompassing aspects such as switching speed, noise immunity, power efficiency, and heat dissipation. Further, a simulation grounded on a NAND gate substantiates certain traits in CMOS and FinFET, specifically switching speed, propagation delay, and noise margin. The results illustrate a superior performance of FinFET over CMOS. Additionally, as CMOS technology scales, its efficacy enhances. Nonetheless, the present research and simulations hold potential uncertainties and constraints, paving avenues for more refined investigations in the future.

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24

Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.

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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.

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25

Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (November 17, 2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of CMOS device, and the combined circuit design and sequential logic circuit design principle of dynamic and static CMOS are explained in detail. Then, the application principle of CMOS technology in GPU is analyzed, and its specific application in GPU acceleration algorithm is analyzed. Finally, the application of CMOS technology in integrated circuits and its application and acceleration effect are summarized.

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26

Panwar, Shikha, Mayuresh Piske, and Aatreya Vivek Madgula. "Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits." VLSI Design 2014 (July 15, 2014): 1–5. http://dx.doi.org/10.1155/2014/380362.

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This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

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27

KAKKAR, VIPAN. "PERFORMANCE ANALYSIS OF CMOS FOR HIGH SPEED MIXED SIGNAL CIRCUITS." Journal of Circuits, Systems and Computers 20, no. 06 (October 2011): 1067–74. http://dx.doi.org/10.1142/s0218126611007761.

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The objective of this paper is to discuss the opportunities of an advanced RFCMOS for millimeter-wave applications based on an assessment of figures of merits including relevant device information. This paper introduces the RF specifications for 45 nm CMOS node and present the evolution of RF-FOMs with gate downscaling over the previous generations. Especially, since 45 nm CMOS is the technology to be available in production, a particular focus on its RF performance for power and bandwidth is given.

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28

R.Rajprabu, R. Rajprabu. "Performance Analysis of CMOS and FinFET Logic." IOSR journal of VLSI and Signal Processing 2, no. 1 (2013): 01–06. http://dx.doi.org/10.9790/4200-0210106.

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29

ZHANG Jing-shui, 张镜水, 孔令琴 KONG Lingqin, 董立泉 DONG Li-quan, and 赵跃进 ZHAO Yue-jin. "Terahertz CMOS transistor model and experimental analysis." Optics and Precision Engineering 25, no. 12 (2017): 3128–36. http://dx.doi.org/10.3788/ope.20172512.3128.

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30

Wang, Fei, and Albert Theuwissen. "Linearity analysis of a CMOS image sensor." Electronic Imaging 2017, no. 11 (January 29, 2017): 84–90. http://dx.doi.org/10.2352/issn.2470-1173.2017.11.imse-191.

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31

Sanghoon Kang, Byounggi Choi, and Bumman Kim. "Linearity analysis of CMOS for RF application." IEEE Transactions on Microwave Theory and Techniques 51, no. 3 (March 2003): 972–77. http://dx.doi.org/10.1109/tmtt.2003.808709.

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32

Pinto, M. R., and R. W. Dutton. "Accurate trigger condition analysis for CMOS latchup." IEEE Electron Device Letters 6, no. 2 (February 1985): 100–102. http://dx.doi.org/10.1109/edl.1985.26057.

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33

Rangavajjhala, V. S., B. L. Bhuva, and S. E. Kerns. "Statistical degradation analysis of digital CMOS IC's." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, no. 6 (June 1993): 837–44. http://dx.doi.org/10.1109/43.229759.

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34

Chao, H. J., and C. A. Johnston. "Behavior analysis of CMOS D flip-flops." IEEE Journal of Solid-State Circuits 24, no. 5 (October 1989): 1454–58. http://dx.doi.org/10.1109/jssc.1989.572637.

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35

Dogan, Hakan, Robert G. Meyer, and Ali M. Niknejad. "Analysis and Design of RF CMOS Attenuators." IEEE Journal of Solid-State Circuits 43, no. 10 (October 2008): 2269–83. http://dx.doi.org/10.1109/jssc.2008.2004325.

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36

Finvers, I. G., and I. M. Filanovsky. "Analysis of a source-coupled CMOS multivibrator." IEEE Transactions on Circuits and Systems 35, no. 9 (1988): 1182–85. http://dx.doi.org/10.1109/31.7584.

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37

Samanta, Jagannath, and Bishnu Prasad De. "Delay analysis of UDSM CMOS VLSI circuits." Procedia Engineering 30 (2012): 135–43. http://dx.doi.org/10.1016/j.proeng.2012.01.844.

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38

Pittet, P., J. M. Galvan, G. N. Lu, L. J. Blum, and B. D. Leca-Bouvier. "CMOS LIF detection system for capillary analysis." Sensors and Actuators B: Chemical 97, no. 2-3 (February 2004): 355–61. http://dx.doi.org/10.1016/j.snb.2003.09.021.

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39

Sharroush, Sherif M. "Analysis of the subthreshold CMOS logic inverter." Ain Shams Engineering Journal 9, no. 4 (December 2018): 1001–17. http://dx.doi.org/10.1016/j.asej.2016.05.005.

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40

Kim, Kyung Ki. "Analysis of Electromigration in Nanoscale CMOS Circuits." Journal of the Korea Industrial Information Systems Research 18, no. 1 (February 28, 2013): 19–24. http://dx.doi.org/10.9723/jksiis.2013.18.1.019.

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41

Shan, Yu, Zhang Dingkang, and Huang Chang. "0.8μm LDD CMOS reliability experiments and analysis." Journal of Electronics (China) 12, no. 1 (January 1995): 84–89. http://dx.doi.org/10.1007/bf02684572.

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42

G, Minikumari. "Performance Analysis of Deep Sub Micron Two Quadrant Analog Divider Circuits." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 663–68. http://dx.doi.org/10.22214/ijraset.2023.51561.

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Abstract: Current mode Analog Dividers are widely used in various circuits such as fuzzy logic controllers, neural networks, adaptive filters and variable gain amplifiers. When these current analog divider circuits implemented in DSM technology, many of the second order effects starts deteriorating its performance. Most of the available literatures on analog dividers are reporting performance of these circuits implemented using long channel MOSFETs. Hence it is a peak time to compare the performance variation between various proposed analog circuits implemented in lower technological nodes. This is for identifying most reliable circuit which safely works in this node. .In this work a comparative performance analysis of two quadrant CMOS analog divider against two quadrant CMOS approximation divider using 45nm technological node has been carried out. The obtained result indicates that Approximation Divider is reliabie than two quadrant CMOS analog divider. The entire work is carried out using Tanner software.

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43

., Gudala Konica, and Sreenivasulu Mamilla . "Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling." Volume 4,Issue 5,2018 4, no. 5 (January 5, 2019): 575–79. http://dx.doi.org/10.30799/jnst.187.18040530.

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As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

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44

Jeong, Sang-Hun, Nam-Ho Lee, Min-Woong Lee, and Seong-Ik Cho. "Analysis of Radiation Effects in CMOS 0.18um Process Unit Devices." Transactions of The Korean Institute of Electrical Engineers 66, no. 3 (March 1, 2017): 540–44. http://dx.doi.org/10.5370/kiee.2017.66.3.540.

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45

Esonu, M. O., D. Al-Khalili, and C. Rozon. "Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits." VLSI Design 1, no. 4 (January 1, 1994): 261–76. http://dx.doi.org/10.1155/1994/70696.

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The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or Noise Margin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalent ECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used.

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46

Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (March 21, 2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logicÂ techniques Â basedÂ onÂ eitherÂ PMOSÂ orÂ NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

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Mačaitis, Vytautas, and Romualdas Navickas. "Analysis of Main LC-VCO Parameters for Multistandard Tranceivers." Mokslas - Lietuvos ateitis 9, no. 3 (July 4, 2017): 324–28. http://dx.doi.org/10.3846/mla.2017.1043.

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This paper reviews CMOS LC Voltage Controlled Oscillators (VCO) for wireless multi-standard transceivers and wireless communications. The main parameters, such as IC technology, phase noise, carrier frequency, supply voltage, tuning range, power dissipation, figure of merit (FOMT and FOMTT) were reviewed in this paper. These parameters were taken of 20 articles published in 2012–2016 years. Of the reviewed articles it can be said that most VCOs was designed in 180 nm (55%) and 65 nm (25%) CMOS IC technology. FOMTT quality function has been proposed for extended VCO quality assessment. FOMTT quality function additionally evaluates VCO IC technology, and the power supply.

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Wagaj, S. C., and S. C. Patil. "Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor." International Journal of Engineering and Advanced Technology 10, no. 6 (August 30, 2021): 1–10. http://dx.doi.org/10.35940/ijeat.e2576.0810621.

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In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

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Huang, Peihao. "Design and optimization of CMOS layout structure for improved semiconductor device performance." Journal of Physics: Conference Series 2649, no. 1 (November 1, 2023): 012040. http://dx.doi.org/10.1088/1742-6596/2649/1/012040.

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Abstract CMOS layout structure plays a very important role in the field of semiconductor. Since the invention of CMOS technology in the 1970s, engineers have developed many other CMOS layout technologies based on it. This paper will also focus on the CMOS transistor layout structure, focusing on the analysis of three more important structures, demonstrating their impact on the performance of semiconductor devices. Before that, this paper will first introduce the basic theory of CMOS, such as the drift and diffusion of charge carriers in PN junctions, and the working principle of PMOS and NMOS, so as to facilitate us to further describe the optimization and improvement of CMOS structure. Then, the performance and characteristics of each structure are introduced in detail, and finally the comparison is made to highlight their advantages in technology and performance compared with traditional structures. In the future, CMOS structure layout will also become a hot spot, constantly creating more reasonable and advanced structures to improve semiconductor performance.

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Lazzaz, Abdelaziz, Khaled Bousbahi, and Mustapha Ghamnia. "Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM,7 NM and 5 NM node technologies." Facta universitatis - series: Electronics and Energetics 36, no. 1 (2023): 1–16. http://dx.doi.org/10.2298/fuee2301001l.

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Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore?s empirical law. The planar metal-oxide semiconductor field effect transistor (MOSFET) structure has reached its limit in terms of technological node reduction. To ensure the continuation of CMOS scaling and to overcome the Short Channel Effect (SCE) issues, a new MOS structure known as Fin field-effect transistor (FinFET) has been introduced and has led to significant performance enhancements. This paper presents a comparative study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology nodes. Electrical parameters like the maximum switching current ION, the leakage current IOFF, and the performance ratio ION/IOFF for N and P FinFET with different nodes are presented in this simulation. The aim and the novelty of this paper is to extract the operating frequency for CMOS circuits using Quantum and Stress effects implemented in the Spice parameters on the latest Microwind software. The simulation results show a fitting with experimental data for FinFET N and P 10 nm strctures using quantum correction. Finally, we have demonstrate that FinFET 5 nm can reach a minimum time delay of td=1.4 ps for CMOS NOT gate and td=1 ps for CMOS NOR gate to improve Integrated Circuits IC.

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