Dissertations / Theses: 'Analog VLSI'

1

Blum, Richard Alan. "An analog VLSI centroid imager." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14826.

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2

Morris, Tonia Gay. "Analog VLSI visual attention systems." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15010.

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Benson, Ronald Gary Hopfield John J. "Analog VLSI supervised learning system /." Diss., Pasadena, Calif. : California Institute of Technology, 1994. http://resolver.caltech.edu/CaltechETD:etd-06152004-095124.

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4

Wee, Keng Hoong. "An analog VLSI vocal tract." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43053.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 165-168).
Increasingly, circuit models of biology are being used to improve performance in engineering systems. For example, silicon-cochlea-like models have led to improved speech recognition in noise and low-power cochlear-implant processors for the deaf. A promising approach to improve the naturalness of synthetic speech is to exploit bioinspired models of speech production with low bit-rate control parameters. In this work, we present the first experimental integrated-circuit vocal tract by mapping fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The 275 jW analog vocal tract chip can be used with auditory processors in a feedback speech locked loop to implement speech recognition that is potentially robust in noise. Our use of a physiological model of the human vocal tract enables the analog vocal tract chip to synthesize speech signals of interest, using articulatory parameters that are intrinsically compact and linearly interpolatable. Previous attempts that take advantage of the powerful analysis-by-synthesis method employed computationally expensive approaches to articulatory synthesis using digital computation. Our strategy uses an analog vocal tract to drastically reduce power consumption, enables real-time performance and could be useful in portable speech processing systems of moderate complexity, e.g., in cell phones, digital assistants and bionic speech-prosthesis systems.
by Keng Hoong Wee.
Ph.D.

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5

Shiraishi, Hisako. "Design of an Analog VLSI Cochlea." University of Sydney. Electrical and Information Engineering, 2003. http://hdl.handle.net/2123/556.

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The cochlea is an organ which extracts frequency information from the input sound wave. It also produces nerve signals, which are further analysed by the brain and ultimately lead to perception of the sound. An existing model of the cochlea by Fragni`ere is first analysed by simulation. This passive model is found to have the properties that the living cochlea does in terms of the frequency response. An analog VLSI circuit implementation of this cochlear model in CMOS weak inversion is proposed, using log-domain filters in current domain. It is fabricated on a chip and a measurement of a basilar membrane section is performed. The measurement shows a reasonable agreement to the model. However, the circuit is found to have a problem related to transistor mismatch, causing different behaviour in identical circuit blocks. An active cochlear model is proposed to overcome this problem. The model incorporates the effect of the outer hair cells in the living cochlea, which controls the quality factor of the basilar membrane filters. The outer hair cells are incorporated as an extra voltage source in series with the basilar membrane resonator. Its value saturates as the input signal becomes larger, making the behaviour rather closer to that of a passive model. The simulation results show this nonlinear phenomenon, which is also seen in the living cochlea. The contribution of this thesis is summarised as follows: a) the first CMOS weak inversion current domain basilar membrane resonator is designed and fabricated, and b) the first active two-dimensional cochlear model for analog VLSI implementation is developed.

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6

Murphy, Chad Douglas. "Implementing anisotropic diffusion using analog VLSI." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0018/MQ48284.pdf.

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7

Xing, Nianwei. "Measuring optical flow using analog VLSI." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2002. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63569.pdf.

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8

Watts, Lloyd Mead Carver. "Cochlear mechanics : analysis and analog VLSI /." Diss., Pasadena, Calif. : California Institute of Technology, 1993. http://resolver.caltech.edu/CaltechETD:etd-07022004-115127.

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9

Koosh, Vincent F. Goodman Rodney. "Analog computation and learning in VLSI /." Diss., Pasadena, Calif. : California Institute of Technology, 2001. http://resolver.caltech.edu/CaltechETD:etd-10022001-201911.

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10

Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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11

Mortara, Alessandro. "Communication techniques for analog VLSI perceptive systems /." [S.l.] : [s.n.], 1995. http://library.epfl.ch/theses/?nr=1329.

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12

Gulino, Fabio G. "Consistency-enhanced anisotropic diffusion in analog VLSI." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63520.pdf.

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13

Tavakoli, Dastjerdi Maziar 1976. "Analog VLSI circuits for inertial sensory systems." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86766.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (leaves 67-68).
by Maziar Tavakoli Dastjerdi.
S.M.

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14

Huang, Shu-Chuan. "Systematic design solutions for analog VLSI circuits /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487850665560538.

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15

Dalloul, Nizar M., and Elie J. Baghdady. "MODELS OF ANALOG VLSI LOW-NOISE MULTIPLIERS." International Foundation for Telemetering, 1986. http://hdl.handle.net/10150/615392.

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International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevada
The class of Steerable Localized Injection Multipliers (SLIM) is known to be of high speed with least self-noise among all known analog multiplication techniques, and to be highly suited for VLSI implementation. SLIM design with predictable bounds on multiplication error due to intrinsic circuit noise requires valid noise generation modeling. Two models of SLIM noise sourcing are formulated: a small-signal model and a largesignal model. These noise models were simulated using SPICE to determine the power spectral density of SLIM output noise. The output power spectral density was shown to be flat over the frequency range up to 100MHZ, in agreement with prior experimental results.

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16

Dugger, Jeffery Don. "Adaptive Analog VLSI Signal Processing and Neural Networks." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5294.

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Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid foundation for future development of large-scale, compact, low-power adaptive parallel analog computation systems. The investigation described here started with observation of this potential learning capability and led to the first derivation and characterization of the floating-gate pFET correlation learning rule. Starting with two synapses sharing the same error signal, we progressed from phase correlation experiments through correlation experiments involving harmonically related sinusoids, culminating in learning the Fourier series coefficients of a square wave cite{kn:Dugger2000}. Extending these earlier two-input node experiments to the general case of correlated inputs required dealing with weight decay naturally exhibited by the learning rule. We introduced a source-follower floating-gate synapse as an improvement over our earlier source-degenerated floating-gate synapse in terms of relative weight decay cite{kn:Dugger2004}. A larger network of source-follower floating-gate synapses was fabricated and an FPGA-controlled testboard was designed and built. This more sophisticated system provides an excellent framework for exploring applications to multi-input, multi-node adaptive filtering applications. Adaptive channel equalization provided a practical test-case illustrating the use of these adaptive systems in solving real-world problems. The same system could easily be applied to noise and echo cancellation in communication systems and system identification tasks in optimal control problems. We envision the commercialization of these adaptive analog VLSI systems as practical products within a couple of years.

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17

Bridges, Seth. "Low-power visual pattern classification in analog VLSI /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6984.

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18

Moini, Alireza. "Synthesis of biological vision models using analog VLSI /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm712.pdf.

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19

Pedroni, Volnei A. Yariv Amnon Yariv Amnon. "VLSI systems for analog and Hamming parallel computation /." Diss., Pasadena, Calif. : California Institute of Technology, 1995. http://resolver.caltech.edu/CaltechETD:etd-10172007-153538.

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20

Tavakoli, Dastjerdi Maziar 1976. "An analog VLSI front end for pulse oximetry." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36184.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 210-216).
Pulse oximetry is a fast, noninvasive, easy-to-use, and continuous method for monitoring the oxygen saturation of a patient's blood. In modem medical practice, blood oxygen level is considered one of the important vital signs of the body. The pulse oximeter system consists of an optoelectronic sensor that is normally placed on the subject's finger and a signal processing unit that computes the oxygen saturation. It uses red and infrared LEDs to illuminate the subject's finger. We present an advanced logarithmic photoreceptor which takes advantage of techniques such as distributed (cascaded) amplification, automatic loop gain control, and parasitic capacitance unilateralization to improve the performance and ameliorate certain shortcomings of existing logarithmic photoreceptors. These improvements allow us to reduce LED power significantly because of a more sensitive photoreceptor. Furthermore, the exploitation of the logarithmic nonlinearity inherent in transistors eliminates the need of performing some of the mathematical operations which are traditionally done in digital domain to calculate oxygen saturation and allows for a very area-efficient all-analog implementation. The need for an ADC and a DSP is thus completely eliminated.
(cont.) We show that our analog pulse oximeter constructed with red and infrared LEDs and our novel photoreceptor at its front end consumes 4.8mW of power whereas a custom-designed ASIC digital implementation (employing a conventional linear photoreceptor) and the best commercial pulse oximeter are estimated to dissipate 15.7mW and 55mW, respectively. The direct result of such power efficiency is that while the batteries in this commercial oximeter need replacement every 5 days (assuming four "AAA" 1.5V batteries are used), our analog pulse oximeter allows 2 months of operation. Therefore, our oximeter is well suited for portable medical applications such as continuous home-care monitoring for elderly or chronic patients, emergency patient transport, remote soldier monitoring, and wireless medical sensing.
by Maziar Tavakoli Dastjerdi.
Ph.D.

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21

Motamed, Ali. "Low-voltage analog VLSI circuits and signal processing /." The Ohio State University, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487942182325593.

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22

Körner, Tim. "Analog VLSI implementation of a local cluster neural net /." Paderborn : HNI, 2000. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=015378431&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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23

Athreya, Jayantha Krishna V. "An analog VLSI architecture for image smoothing and segmentation." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0028/MQ39633.pdf.

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24

Tung, Kenny W. L. Carleton University Dissertation Engineering Electronics. "A technique for on-chip analog VLSI circuit testing." Ottawa, 1993.

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25

Delbrück, Tobias Mead Carver. "Investigations of analog VLSI visual transduction and motion processing /." Diss., Pasadena, Calif. : California Institute of Technology, 1993. http://resolver.caltech.edu/CaltechETD:etd-07022004-144710.

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26

Leonard, Jason 1976. "Analog VLSI implementation of synaptic modification in realistic neurons." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47903.

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Thesis (S.M. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (p. 79).
An analog VLSI implementation of synaptic modification in realistic neurons is presented. The implementation uses CMOS integrated circuit technology to emulate the electrical behaviors of the neuron membrane, dendrite, and synapse, using principles based on the actual biology. The synapse circuitry includes a mechanism for the modification of the synaptic conductance. The circuits were simulated, layed out, and submitted for fabrication.
by Jason Leonard.
S.M.and M.Eng.

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27

Zarabadi, Seyed Ramezan. "Design of analog VLSI circuits in BICMOS/CMOS technology /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487777170407338.

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28

To, Hing-yan. "Statistical Analysis and Design Techniques for Analog VLSI Circuits /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487928649989917.

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29

Bragg, Julian Alexander. "A biomorphic analog VLSI implementation of a mammalian motor unit." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20693.

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30

Peiris, Vincent. "Mixed analog digital VLSI implementation of a Kohonen neural network /." [S.l.] : [s.n.], 1994. http://library.epfl.ch/theses/?nr=1295.

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31

Rasche, Christoph Albrecht. "Analog VLSI circuits for emulating computational features of pyramidal cells /." [S.l.] : [s.n.], 1999. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13268.

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32

Gedra, David R. "Design of a VLSI charge-coupled device analog delay line." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA296475.

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33

Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.

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34

Qumsieh, Ala. "An analog VLSI implementation of an attention-based saccade generator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0005/MQ44036.pdf.

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35

McQuirk, Ignacio Sean. "An Analog VLSI Chip for Estimating the Focus of Expansion." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/6771.

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For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a real-time analog VLSI chip which estimates the focus of expansion (FOE) from measured time-varying images. Our approach assumes a camera moving through a fixed world with translational velocity; the FOE is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the FOE gives the direction of 3-D translation. The algorithm we use for estimating the FOE minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the FOE. This minimization is not straightforward, because the relationship between the brightness derivatives depends on the unknown distance to the surface being imaged. However, image points where brightness is instantaneously constant play a critical role. Ideally, the FOE would be at the intersection of the tangents to the iso-brightness contours at these "stationary" points. In practice, brightness derivatives are hard to estimate accurately given that the image is quite noisy. Reliable results can nevertheless be obtained if the image contains many stationary points and the point is found that minimizes the sum of squares of the perpendicular distances from the tangents at the stationary points. The FOE chip calculates the gradient of this least-squares minimization sum, and the estimation is performed by closing a feedback loop around it. The chip has been implemented using an embedded CCD imager for image acquisition and a row-parallel processing scheme. A 64 x 64 version was fabricated in a 2um CCD/ BiCMOS process through MOSIS with a design goal of 200 mW of on-chip power, a top frame rate of 1000 frames/second, and a basic accuracy of 5%. A complete experimental system which estimates the FOE in real time using real motion and image scenes is demonstrated.

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36

Haas, Alfred M. "Analog VLSI circuits for biosensors, neural signal processing and prosthetics." College Park, Md.: University of Maryland, 2009. http://hdl.handle.net/1903/9175.

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Thesis (Ph.D.) -- University of Maryland, College Park, 2009.
Thesis research directed by: Dept. of Electrical and Computer Engineering . Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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37

Monzon, Joshua Jen C. "Analog VLSI circuit design of spike-timing-dependent synaptic plasticity." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/54636.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 61-63).
Synaptic plasticity is the ability of a synaptic connection to change in strength and is believed to be the basis for learning and memory. Currently, two types of synaptic plasticity exist. First is the spike-timing-dependent-plasticity (STDP), a timing-based protocol that suggests that the efficacy of synaptic connections is modulated by the relative timing between presynaptic and postsynaptic stimuli. The second type is the Bienenstock-Cooper-Munro (BCM) learning rule, a classical ratebased protocol which states that the rate of presynaptic stimulation modulates the synaptic strength. Several theoretical models were developed to explain the two forms of plasticity but none of these models came close in identifying the biophysical mechanism of plasticity. Other studies focused instead on developing neuromorphic systems of synaptic plasticity. These systems used simple curve fitting methods that were able to reproduce some types of STDP but still failed to shed light on the biophysical basis of STDP. Furthermore, none of these neuromorphic systems were able to reproduce the various forms of STDP and relate them to the BCM rule. However, a recent discovery resulted in a new unified model that explains the general biophysical process governing synaptic plasticity using fundamental ideas regarding the biochemical reactions and kinetics within the synapse. This brilliant model considers all types of STDP and relates them to the BCM rule, giving us a fresh new approach to construct a unique system that overcomes all the challenges that existing neuromorphic systems faced. Here, we propose a novel analog verylarge- scale-integration (aVLSI) circuit that successfully and accurately captures the whole picture of synaptic plasticity based from the results of this latest unified model. Our circuit was tested for all types of STDP and for each of these tests, our design was able to reproduce the results predicted by the new-found model. Two inputs are required by the system, a glutamate signal that carries information about the presynaptic stimuli and a dendritic action potential signal that contains information about the postsynaptic stimuli. These two inputs give rise to changes in the excitatory postsynaptic current which represents the modifiable synaptic efficacy output. Finally, we also present several techniques and alternative circuit designs that will further improve the performance of our neuromorphic system.
by Joshua Jen C. Monzon.
M.Eng.

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38

Dron, Lisa Glitsch 1956. "Computing 3-D motion in custom analog and digital VLSI." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/37745.

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39

Robinson, David Lyle. "Automatic Synthesis of VLSI Layout for Analog Continuous-time Filters." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4913.

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Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits. With analog circuits, however, there is little room for drift. Parasitic influence directly affects signal integrity and the functionality of the circuit. The underlying problem automatic VLSI layout programs face is how to minimize this influence. This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods.

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40

Dalloul, Nizar M., and Elie J. Baghdady. "A SURVEY AND COMPARISON OF MULTIPLICATION TECHNIQUES FOR ANALOG VLSI." International Foundation for Telemetering, 1986. http://hdl.handle.net/10150/615391.

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International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevada
This paper addresses the problem of analog multiplication for analog VLSI implementation, with particular emphasis on multiplication accuracy (low intrinsic noise) and speed. High-speed low noise analog multiplication for analog VLSI has very important implications in analog signal processing, signal generation, signal detection and ultra precise frequency and phase control. The various candidate multiplier mechanisms and circuits proposed todate are surveyed and a comprehensive comparison of them developed, leading to the conclusion that the Steerable Localized Injection Multiplier (SLIM) holds the greatest promise for low noise and high speed analog VLSI multiplication.

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41

De, Guzman Ethan Paul Palisoc. "Energy Efficient Computing using Scalable General Purpose Analog Processors." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2305.

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Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equation solving. However, analog computing also comes with drawbacks such as its sensitivity to process variation and noise, limited scalability, programming difficulty, and poor compatibility with digital circuits and design tools. We propose to leverage the strengths of analog circuits and avoid its weaknesses by using digital circuits and time-encoded computation. Time-encoded circuits also operate on continuous data but are implemented using digital circuits. We propose a novel scalable general purpose analog processor using time-encoded circuits that is well suited for emerging applications that require high numeric precision. The processor’s datapath, including time-domain register file and function units are described. We evaluate our proposed approach using an implementation that is simulated with a 0.18µm TSMC process and demonstrate that this approach improves the performance of a scientific benchmark by 4x compared against conventional analog implementations and improves energy consumption by 146x compared against digital implementations.

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42

Dickson, Jeffrey Allen Goodman Rodney. "Integration of analog VLSI and thin films for chemical sensing arrays /." Diss., Pasadena, Calif. : California Institute of Technology, 1999. http://resolver.caltech.edu/CaltechETD:etd-02062008-131420.

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43

BADAOUI, RAOUL. "APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

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44

Sivilotti, Massimo Antonio Mead Carver. "Wiring considerations in analog VLSI systems, with application to field-programmable networks /." Diss., Pasadena, Calif. : California Institute of Technology, 1991. http://resolver.caltech.edu/CaltechETD:etd-07122007-134330.

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45

Khachab, Nabil Ibrahim. "Analog CMOS nonlinear cells and their applications in VLSI signal and information processing /." The Ohio State University, 1990. http://rave.ohiolink.edu/etdc/view?acc_num=osu148768520496624.

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46

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

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47

KANKIPATI, SUNDER RAJAN. "MACRO MODEL GENERATION FOR SYNTHESIS OF ANALOG AND MIXED SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077297705.

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48

Pradhan, Almitra. "Accurate Analog Synthesis Based On Circuit Matrix Models." University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1258661691.

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49

Hwang, Changku. "A universal approach to the design of low voltage constant-gm analog VLSI circuits /." The Ohio State University, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=osu148793595884748.

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50

Hung, Chung-Chih. "Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications /." The Ohio State University, 1997. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487943341527253.

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Dissertations / Theses on the topic 'Analog VLSI'

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