Dissertations / Theses on the topic 'Analog electronics and interfaces'
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Harikumar, Prakash. "Building Blocks for Low-Voltage Analog-to-Digital Interfaces." Licentiate thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111958.
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In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters. To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/
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U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.
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Mosciatti, Thomas. "Nanostructured hybrid interfaces for supramolecular electronics." Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAF024/document.
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Cette thèse a exploré comment, en introduisant des interfaces nanostructurées dans des systèmes supramoléculaires pour l'électronique, il est possible de moduler, ajouter et étudier les propriétés des nano-objets. Sur ces applications de fonctionnalisation auto-assemblée des limites, le contrôle thermique sur les propriétés intrinsèques, la modulation lumineuse des structures chimiques et physiques ont été trouvés comme étant des techniques adaptées pour affecter le système supramoléculaire fonctionnalisé nano-structuré pour l'électronique organique. Des nanoparticules d'or ont été utilisées pour générer des interfaces qui ont été fonctionnalisés afin d'étudier l'effet de transport de charge dans un transistor à couche mince organique. Par conséquent, cette approche a été intensifiée en employant des molécules photochromiques et par le contrôle du piégeage de charge par irradiation de lumière. Le même principe a été utilisé pour moduler l'injection de charge dans les transistors à haute performances, par fonctionnalisation des électrodes appropriées avec des diaryléthènes. Enfin, une approche différente pour contrôler le dépôt de flocons de graphène sur surface diélectrique a été employée avec succès pour concevoir de nouveaux éléments de mémoire par ajustement de l'alignement des niveaux énergétiques du graphène après recuit thermiqueThis thesis explored how, by introducing nanostructured interfaces in supramolecular system for electronics, is possible to modulate, tune, add and study properties arising from nano-objects. On these purposes self-assembled functionalization of boundaries, thermal control on intrinsic properties, light modulation of chemical and physical structures have been found as tailored techniques to affect nano-structured functionalized supramolecular system for organic electronics. Gold nanoparticles have been used to generate interfaces that have been functionalized in order to study charge transport effect in organic thin film transistor. Therefore this approach has been stepped up employing photochromic molecules and controlling charge trapping with light irradiation. The same principle has been used to modulate charge injection in high performance transistors, by functionalizing electrodes with appropriate diarylethenes. Finally, a different approach of controlling deposition of graphene flakes on dielectric surface has been successfully employed to design new memory elements by tuning energetic level alignment of graphene with thermal annealing
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Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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Wang, Haibo. "Field programmable analog array synthesis." Diss., The University of Arizona, 2002. http://hdl.handle.net/10150/289777.
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Field programmable analog arrays (FPAAs), the analog counterparts of digital field programmable gate arrays (FPGAs), are suitable for prototyping analog circuits and implementing dynamically re-configurable analog systems. Although various FPAA architectures have been recently developed, very little work has been reported in the area of design automation for field programmable analog arrays. The lack of sophisticated FPAA synthesis tools is becoming one of the key limitations toward fully exploiting the advantages of FPAAs. To address this problem, this dissertation presents a complete synthesis flow that can automatically translate abstract-level analog function descriptions into FPAA circuit implementations. The proposed synthesis flow consists of function decomposition, macro-cell synthesis, placement & routing, and post-placement simulation subroutines. The function decomposition subroutine is aimed at decomposing high-order analog functions into low-order sub-functions. This not only increases the accuracy of the realized analog functions, but also reduces the routing complexity of the synthesized circuits. The macro-cell synthesis subroutine generates circuit implementations for the decomposed sub-functions. Then, FPAA placement & routing is performed to map the synthesized analog circuits onto FPAA chips. The final stage of the synthesis flow is post-placement simulation, which is used to verify that the synthesized circuits meet performance specifications. The major contributions of this dissertation are techniques developed for implementing the FPAA synthesis flow. In the work of function decomposition, we developed theoretical proofs for two optimization criteria that were previously used to search optimal function decomposition solutions. In addition, we developed more efficient procedures to search optimal function decomposition solutions. To implement the macro-cell synthesis subroutine, we proposed a modified signal flow graph to represent FPAA circuits. Graph transformations are introduced for exploring alternative circuit structures in FPAA synthesis. Finally, in the work of FPAA placement and routing, an efficient method for estimating FPAA parasitic effects was developed. The effectiveness of the developed techniques is demonstrated by the experiments of synthesizing various FPAA circuits. The proposed synthesis methodologies will significantly simplify the use of FPAAs, and consequently make FPAAs more appealing in analog design.
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Chaumy, Guillaume. "Tunable metal-organic interfaces for spin electronics." Thesis, Strasbourg, 2019. http://www.theses.fr/2019STRAE030.
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L’objet de cette thèse est l’étude de l’interface entre les métaux et les matériaux organiques, avec pour objectif la réalisation de vannes de spin organiques. Pour ce faire, nous avons étudié des transistors organiques à effet de champ à grille électrolytique dans une structure planaire, et analysé leurs propriétés de transport et d’interface sous l’application de différents stimuli (température, dopage, champ magnétique…). Cette structure nous permet de nous rapprocher des conditions optimales pour l’injection et la détection de spin, mais elle nous a amenés à revoir la définition standard de la propriété intrinsèque des interfaces. Nous avons mis en évidence une résistance spécifique de contact particulièrement faible qui décroit avec la miniaturisation des dispositifs, ainsi que la magnétorésistance des résistances (spécifiques) d’interfaceThis thesis studies the interface between metals and organic materials, aiming the realization of organic spin-valves. To that end, we studied planar electrolyte-gated field-effect organic transistors and analysed their transport and interface properties under the application of different stimuli (temperature, doping, magnetic field…). This structure allowed us to approach the optimal conditions for spin injection and detection but led to redefine the standard intrinsic property of interfaces. We exhibited a very low specific contact resistance, that decreases with the downscaling of the devices, and the magnetoresistance of specific interface resistance
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Hematy, Arman. "Digitally programmable analog log-domain filters." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21302.
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Frequency filtering networks have numerous applications in consumer products. For high-speed and low-voltage systems, continuous-time filters are the preferred choice---these filters have become very popular with the wireless industry. Unfortunately, continuous-time filters have a high production cost since they are not geared toward mass production. This thesis proposes an analog filter structure that can be both mass produced and customized for a particular application. Such a structure is possible through the use of a state-space approach, and log-domain filtering.First, a general state-space formulation is presented; a method of obtaining the state-space coefficients from an equivalent LC ladder network is described. Such a set of coefficients results in a realization with low noise and low sensitivity properties. Next, the effects of coefficient quantization on a state-space filter's response is examined. An optimization procedure is outlined to obtain the best approximation to the desired transfer function.
In order to implement the proposed filter structure, a universal log-domain cell is presented. Such a cell can be used to produce the stages required by any filter design (input, output, and integrator stages). Using the universal log-domain cell, a systematic approach to realizing any arbitrary-order filter is described. Next, the peripheral components needed to complete the filter are presented. Included are a novel 8-bit DAC, used to implement the programmable current sources that bias the filter, and V-to-I and I-to-V converters, used to interface the current-mode filter with voltage-mode instruments.
Finally, experimental results from several prototype boards are used to verify the feasibility of the proposed filter structure. These boards make use of ICs fabricated in a 0.8 mum BiCMOS technology; included are an IC with stand-alone programmable current sources, an IC with a third-order filter, as well as one with a fifth-order filter. The results from the test boards clearly demonstrate the programmability and functionality of digitally programmable state-space filters.
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Hawrysh, Evan M. (Evan Mark). "Digital architectures for analog signal generation." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24058.
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Analog and mixed-signal testing is far more complex than its digital equivalent. This thesis will identify the analog test requirements through an extensive analysis of integrated circuit testing, possible error sources, and the different levels of test hierarchy. The results will show that analog testing requires spectrally pure, high-quality predictable test signals. These signals are most robust when reproduced through digital techniques such as direct digital frequency synthesis. Delta-sigma ($ Delta Sigma$) modulation is perhaps the most versatile technique, as it can precisely encode arbitrary analog waveforms into a pulse-density modulated (PDM), infinite-length, single bit-wide pattern. The noise-shaping characteristics of the $ Delta Sigma$ modulator also allow for simple reconstruction of the embedded signal. Unfortunately, on-chip signal generation using this method is currently hindered by the high area overhead and limited programmability of $ Delta Sigma$ modulation oscillators. We will introduce the concept of forcing the PDM pattern to be finite in length and thus periodic. Although other periodic encoding algorithms exist, forced-periodic PDM patterns will be shown to be far superior for their precise control over signal amplitude, frequency, phase, and also for their ability to encode an arbitrary waveform. Its effectiveness will be demonstrated with several experiments of single- and multi-tone waveforms of varying degrees of complexity. By creating a fixed-length pattern, we can take advantage of many common digital built-in self-test (BIST) concepts such as scan and RAMBIST, found on most digital and mixed-signal integrated circuits, to supply the necessary hardware. We will show how analog signal generation can be integrated into digital ICs using any or all of the IEEE 1149.1-1990 standard, embedded RAMs, and scan chains. These applications will indeed prove that with very little additional hardware, on-chip, high-quality analog signal gene
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Harikumar, Prakash. "Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces." Doctoral thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-122730.
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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential. The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2. The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2. The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.
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Shen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.
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This thesis studies the floating-point analog-to-digital converter (FP-ADC). The first attempt is to analyze the parallel architecture of the floating-point converter, which is our research base. The characteristics and specifications of the floating-point AID converter are described. Simulations of the parallel architecture of the floating-point A/D converter were conceived, run and presented here to support the theoretically derived FP-ADC transfer characteristics.
After analyzing the parallel architecture of the floating-point A/D converter, the following work is to provide a way of minimizing the conversion time as well as keeping the precision of the floating point A/D converter (FP-ADC) by implementing the parallel architecture with Field Programmable Gate Arrays (FPGA).
The thesis presents the design and practical implementation of the parallel FP-ADC, based on a FPGA and other hybrid components-of-the-shelf. The correctness of the design was verified by computer simulation, while the functionality of the implemented FP-ADC was tested on a test bench controlled by a PC. (Abstract shortened by UMI.)
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Lu, Albert K. (Albert Keishi). "Analog signal generation using delta-sigma modulation." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68040.
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This thesis introduces a method by which low-frequency analog waveforms may be generated using delta-sigma modulation. The technique centers around a delta-sigma based oscillator which, with the exception of a continuous-time low-pass filter, is entirely digital and provides precise control over the oscillation frequency, amplitude, and phase. The incorporation of a delta-sigma modulator inside the resonator loop leads to an efficient implementation requiring 4 multi-bit adders, 4 delay elements, and a 2-input multiplexer. Two additional circuits, which generate multi-tone and piece-wise linear waveforms, are presented as extensions of the original single-tone design.Prototypes of the proposed designs have been assembled using Field-Programmable Gate Array, and BiCMOS technologies. The test results have successfully verified the validity of the proposed concepts indicating dynamic ranges exceeding 80 dB and 60 dB for the single and multi-tone generators respectively.
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Braun, Slawomir. "Studies of Materials and Interfaces for Organic Electronics." Doctoral thesis, Linköping : Univ, 2007. http://www.bibl.liu.se/liupubl/disp/disp2007/tek1103s.pdf.
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Sellner, Stefan. "Organic inorganic interfaces for applications in organic electronics." [S.l. : s.n.], 2006. http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-25843.
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Syed, Arsalan Jawed. "Analog-to-Digital Converter Design for Non-Uniform Quantization." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2654.
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The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.
High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.
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Debski, Michal. "Self-calibrating floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/26884.
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The Floating-Point Analog-to-Digital Converter (FPADC) is an extended version of the Fixed-Point ADC. It is designed to deal with a broader dynamic range of signals while exhibiting a smaller relative quantization error. The traditional implementation of the FPADC is characterized by a high relative precision, but it requires high-precision high-speed components in order to achieve that. The high precision of the high-speed components comes at a greater cost. This constraint limits the availability of FPADCs to high-priced designs.
The thesis addresses a low-speed and a low-cost calibration approach for the FPADC. It presents the architecture, design and implementation platform of a self-calibrating differential predictive FPADC which is characterized by utilizing low-grade components. The precision is maintained at high values by additional hardware that periodically performs calibration cycles. Starting with a review of the field of FPADC the thesis develops the understanding of the Floating Point ADCs. The implementation is then extended to include a high precision low speed calibrating ADC. A complete implementation of the design is carried out and described. Finally, experimental measurements are performed to test the new FPADC and present the acquired results.
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Pishdad, Bardia. "Nyquist-rate analog-to-digital conversion with calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29544.
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Analog-to-Digital Converter (ADC) microcircuits are required to meet stringent accuracy specifications in spite of their analog components' inherent nonidealities as well as the accuracy limitations due to fabrication technology. In this thesis, a 3-step Nyquist rate ADC is presented which makes use of bitstream processing to calibrate the digital-to-analog converter (DAC) and the residue amplifier, while using the same hardware to calibrate the sub-ADC. The system is designed to provide programmability and calibrate undesired circuit characteristics such as offset, gain error, and nonlinearity. Thus, the DAC can tolerate gain errors much higher than the standard amount, and has the potential to completely cancel nonlinearity and offsets in its transfer function. The offset of the residue amplifier can also be calibrated with this system. Moreover, the system eliminates the need for a reference ladder in the sub-ADC, and calibrates comparator offsets. Simulation and experimental results of the circuits fabricated in a 0.18mum CMOS process are presented.
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AGARWAL, NEETU. "ON FORMAL DEVELOPMENT OF ANALOG/DIGITAL INTERFACES IN MIXED-SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123772655.
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Zareba, Grzegorz Szczepan. "Behavioral simulation of analog to digital converters." Diss., The University of Arizona, 2005. http://hdl.handle.net/10150/290152.
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The design of high-speed and high-resolution data converters is very difficult due to complexity of architectures used for converting analog signals into their digital representation. Since the introduction of the simplest conversion technique called parallel or flash technique numerous other architectures have been developed, for example n-stage pipeline, reference feed-forward architecture, folding and interpolating technique. The variety of A/D converter architectures additionally complicates design process due to fact that there is no available behavioral simulator, which can be utilized to support verification of particular converter's design. Many effects and imperfections present in A/D converters influence their performance, for example: switching imperfections, finite gain, clock jitter, and switching and coupling (Electro-Magnetic and substrate perturbations). In most cases several simulation tools have to be used to very performance of designed A/D converter. In this work a new methodology for behavioral simulation of A/D converters has been presented. Novel approach in behavioral modeling of A/D converters is based on utilization of Dynamic Linked Libraries (DLLs) to encapsulate behavior of basic modules of A/D converters. Predefined Basic Building Modules (BBMs) of A/D converters such as comparators, folding circuits, analog switches, binary encoders and many others are used to form a behavioral model of various types of A/D converters. Imperfections of BBMs are separated from the simulator framework and included into behavioral description of BBMs kept in DLL modules. Utilization of DLL modules gives a very convenient way for modifying BBMs independently from the simulator framework, and because DLL modules are executable files simulation time is significantly reduced (no translation or interpretation of simulation language commands is needed). Developed Behavioral Simulator of A/D converters is implemented in Visual C++ language and is partially based on an event driven simulation scheme and a data flow technique. The data flow technique was introduced into the simulator architecture to reduce number of events generated during simulation process, which additionally reduces simulation time. Several BBMs have been defined and constructed as DLL modules to support simulation of various types of A/D converters including flash, multi-stage, pipelined, and folding A/D converters.
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Aouini, Sadok. "A programmable analog Gaussian noise generator for test applications /." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=99401.
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This thesis presents a robust programmable analog Gaussian noise generator suitable for mixed-signal test applications. Unlike conventional methods, noise generators employing a linear feedback shift register (LFSR) or resistor thermal noise amplification techniques, the user has full control over the characteristics of the Gaussian signal. Indeed, the frequency band, the mean, and the variance of the distribution are fully programmable over the voltage range within the supply rails. The method consists of digitally encoding the specified Gaussian signal in a random access memory (RAM), using pulse-density modulation, followed by filtering the output bit stream using an analog low-pass filter. It is demonstrated that the quality of the generated noise signal is independent of the quality of the filter used; hence, making the noise source highly robust. The output of the noise generator accurately models a real Gaussian signal, even at high sigma values; thus, making it a very effective and predictable dithering signal. Two applications of the proposed Gaussian noise source are demonstrated: histogram testing of analog-to-digital converters (ADCs) and high-resolution digitization. In addition, a high-voltage automotive test instrument that supports the high-resolution digitization process proposed is outlined.
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Taillefer, Christopher. "Analog-to-digital conversion via time-mode signal processing." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=18669.
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Conventional voltage-mode analog-to-digital converters use voltage amplifiers, voltage comparators, and switch capacitor networks to perform their signal processing. When compared to digital circuitry, these analog circuit blocks consume significant power, occupy large silicon areas, and operate at relatively slow data processing speeds. A signal processing methodology is proposed that performs analog-to-digital conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode signal processing, uses time-difference variables as an intermediate signal between the input voltage and digital output. The resulting silicon devices offer very compact, low power, high-speed, and robust analog-to-digital converter alternatives. There are five main analog-to-digital converter topologies: flash, successiveapproximation, pipeline, delta-sigma, and integrating converters. Each converter topology is presented in the context of the time-mode signal processing methodology. The circuits that implement each time-mode data converter are described and when appropriate system-level, transistor-level, and experimental results are revealed. Three integrated circuits (IC) were fabricated in a 0.18-µm CMOS technology to demonstrate the feasibility of the time-mode ADC methodology. The first IC implemented the time-mode comparator and a time-mode flash ADC. The timemode delta-sigma ADC design was demonstrated in the second IC. Two circuits were implemented in the third IC: a differential-input time-mode delta-sigma ADC and a cyclic (or algorithmic) ADC.Les convertisseurs conventionnels pour changer la tension analogique à une tension numérique emploient les amplificateurs de tension, les comparateurs de tension, et les résaux de condensateur sélectionable pour acquir leur traitement de signal. En comparaison le circuit des modules analogues vis-à-vis le circuit numérique nous constatons une augmentation de puissance, une superficie de silicium moins compacte, et un traitement de données beaucoup plus lent. Une méthodologie est proposée pour le traitement du signal qui établi la conversion analogue à numérique sur les signaux de tension et tout en mettant en oeuvre tous les circuits dans un format numérique de type circuit à semiconducteur oxyde-métal à symétrie complémentaire (CMOS). Cette méthodologie reconnue sur le nom de technique-temporelle donne un traitement de signal par domaine temporel en employant la variance de cadence entre les temps comme un signal intermédiare entre la tension d'entrée et la tension de sortie numérique. Les formats numériques de type circuit semiconducteur nous offrent une alternative en temps convertisseur d'analogue à numérique avec l'avantage d'une unité compact, robuste, un coût de puissance réduit, et une haute-vitesse efficace. Il existe cinq topologies principales dans les convertisseurs analogiques à numérique: flash, approximations successives, pipeline, delta-sigma, convertisseurs intégrés. Dans chacune des topologies mentionnées ci-dessus, le traitement de signal par technique-temporelle est une méthode réconnue. Les circuits employés par chaque convertisseur de donnée par technique temporelle sont décrits lorsque le niveau du système est approprié, le niveau du transitor, et les données expérimentales sont identifiés. Trois circuits intégrés (CI) ont été conçus et fabriqués, avec une technologie de 0,18-µm CMOS pour démontrer la possibilité de la méthodologie du techniquetemporelle convertisseur analogique-numéri
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Espinosa, Christlieb José Humberto. "Reducing complexity of consumer electronics interfaces using commonsense reasoning." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33202.
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Thesis (S.M.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2005.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 94-100).
User interfaces to consumer electronics devices - Video recorders, phones, cameras, washing machines, microwave ovens, etc. - are getting too complicated to be easily used by ordinary consumers. We believe that what is responsible for such complication is a design philosophy which simply maps functions the device can perform to controls like buttons and menu items. That leaves the users with the difficult cognitive task of mapping their goals onto the devices' capabilities - a frustrating and error-prone process. Our hypothesis is that we can provide better assistance to the user using Commonsense Reasoning leading to shorter interactions with the devices. Commonsense can infer the users' likely goals from watching their actions, and anticipate what capabilities of the device can fulfill the users' needs. As devices gain networking capabilities and interact with other devices, Commonsense can also help devices cooperate in support of the users' goals.
by José Humberto Espinosa Christlieb.
S.M.
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Sheriff, Bonnie Ann Collier C. Patrick Heath James M. "Silicon nanowires and silicon/molecular interfaces for nanoscale electronics /." Diss., Pasadena, Calif. : California Institute of Technology, 2009. http://resolver.caltech.edu/CaltechETD:etd-06302008-165534.
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Qumsieh, Ala. "An analog VLSI implementation of an attention-based saccade generator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0005/MQ44036.pdf.
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Wu, Yang 1974. "Monolithic nyquist rate analog to digital converter with digital calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29549.
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Nyquist rate analog to digital converter have always been an essential component in complex systems ranging from digital oscilloscope, radar, to modern telecommunication equipments. The fast-paced development in these complex systems has necessitated methods to improve resolution and power consumption of the analog to digital converters. The aim of this thesis is to offer one such method. The method involves the application of a digital DC reference source. The digital reference source will be proposed and used to remove mismatch, reduce comparator offset, thus improving the resolution of both flash and pipeline ADCs, while consuming no static power. The design of pipeline ADCs is also the emphasis of this work.The digital reference source consists of flip-flops and RC low-pass filters. By programming flip-flops with appropriate digital bit streams, accurate DC reference levels can be generated. The generated DC reference levels replace the need for reference ladder in Flash ADCs. Furthermore, with programmability provided by the digital reference source, the generated reference levels can be modified to reduce comparator offset. The comparator offset reduction algorithm is also applied to pipeline ADCs to reduce non-linear distortion.
The design details of pipeline ADC is also discussed in this work. Quantitative analyses have been provided in determining design parameters in various subsystems. The analyses ensure that a 10-bit resolution is achieved for the pipeline ADC. Both Flash ADC and pipeline ADC were implemented in a 0.25 mum and 0.18 mum CMOS process respectively, and results demonstrating their successful operation are presented.
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Ali-Bakhshian, Mohammad. "Digital processing of analog information adopting time-mode signal processing." Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114237.
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As CMOS technologies advance to 22-nm dimensions and below, constructing analog circuits in such advanced processes suffers many limitations, such as reduced signal swings, sensitivity to thermal noise effects, loss of accurate switching functions, to name just a few. Time-Mode Signal Processing (TMSP) is a technique that is believed to be well suited for solving many of these challenges. It can be defined as the detection, storage, and manipulation of sampled analog information using time-mode variables. One of the important advantages of TMSP is the ability to realize analog functions using digital logic structures. This technique has a long history of application in electronics; however, due to lack of some fundamental functions, the use of TM variables has been mostly limited to intermediate stage processing and it has been always associated with voltage/current-to-time and time-to-voltage/current conversion. These conversions necessitate the inclusion of analog blocks that contradict the digital advantage of TMSP. In this thesis, an intensive research has been presented that provides an appropriate foundation for the development of TMSP as a general processing tool. By proposing the new concept of delay interruption, a completely new asynchronous approach for the manipulation of TM variables is suggested. As a direct result of this approach, practical techniques for storage, addition and subtraction of time-mode variables are presented. To Extend the digital implementation of TMSP to a wider range of applications, the comprehensive design of a unity gain dual-path time-to-time integrator (accumulator) is demonstrated. This integrator is then used to implement a digital second-order delta-sigma modulator. Finally, to demonstrate the advantage of TMSP, a very low power and compact tunable interface for capacitive sensors is presented that is composed of a number of delay blocks associated with typical logic gates. All the proposed theories are supported by experimental results and post-layout simulations.The emphasis on the digital construction of the proposed circuits has been the first priority of this thesis. Having the building blocks implemented with a digital structure, provides the feasibility of a simple, synthesizable, and reconfigurable design where affordable circuit calibrations can be adopted to remove the effects of process variations.Les technologies CMOS progressant vers les procédés 22 nm et au delà, la abrication des circuits analogiques dans ces technologies se heurte a de nombreuses limitations. Entre autres limitations on peut citer la réduction d'amplitude des signaux, la sensibilité aux effets du bruit thermique et la perte de fonctions précises de commutation. Le traitement de signal en mode temps (TMSP pour Time-Mode Signal Processing) est une technique que l'on croit être bien adapté pour résoudre un grand nombre de problèmes relatifs a ces limitations. TMSP peut être défini comme la détection, le stockage et la manipulation de l'information analogique échantillonnée en utilisant des quantités de temps comme variables. L'un des avantages importants de TMSP est la capacité à réaliser des fonctions analogiques en utilisant des structures logiques digitales. Cette technique a une longue histoire en terme d'application en électronique. Cependant, en raison du manque de certaines fonctions fondamentales, l'utilisation de variables en mode temps a été limitée à une utilisation comme étape intermédiaire dans le traitement d'un signal et toujours dans le contexte d'une conversion tension/courant-temps et temps-tension/courant. Ces conversions nécessitent l'inclusion de blocs analogiques qui vont a l'encontre de l'avantage numérique des TMSP. Cette thèse fournit un fondement approprié pour le développement de TMSP comme outil général de traitement de signal. En proposant le concept nouveau d'interruption de retard, une toute nouvelle approche asynchrone pour la manipulation de variables en mode temps est suggéré. Comme conséquence directe de cette approche, des techniques pratiques pour le stockage, l'addition et la soustraction de variables en mode temps sont présentées. Pour étendre l'implémentation digitale de TMSP à une large gamme d'applications, la conception d'un intégrateur (accumulateur) à double voie temps- à -temps est démontrée. cet intégrateur est ensuite utilisé pour implémenter un modulateur delta-sigma de second ordre.Enfin, pour démontrer l'avantage de TMSP, une Interface de très basse puissance, compacte et réglable pour capteurs capacitifs est présenté. Cette interface est composé d'un certain nombre de blocs de retard associés à des portes logiques typiques. Toutes les théories proposées sont soutenues par des résultats expérimentaux et des simulations post-layout. L'implémentation digitale des circuits proposés a été la première priorité de cette thèse. En effet, une implémentation des bloc avec des structures digitales permet des conceptions simples, synthétisable et reconfigurables où des circuits de calibration très abordables peuvent être adoptées pour éliminer les effets des variations de process.
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Gottiparthy, Ramraj Wilamowski Bogdan M. "An accurate CMOS four-quadrant analog multiplier." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/master's/GOTTIPARTHY_RAMRAJ_15.pdf.
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Hu, Zongqi. "Analog integrated circuit design of hypertrellis decoders /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HU.
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Conway, Kevin Michael. "X-ray studies of solid state layers and interfaces." Thesis, Cardiff University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.238154.
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Piels, Molly. "Si/Ge photodiodes for coherent and analog communication." Thesis, University of California, Santa Barbara, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3612014.
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High-speed photodiodes have diverse applications in wireless and fiber communications. They can be used as output stages for antenna systems as well as receivers for fiber optic networks. Silicon is an attractive substrate material for photonic components for a number of reasons. Low cost manufacturing in CMOS fabrication facilities, low material loss at telecommunications wavelengths, and relatively simple co-packaging with electronics are all driving interest in silicon photonic devices. Since silicon does not absorb light at telecommunications wavelengths, photodetector fabrication requires the integration of either III-V materials or germanium. Recent work on germanium photodetectors has focused on low-capacitance devices suitable for integration with silicon electronics. These devices have excellent bandwidth and efficiency, but have not been designed for the levels of photocurrent required by coherent and analog systems. This thesis explores the design, fabrication, and measurement of photodetectors fabricated on silicon with germanium absorbing regions for high speed and high power performance.
There are numerous design trade-offs between speed, efficiency, and output power. Designing for high bandwidth favors small devices for low capacitance. Small devices require abrupt absorption profiles for good efficiency, but design for high output power favors large devices with dilute absorption. The absorption profile can be controlled by the absorber layer thickness, but this will also affect the bandwidth and power handling. This work quantifies the trade-offs between high speed, high efficiency, and high power design. Intrinsic region thickness and absorption profile are identified as the most important design variables. For PIN structures, the absorption profile and intrinsic region thickness are both functions of the Ge thickness, but in uni-traveling carrier (UTC) structures the absorption profile and intrinsic region can be designed independently. This allows optimization of the absorption profile independently from the RC-limited frequency response and compression current and ultimately enables larger saturation current-bandwidth products. This thesis includes the first theory, fabrication, and measurement of a uni-traveling carrier photodiode on the Si/Ge platform. Key contributions include an accurate nonlinear device model and a complete set of processes and design rules for fabricating Ge devices in the UCSB nanofab. The UTC structure is shown to be useful in extending the bandwidth and power handling capabilities of waveguide-integrated photodiodes, especially at high frequencies.
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Dufort, Benoit. "Analog signal generation using periodic sigma-delta modulated streams." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0018/NQ55325.pdf.
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Gustafsson, E. Martin I. "Reconfigurable Analog to Digital Converters for Low Power Wireless Applications." Doctoral thesis, Kista : KTH School of Information and Communication Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4774.
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Smith, Christopher T. "Graphene oxide material interfaces in electronics, energy and environmental membranes." Thesis, University of Surrey, 2016. http://epubs.surrey.ac.uk/811137/.
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The wonder material graphene promises to revolutionise countless applications as a result of its remarkable properties. However, an inability to process graphene in aqueous solution inhibits its potential for use in mass produced practical applications. This thesis investigates the use of graphene oxide (GO), a solution processable graphene based material produced from graphite in various applications. GO can be used to produce a graphene like material, reduced graphene oxide (rGO) which is also investigated. The scale up of GO is examined, showing no discernible difference to the final product with increasing batch sizes. By varying the concentration of oxidisers in the synthesis method, a series of GO materials with differing degrees of disorder and solution process ability are produced and characterised. Using this series of GO materials, a model is proposed to explain the effect of the oxidation process on the GO flakes. Using Raman spectroscopy, a decrease in average sp2 cluster size to approximately 1.2 nm is shown. This causes an increase in internal stress and structural disorder resulting in the broadening of the characteristic D and G peaks from 47 cm-1 and 26 cm-1 to 118 ± 6 cm-1 and 72 ± 5 cm-1, respectively. Thermogravimetric analysis (TGA) results confirm this increase in disorder, showing a decrease in the thermal decomposition temperature in air from 700oC to 450oC as oxygen in the atmosphere preferentially target sites of disorder. This analysis is used to determine the disorder present in a range of rGO samples, to determine the best material for use in various applications. The disorder present in GO also isolates sp2 clusters, resulting in an increase in the band gap ranging from 0.02eV to 3.4 eV, while the reduction methods tested restore conjugation between isolated regions, causing the band gap to drop significantly. GO is used as a hole transport layer in high efficiency organic photovoltaic (OPV) devices, producing power conversion efficiencies (PCE) of approximately 5% using the polymer blend Poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)]: Phenyl-C70-butyric acid methyl ester (PCDTBT:PC70BM) as the active layer. This represents an increase of 90% (+ 2.4% PCE) over devices without a hole transport layer, and results in similar efficiencies to devices using the standard material PEDOT:PSS. Additionally, due to the chemical stability of GO, the shelf lifetime of GO OPV devices is improved by 62% (+ 3200 hours) when compared with a reference PEDOT:PSS device. ii Using a low temperature (< 250oC) simultaneous spray coating chemical reduction method; GO films are sprayed and chemically reduced on a surface using vitamin C, while the conductivity is monitored in real time. This allows for a conductivity increase of 5 orders of magnitude, resulting in thin films with 16.68kΩ/□ sheet resistance and 66.8% transmission (measured at 550nm). This conductivity ratio, i.e. the electrical conductivity divided by the optical conductivity (ςDC/ςOp), of 0.05 for the devices is comparable with other rGO based conducting networks reported, produced without the need for high temperatures, treated substrates or toxic reducing agents, making it practical for use on flexible plastic substrates. Importantly, Raman analysis of the thin films suggests that the conductivity of the rGO thin film is only partially limited by the disorder of the individual rGO flakes, with a significant proportion of the resistance originating from another source, i.e. flake to flake junctions. GO materials are tested as environmental membranes for the adsorption of the textile dye Rhodamine B (RhB) absorbing as high as 106.5 mg per gram of GO adsorbent. Initial results suggest a link between the interlayer distance of GO based materials and their ability to quickly adsorb the dye. It is shown that by using a partially oxidised GO material, it is possible to adsorb the dye quickly (approx. 60 - 100 mg of dye adsorbed per gram of GO in 60 minutes), while minimising the GO left in solution (below 10 ppm stable in solution after 52 hours) reducing the likelihood of causing contamination. Furthermore, rGO based porous sponges are synthesised and, using SEM and X-ray CT, shown to be porous throughout, reducing the likelihood of contamination further because of the hydrophobicity associated with rGO materials. Additionally, a hybrid rGO based material is synthesised, which contains iron nanoparticles of approximately 25 nm in diameter, encased in an iron oxide shell and impregnated in rGO sheets. This material (Fe-rGO) is shown to be magnetic, and is used in both OPV applications and for environmental adsorption. Finally, Fe-rGO porous sponges are produced, which could be revolutionary for use in environmental remediation. The magnetic properties allow for the adsorbing Fe-rGO to be removed from solution after adsorption, allowing 99% of the RhB dye to be recovered through elution in ethanol.
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Jönsson, Stina Karin Maria. "Towards flexible organic electronics : photoelectron spectroscopy of surfaces and interfaces /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek895s.pdf.
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Barrett, Richard. "Novel processing routes for neural interfaces." Thesis, University of Birmingham, 2014. http://etheses.bham.ac.uk//id/eprint/5137/.
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The thesis describes novel processing routes that have been developed to fabricate neural interfaces. A process has been investigated that uses microfabrication techniques to fabricate a multi-channel regenerative implant that can record nerve impulses in the peripheral nervous system (PNS), called the Spiral Peripheral Nerve Interface (SPNI). It is shown both theoretically and experimentally that the implant improves the ability to record signals in the PNS via micro-channels that act as axonal amplifiers. New processing routes are introduced to create robust interconnections from the SPNI to external electronics via ‘Microflex’ technology. To incorporate the new interconnection technology the SPNI had to be modified. During this modification the strain in the device was given specific consideration, for which a new bending model is presented. Modelling is used to show that electrochemical impedance spectroscopy can be used to assess the quality of the fabrication process. Electrochemical and mechanical tests show that the interconnection technology is suitable for a neural interfaces but the fabrication of perfectly sealed micro-channels was not evident. Thus, the SPNI was further improved by the introduction of a silicone sealing layer in the construction of the micro-channel array that was implemented using a novel adhesive bonding technique.
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Louis, Loai. "A study of delta-sigma modulators for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0029/MQ50639.pdf.
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Macedo, Marco. "Calibration and high speed techniques for CMOS analog-to- digital converters." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110482.
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The main focus of the work carried in this dissertation is to find the best design solution for an ultra high-speed Analog-to-Digital converter. Designing CMOS Analog-to-Digital converters in the gigahertz range for a good resolution is a challenge due to a lower power supply and smaller transistors. As a result, critical analog components (e.g., comparator, pre-amplifiers, band-gap) become more susceptible to process variation and make it hard to achieve a good resolution (e.g., higher than 6-bit). The traditional approach to design Analog-to-Digital converters does not work well with current CMOS technology and yields unpractical designs since it does not take advantage of the technology scaling down. For these reasons, this work investigates new designs topologies for the track-and-hold circuits needed at the front-end of ultra high-speed Analog-to- Digital converters and also investigates a digital foreground technique aimed at reducing the impact of process mismatch. For this purpose, two chips have been designed to investigate the best track-and-hold architecture based on a differential switch source-follower and to validate a proposed digital foreground calibration technique using resistive loads.L'objectif de cette dissertation est de trouver la meilleure méthode de conception pour les convertisseurs de type analogique à digital. La conception de convertisseurs de type analogique à digital en CMOS qui soient capables de fournir une résolution élevée est un défi de taille à des fréquences très élevées comme les gigahertz, car en CMOS les sources de voltages sont très petites et les dimensions des transistors rendent les composantes analogues (e.g., comparateur, amplicateur, et references de voltage) de plus en plus susceptibles aux variations physiques et chimiques qui se produisent durant la fabrication des puces microélectroniques.Les méthodes traditionnelles de conception pour les convertisseurs de type analogique à digital ne sont plus a la hauteur pour fournir des convertisseurs capables d'une bonne resolution, car elles ne prennent pas avantage des percés technologiques qui ont été réalisées avec la diminution de la taille physique des transistors en CMOS. Par conséquent, le travail de recherche éffectué dans cette thèse consiste à étudier des nouvelles structures de circuits pour faire la conception de track-and-hold qui est necessaire au bon fonctionnement de convertisseurs analogique à digital de très hautes fréquences. De plus, une méthode de calibration digitale qui a pour objectif de corriger les défectuosités engendrées par la fabrication des puces microélectroniques est aussi proposée afin d'ameliorer la performance et la résolution des convertisseurs analogique à digital. Finalement, deux puces microélectroniques ont été fabriquées a des fins expérimentales pour démontrer la performance d'un nouveau track-and-hold ainsi que valider une nouvelle technique de calibration digitale de type foreground qui utilise des résistances.
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Taherzadeh-Sani, Mohammad. "Reconfigurable pipelined analog-to-digital converters in low -voltage nanometer CMOS." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114247.
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The growing demand for multi-mode/multi-standard wireless terminals is fuelling interest in analog-to-digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions. Furthermore, for power-efficiency, these ADCs must be power-scalable (i.e., their power scales with their bandwidth and resolution), thereby maintaining a constant figure-of-merit (FOM) over their entire reconfigurability space. Such reconfigurable power-scalable ADCs must be implemented in a standard digital CMOS process, for higher integration of the analog and digital functions in a communication system and for lower fabrication costs. However, in nanometer CMOS technologies, the decreasing supply voltages and the shrinking devices with poor analog-signal-processing capabilities, complicate the design of low-power ADCs. This thesis proposes a pipelined ADC that is reconfigurable over a continuous range of sampling frequencies fs = 0.4 to 44 MS/s (bandwidths BW = 0.2 to 22 MHz), and over resolutions N = 10, 11, 12 bits. Fabricated in a 1.2-V 90-nm digital CMOS process, it achieves low power (FOM = 0.35 to 0.5 pJ/conversion step) over its full bandwidth-resolution space. Thus, this ADC is suitable for multiple wireless and cellular standards, ranging from GSM up to LTE/WiMax and 802.11g. Furthermore, owing to its power efficiency, this ADC is attractive for various applications over a wide bandwidth-resolution space, thereby saving on development costs and reducing the time-to-market. Compared to the state-of-the-art power-efficient (FOM < 2 pJ/conversion step) reconfigurable pipelined or Delta-Sigma ADCs, this ADC provides a wide bandwidth-resolution reconfigurability space, while achieving a highly-competitive FOM over this entire space. For power scalability, the ADC bandwidth and resolution are reconfigured using current-scaling and stage-bypass methods, respectively. The following techniques are also introduced to achieve low-power performance for the ADC over its wide reconfigurability space, and to enable its implementation in low-voltage nanometer CMOS: 1) low-power digital background gain calibration to enable designing the ADC using low-gain/low-power opamps; 2) pseudo-cascode compensation for the low-power design of low-voltage current-scalable opamps; and 3) design of switched-capacitor dynamic comparators with low input loading.La demande croissante de terminaux sans fil multimode et multistandard alimente l'intérêt pour des convertisseurs analogique-numérique (CAN) qui soient largement reconfigurables en terme de bande passante et de résolution. En outre, et pour des raisons d'efficacité énergétique, l'alimentation de ces CANs doit être modulable dans le but de maintenir une constante figure de mérite (FOM) dans tout l'espace de reconfigurabilité. Aussi, ces CANs doivent pouvoir être implémentés dans un technologie CMOS standard pour bénéficier d'un niveau d'intégration élevé de ses composants digitaux et analogiques ainsi qu'un plus faible cout de fabrication. Ceci dit, dans les technologies CMOS nanométriques, la diminution des tensions d'alimentation et la diminution de la taille des dispositifs sont des éléments contraignant la conception des CANs faible puissance. Cette thèse propose un CAN de type pipeline qui est reconfigurable sur une gamme continue de fréquences d'échantillonnage fs = 0.4 à 44 MS/s (bande passante de 0.2 à 22 MHz), pour les résolutions N = 10, 11, et 12 bits. Fabriqué dans une technologie digitale CMOS de 90-nm et 1.2-V, ce CAN est caractérisé par une faible consommation de puissance (FOM = 0.35 to 0.5 pJ/conversion step) sur tout son espace bande-resolution. Ainsi, ce CAN est approprié pour de multiples standards sans fil et cellulaire allant du GSM au LTE/iMax et 802.11g. Aussi, et en raison de son efficacité énergétique, ce CAN est attrayant pour diverses applications ce qui permet des économies de développements ainsi qu'une rapide mise sur le marché.Comparé à ce qui ce se fait aujourd'hui en terme d'efficacité énergétique (FOM < 2 pJ/conversion step), par exemple CAN de type pipeline ou Delta-Sigma, ce CAN offre un large espace de reconfiguration bande-resolution tout en réalisant un FOM hautement concurrentiel sur tout le dit espace. Pour varier la tension d'alimentation, la bande passante et la resolution du CAN sont reconfigurés en utilisant les méthodes dites de current-scaling et de stage-bypass respectivement. Les techniques suivantes sont également introduites pour obtenir des performances faible puissance dans l'espace de reconfigurabilite du CAN et permettre son implémentation dans une technologie CMOS nanométrique basse tension: 1) calibration digitale de gain type background pour permettre la conception du CAN à l'aide d'amplificateurs opérationnels faible gain et faible puissance; 2) compensation pseudo-cascode pour les amplificateurs opérationnels à courants variables; 3) la conception de comparateurs dynamiques type switch-cap à faible charge d'entrée.
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Nagarathnam, Premkumar. "Novel carbon nanotube thermal interfaces for microelectronics." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31720.
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Thesis (M. S.)--Mechanical Engineering, Georgia Institute of Technology, 2010.Committee Chair: Graham, Sam; Committee Member: Joshi, Yogendra; Committee Member: Kalaitzidou, Kyriaki. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Dida, Bashkim. "Automatiserad konstruktion av analoga förstärkare." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2944.
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The last few decades the development in the field of electronics has been huge. The components performance gets better at the same time as the manufacturing cost decreases. Many of the design moments that have to be done, are done automatically today, but it can get better. Especially for analog circuit design.
At Electronic System in Linköpings universitet, research is in progress to develop a tool that can design analog circuits in reasonable time. It means that it has to size the components (transistors, resistances, capacitances etc), so that the circuit can fulfill the performance requirements. An optimization method in conjunction with derived equations for the circuit performance is used to solve this task. The tool is created to design e.g. analog amplifiers. The goal is to decrease the design time and at the same time achieve better circuit performance.
This tool has been tested on three different circuits, a power-amplifier, a Nested Miller Compensated amplifier with an active feedback (Active Nested Miller Compensation) and a Nested Miller Compensated amplifier without an active feedback (Nested Miller Compensation). In this report the results from the designing tests are presented.
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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.
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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
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Hou, Xiaobo Rosen Warren A. Daryoush Afshin S. "A leaky waveguide all-optical analog-to-digital converter /." Philadelphia, Pa. : Drexel University, 2004. http://dspace.library.drexel.edu/handle/1860/437.
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Ying, Weidong Larry 1968. "Verification and re-design of communication interfaces with heterogeneous timing." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=34002.
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In this thesis we use a novel refinement-based technique to formally verify data transfer in an asynchronous timing framework. Novel data transfer models are proposed to represent the implicit relationship between clock and data validity events. We construct comprehensive implementation models for a previously published GALS architecture for on-chip systems [MVK+99]. Applying our techniques on this claimed to be hazard-free architecture, we find several hazards, and other dangers, together with additional delay constraints to avoid some of the detected dangers.We further exam re-design issues of an existing GALS system as compact design, internal structure optimization and reduced power consumption. Exhaustive verifications are applied to re-designed asynchronous wrapper circuits using our proposed refinement-based technique to ensure hazard-free operation.
We explore a strategy to resolve relative timing conflicts by implementing detected chain constraints as new circuit components to be integrated with the original design. This method is applied on two design cases to demonstrate its benefits and tradeoffs.
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Hollinger, Avrum. "Optical sensing, embedded systems, and musical interfaces for functional neuroimaging." Thesis, McGill University, 2014. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=123054.
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Behavioural neuroscience experiments are increasingly making use of functional magnetic resonance imaging (MRI) and require new physical interfaces augmented with sensors and electronic control systems to capture behaviour in synchrony with the MRI scanner, while presenting stimuli and feedback. These interfaces permit neuroscientists to correlate changes in neural activity with changes in behaviour, and thus form a better understanding of the human brain.Safety and MRI-compatibility are paramount, although repeated testing of new interfaces in the MRI scanner increases development costs. The inherent compatibility of fibre optic sensors ensures the safety and proper functioning of optoelectronic acquisition of behavioural measures within the MRI scanner, and will ensure their compatibility in newer, higher-field MRI scanners.I have designed and built novel optical sensors, optoelectronic acquisition and control systems, and augmented MRI-compatible musical interfaces for use in musical neuroimaging experiments. The fibre optic sensors were created for the measurement of proximity, position, displacement, flexion, force, vibration, and magnetic field. The embedded systems that have been developed enable optoelectronic signal acquisition, logging, communication, and real-time presentation (including mapping and synthesis) of auditory feedback, with the goal of a self-contained system to perform behavioural experiments. These MRI-compatible musical interfaces include: the Ballagumi, a novel flexible silicone instrument; an optoelectronic piano keyboard; and an optoacoustic cello. The piano and cello have been utilized in neuroimaging experiments, allowing, for the first time, the capture of musician gestures during actual performance on musical instruments within the MRI scanner. Presented herein is the iterative development and testing of these technologies. Additionally, the literature on MRI-compatible musical interfaces and related fields is reviewed, as well as future developments of these technologies and their applications in behavioural neuroscience, neuro-rehabilitation, and music performance.L'imagerie par résonance magnétique fonctionnelle (IRM) est de plus en plus utilisée pour des expériences de neuroscience comportementale. De telles expériences nécessitent la création de nouvelles interfaces augmentées de capteurs et de systèmes de contrôle électroniques pour capter les comportements, présenter des stimuli et produire des retours d'information de manière synchrone avec le scanner. Ainsi, il est possible pour les neuroscientifiques d'établir des corrélations entre les changements de comportement et les changements d'activité cérébrale; ceci leur permet donc de développer une meilleure compréhension du cerveau humain.Sécurité et compatibilité sont de plus haute importance, bien que des essais répétés de nouvelles interfaces dans le scanner IRM, afin de garantir qu'elle soit sécuritaire, augmente donc le prix de son développement. Les capteurs à fibre optique permettent d'atteindre ces objectifs avec les scanners actuels et les nouvelles générations de scanners qui produisent des champs magnétiques encore plus puissants.J'ai développé et construit de nouveaux capteurs optiques, des systèmes d'acquisition optoélectroniques, et des interfaces musicales compatibles avec les scanners IRM dans le cadre d'études d'imagerie cérébrale. Les capteurs à fibre optique que j'ai concus ont été créés pour mesurer la proximité, la position, le déplacement, la flexion, la force et le champs magnétique. Les systèmes embarqués développés durant cette thèse ont pour objectif de fournir des systèmes autonomes permettant de réaliser des expériences comportementales. à ce titre, ils permettent l'acquisition optoélectronique de signaux, leur communication, leur enregistrement et la production de stimuli auditif en temps-réel (incluant le mapping et la synthèse). Voici une liste des interfaces de contrôle musicales mises au point durant ce projet de doctorat: le Ballagumi, un nouvel instrument flexible fait en silicone; des claviers de piano optoélectroniques; et un violoncelle optoacoustique. Les pianos et le violoncelle ont été mis à contribution lors d'expériences ayant permis, pour la première fois, de capter les gestes d'un instrumentiste au sein d'un scanner. Dans ce qui suit, je présente le processus itératif de développement et de test ayant mené à ces nouvelles interfaces. De plus, l'état de l'art sur les interfaces musicales compatibles avec les scanners IRM est passé en revue, ainsi que les futures évolutions et applications de ces technologies aux domaines de la neuroscience comportementale, de la réhabilitation cérébrale et de la performance musicale.
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Dugger, Jeffery Don. "Adaptive Analog VLSI Signal Processing and Neural Networks." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5294.
Full textAbstract:
Research presented in this thesis provides
a substantial leap from the study of interesting
device physics to fully adaptive analog networks
and lays a solid foundation for future development
of large-scale, compact, low-power adaptive parallel
analog computation systems.
The investigation described here started with
observation of this potential learning capability
and led to the first derivation and characterization of
the floating-gate pFET correlation learning rule.
Starting with two synapses sharing the same error signal,
we progressed from phase correlation experiments
through correlation experiments involving harmonically related sinusoids,
culminating in learning the Fourier series coefficients
of a square wave cite{kn:Dugger2000}.
Extending these earlier two-input node experiments to the general case
of correlated inputs required dealing with
weight decay naturally exhibited by the learning rule.
We introduced a source-follower floating-gate synapse
as an improvement over our earlier source-degenerated floating-gate synapse
in terms of relative weight decay cite{kn:Dugger2004}.
A larger network of source-follower floating-gate synapses was fabricated
and an FPGA-controlled testboard was designed and built.
This more sophisticated system provides an excellent
framework for exploring applications to multi-input, multi-node
adaptive filtering applications.
Adaptive channel equalization provided
a practical test-case illustrating the use
of these adaptive systems in solving real-world problems.
The same system could easily be applied to noise and echo cancellation
in communication systems and system identification tasks in
optimal control problems.
We envision the commercialization of these adaptive analog VLSI
systems as practical products within a couple of years.
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Abcarius, John 1972. "High-speed low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=20898.
Full textAbstract:
As digital electronics becomes increasingly popular, the need for efficient data conversion to provide the link to our analog world grows all the more important. To sustain the current rate of technological advancement, the requirements on the data conversion systems are becoming more stringent. Wireless communication systems demand high speed, high performance analog-to-digital conversion front-ends. Furthermore, consumers demand quality electronics at low cost, which precludes the use of expensive analog processes.This thesis investigates the potential of DeltaSigma modulation techniques in addressing both of these issues through the design, implementation and experimentation of several prototype integrated circuits. Delta-Sigma modulation has recently become widely recognized for its ability to perform high performance data conversion without the use of high precision components. To extend these benefits to wireless applications, a novel eighth-order bandpass DeltaSigma modulator for A/D conversion will be presented. The modulator design is developed beginning at the signal processing level and realized in a 0.8mu BiCMOS process using the switched-capacitor (SC) technique. To address the cost issue, the design of a data conversion system based on the DeltaSigma modulation technique using an economical purely digital CMOS implementation is investigated. The distortion performance of experimental prototypes implemented using switched-capacitor (with capacitors realized using MOSFETs) and switched-current techniques is assessed.
This work therefore contributes to the ongoing drive to improve the performance and applicability of the DeltaSigma modulation technique in meeting modern-day data conversion needs.
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Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.
Full textAbstract:
This thesis presents the first fully integrated array of high-voltage (HV) digital-to-analog converters (DACs). It was designed in DALSA Semiconductor's 0.8mum CMOS/DMOS HV process technology. The 6-bit 300V DACs are based on a current-steering, thermometer coded architecture. Two designs adapted to the HV technology are proposed for the current-to-high-voltage conversion as traditional output resistor or op-amp solutions are not optimum for the HV process: one uses a high-compliance current mirror, while the other uses a simple current mirror. The DACs show a DNL of 0.16LSB and 1LSB, respectively, while the INL profile is 0.16LSB and 13LSBs for the first and second designs. The array is suited for applications requiring a set of digitally-controlled high-voltage signals.
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Smith, O'neil Lohanica. "Design and use of surface modifiers as tools for understanding and controlling interfaces in organic electronics." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51838.
Full textAbstract:
This thesis focuses on the use of surface modifiers as tools for probing and/or controlling interfaces. Surface modification of transparent conducting oxides (TCOs) with organic and organometallic modifiers can be used as a tool for mediating interfacial energetics as well as probing the kinetics of charge-transfer at the metal oxide/organic interface. The synthetic tunability of these modifiers allows us to design molecules based on various parameters, which include the nature of the binding, spacer, and terminal groups. Based on this framework, several modifiers were synthesized and used to investigate surface energy tuning as well as charge injection kinetics as a function of molecular structure. More specifically, we use XPS/UPS to examine the evolution of the chemical structure and frontier orbital levels of the TCO/organic interface as a function of the chosen surface modifier. In addition, we investigate the impact that various molecular binding groups have on mediating the kinetics of charge-transfer.
In the last section of this body of work we examine the development of dielectric nanocomposite films for capacitor applications. More specifically, we examine the use of phosphonic acid modifiers to functionalize barium titanate nanoparticles in order to provide miscibility with a suitable polymer host. The effect of various modifiers on the dielectric properties not nanocomposite thin films was examined.
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Dghais, Wael. "Behavioral modeling optimization and enhancement for high-speed analog mixed-signal I/O interfaces." Doctoral thesis, Universidade de Aveiro, 2013. http://hdl.handle.net/10773/12094.
Full textAbstract:
Doutoramento em Engenharia ElectrotécnicaA integridade do sinal em sistemas digitais interligados de alta velocidade, e avaliada através da simulação de modelos físicos (de nível de transístor) é custosa de ponto vista computacional (por exemplo, em tempo de execução de CPU e armazenamento de memória), e exige a disponibilização de detalhes físicos da estrutura interna do dispositivo. Esse cenário aumenta o interesse pela alternativa de modelação comportamental que descreve as características de operação do equipamento a partir da observação dos sinais eléctrico de entrada/saída (E/S). Os interfaces de E/S em chips de memória, que mais contribuem em carga computacional, desempenham funções complexas e incluem, por isso, um elevado número de pinos. Particularmente, os buffers de saída são obrigados a distorcer os sinais devido à sua dinâmica e não linearidade. Portanto, constituem o ponto crítico nos de circuitos integrados (CI) para a garantia da transmissão confiável em comunicações digitais de alta velocidade. Neste trabalho de doutoramento, os efeitos dinâmicos não-lineares anteriormente negligenciados do buffer de saída são estudados e modulados de forma eficiente para reduzir a complexidade da modelação do tipo caixa-negra paramétrica, melhorando assim o modelo standard IBIS. Isto é conseguido seguindo a abordagem semi-física que combina as características de formulação do modelo caixa-negra, a análise dos sinais eléctricos observados na E/S e propriedades na estrutura física do buffer em condições de operação práticas. Esta abordagem leva a um processo de construção do modelo comportamental fisicamente inspirado que supera os problemas das abordagens anteriores, optimizando os recursos utilizados em diferentes etapas de geração do modelo (ou seja, caracterização, formulação, extracção e implementação) para simular o comportamento dinâmico não-linear do buffer. Em consequência, contributo mais significativo desta tese é o desenvolvimento de um novo modelo comportamental analógico de duas portas adequado à simulação em overclocking que reveste de um particular interesse nas mais recentes usos de interfaces de E/S para memória de elevadas taxas de transmissão. A eficácia e a precisão dos modelos comportamentais desenvolvidos e implementados são qualitativa e quantitativamente avaliados comparando os resultados numéricos de extracção das suas funções e de simulação transitória com o correspondente modelo de referência do estado-da-arte, IBIS.
Signal integrity (SI) simulation of high-speed digital interconnected system via transistor level models is computational expensive (e.g. CPU time and memory storage), and requires the availability of physical details information of device’s internal structure. This scenario raises the interest for a behavioral modeling alternative which describes the device’s operation characteristics based on the observed input/output (I/O) electrical signal. I/O buffers that interface memory’s interconnects have major share in the computational load containing a very active complex functional part and high numbers of pins. Particularly, output buffers/drivers are forced to distort the I/O signals due to their nonlinear dynamics. In this concern, they constitute the integrated circuit (IC) bottleneck of ensuring reliable data transmission in the high-speed digital communication link. In this PhD work, the previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation, the analysis of the observed I/O electrical signals and the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. Moreover, the most important achievement is the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities.
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Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.
Full textAbstract:
This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.
The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.
In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.
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Fan, Yongquan. "Accelerating jitter and BER qualifications of high speed serial communication interfaces." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=86531.
Full textAbstract:
High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen, Bit Error Rate (BER) performance is of paramount importance in any communication interface. The bit errors in HSSIs are in large part due to jitter. This thesis investigates the topic of accelerating the jitter and BER testing and characterization [1].The thesis first proposes a new algorithm, suitable for extrapolating the receiver jitter tolerance performance from higher BER regions down to the 10-12 level or lower [2]. This algorithm enables us to perform the jitter tolerance characterization and production test more than 1000 times faster [3]. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms [4] while the test usually takes seconds. All the receiver and transmitter testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with speed up to 6 Gigabits per second (Gbps).
The thesis also presents an external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay lines. The scheme can be applied to test HSSIs with data rate up to 12.5 Gbps. It is also suitable for multi-lane HSSI testing with a lower cost than pure ATE solutions. By using high-speed relays, we combine the proposed ATE based approaches and the loopback approach along with an FPGA-based BER tester to provide a more versatile scheme for HSSI post-silicon validation, testing and debugging [5]. In addition, we further explore the unparallel advantages of our digital Gaussian noise generator in low BER evaluation [6].
Les interfaces sérielles à haute vitesse (interfaces HSSI) ont connu une utilisation accrue dans les télécommunications. Le taux d'erreur sur les bits (BER), mesure de la fréquence des erreurs, est d'une importance cruciale dans les interfaces modernes de télécommunication. Cette thèse traite de l'accélération de la caractérisation du vacillement et des tests BER.
Cette thèse propose tout d'abord un nouvel algorithme, approprié pour l'extrapolation de la performance de la tolérance au vacillement d'un récepteur pour un taux d'erreur sur les bits (BER) à un niveau de 10-12 ou moins. Cet algorithme permet de caractériser la tolérance au vacillement dans les tests de production plus de 1000 fois plus rapidement. Ensuite, une conception de transmetteur à sous-échantillonnage est présenté. Cette conception permet d'extraire précisément le vacillement du transmetteur et de compléter les tests de ce dernier en moins de 100 ms alors que ces tests durent normalement plusieurs secondes. Toutes les méthodes de test de récepteurs et de transmetteurs ont été utilisées avec succès sur un équipement d'éssai automatique (ATE) pour qualifier des millions d'interfaces HSSI à des vitesses allant jusqu'à 6 gigabits par seconde (6 Gbps).
Cette thèse présente aussi une conception de test en bouclage où une nouvelle méthode d'injection de vacillement est proposée en utilisant des lignes de délai de phase. Cette méthode peut être appliquée pour tester des interfaces HSSI avec un taux de transfer allant jusqu'à 12.5 Gbps. Elle permet aussi de tester des interface HSSI multi-lignes à un coût moindre qu'une solution utilisant un ATE. En utilisant des relais à haute vitesse, les approches sur ATE et par test en bouclage peuvent être combinées en incorporant un testeur de BER sur circuit intégré prédiffusé programmable (FPGA), ce qui permet une méthode de tests HSSI polyvalente pour la validation post-fabrication, les tests et le débogage. Finalement, nous explorons les avantages de notre générateur de bruit Gaussien dans l'évaluation de BER à bas niveau.