Relevant bibliographies by topics / Analog electronics and interfaces

Academic literature on the topic 'Analog electronics and interfaces'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Analog electronics and interfaces"

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Ohme, Bruce W., and Mark R. Larson. "Analog Component Development for 300°C Sensor Interface Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000199–206. http://dx.doi.org/10.4071/hitec-2012-wp11.

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The development of Enhanced Geothermal Systems (EGS) for base-load electrical power generation will require electronics for sensing and control during exploration and drilling and also during production. The operating temperature environments for these applications will generally be more extreme than those encountered by electronics currently deployed for oil and gas development and production monitoring. To address this requirement, electronic components have been designed and fabricated for operation at temperatures of 300°C. These integrated circuits use silicon-on-insulator (SOI) fabrication processes to achieve high temperature operation. High-fidelity simulation models have been developed by characterization of SOI devices at 300°C. These device models were employed to design components required for the development of a down-hole orientation module. A wide-bandwidth, low-noise operational amplifier has been developed for use with MEMS accelerometer sensors. A multi-channel synchronous voltage-to-frequency converter with built-in reference and oscillators has also been developed for use with 3-axis flux-gate magnetometers. The components themselves are general purpose and could easily be used for other high-temperature sensor-interface applications. .
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Kim, Bruce, Anurag Gupta, and Mitchell Spryn. "Wireless Sensor Platform for Nanosensor Interface Electronics." International Symposium on Microelectronics 2020, no. 1 (September 1, 2020): 000090–93. http://dx.doi.org/10.4071/2380-4505-2020.1.000090.

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Abstract In this paper, we describe a low-cost modular sensing system that can be used to interface with nanosensors. We used nanosensors to detect CO2 gas. In addition, the system can be easily modified to incorporate multiple analog and digital sensors, decreasing the amount of effort needed to integrate multiple sensors.
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Purcaru, Dorina, Cornelia Gordan, Romulus Reiz, and Anca Purcaru. "PC104 Interface Recommended for High Speed Data Acquisition Systems." Applied Mechanics and Materials 325-326 (June 2013): 926–29. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.926.

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The interface presented in this paper is recommended for high speed data acquisition systems; it performs a synchronized sampling of all common-mode or differential analog inputs with a high sampling rate. This is a low cost interface, entirely controlled by the PC104 CPU. Programmable electronic modules that contain such PC104 interfaces can be found running in the energetic system from Romania; these dedicated equipments perform the analog and digital signal acquisition for monitoring and recording different specific transient events. Some experimental results obtained using the disturbance monitoring device PC-08/104 are also presented in this paper.
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Zhang, Chi, Zhao Hui Ye, and Yong Ming Zhou. "Wireless CNC Motion Controller Designed with PSoC." Advanced Materials Research 898 (February 2014): 944–51. http://dx.doi.org/10.4028/www.scientific.net/amr.898.944.

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Numerical control (NC) technology is a kind of technology combined with electronics, machinery manufacturing, and other interdisciplinary combination of technologies. It is an important part of modern manufacturing. Currently, NC technology is developing towards the open CNC system with extensibility and interchangeability, while the modern electronic technology is developing towards the programmable technology and SoC (System-on-Chip) technology. However, current CNC controller designed with SoC is still in the research stage and not practical yet. In this paper, a practical CNC motion controller is built with modern PSoC (Programmable System-on-Chip) with wireless Ethernet interface. This controller has a high-performance microprocessor, numbers of free configurable analog and digital devices and IO (input/output) interfaces, and many kinds of communication interfaces. Therefore, it has good real-time control functions and communication functions. Experiments for controlling a three joint-axis engraving machine show that the controller can achieve high performance of parallel control of the three joint-axis linear interpolation and two joint-axis circular interpolation, and high performance of the trapezoidal and S-shape speed control. In addition, in order to reduce the impact to the motor and increase the system efficiency, a kind of look-ahead algorithm for velocity control with low time cost is used.
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Stoecklin, Sebastian, Elias Rosch, Adnan Yousaf, and Leonhard Reindl. "Very High Bit Rate Near-Field Communication with Low-Interference Coils and Digital Single-Bit Sampling Transceivers for Biomedical Sensor Systems." Sensors 20, no. 21 (October 23, 2020): 6025. http://dx.doi.org/10.3390/s20216025.

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The evolution of microelectronics increased the information acquired by today’s biomedical sensor systems to an extent where the capacity of low-power communication interfaces becomes one of the central bottlenecks. Hence, this paper mathematically analyzes and experimentally verifies novel coil and transceiver topologies for near-field communication interfaces, which simultaneously allow for high data transfer rates, low power consumption, and reduced interference to nearby wireless power transfer interfaces. Data coil design is focused on presenting two particular topologies which provide sufficient coupling between a reader and a wireless sensor system, but do not couple to an energy coil situated on the same substrate, severely reducing interference between wireless data and energy transfer interfaces. A novel transceiver design combines the approaches of a minimalistic analog front-end with a fully digital single-bit sampling demodulator, in which rectangular binary signals are processed by simple digital circuits instead of sinusoidal signals being conditioned by complex analog mixers and subsequent multi-bit analog-to-digital converters. The concepts are implemented using an analog interface in discrete circuit technology and a commercial low-power field-programmable gate array, yielding a transceiver which supports data rates of up to 6.78 MBit/s with an energy consumption of just 646 pJ/bit in transmitting mode and of 364 pJ/bit in receiving mode at a bit error rate of 2×10−7, being 10 times more energy efficient than any commercial NFC interface and fully implementable without any custom CMOS technology.
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SCHAMBACH, J., G. HOFFMANN, K. KAJIMOTO, L. BRIDGES, G. EPPLEY, J. LIU, B. LLOPE, T. NUSSBAUM, and C. MESA. "STAR TIME OF FLIGHT READOUT ELECTRONICS, DAQ, AND COSMIC RAY TEST STAND." International Journal of Modern Physics E 16, no. 07n08 (August 2007): 2496–502. http://dx.doi.org/10.1142/s021830130700815x.

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The new Time-of-Flight (TOF) subsystem for STAR at RHIC will have 3840 6-pad Multigap Resistive Plate Chambers (MRPC) distributed over 120 trays. Each tray contains 192 channels and three types of electronics cards: “TINO”, “TDIG” and “TCPU”. Every 30 trays send data to a “THUB” card that interfaces to STAR trigger and transmits data over fiber to a STAR DAQ fiber receiver. TINO contains analog front end electronics based on the CERN/LAA NINO custom IC. TDIG digitizes the data using the CERN HPTDC ASIC. TCPU formats and buffers the digital information. A cosmic ray test system comprised of three plastic scintillators, 4 MRPC modules, and TOF prototype electronics is used to determine the timing resolution to be achieved for the entire TOF system. Overall timing resolution of 80 – 110 ps has been achieved.
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Galkin, Y. D., O. V. Dvornikov, V. A. Tchekhovski, and N. N. Prokopenko. "Experimental studies and a double gate JFET model for analog integrated circuits." Doklady BGUIR 19, no. 7 (November 25, 2021): 5–12. http://dx.doi.org/10.35596/1729-7648-2021-19-7-5-12.

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One of directions of improving parameters of analog integrated circuits is a development of new and modernization of existing designs of integrated elements without significantly changing of a technological route of integrated circuit manufacturing with a simultaneous creation of new integrated elements models. The article considers the results of experimental studies of the double gate junction field-effect transistor manufactured according to the 3CBiT technological route of JSC Integral. Based on the obtained results, the electrical model of double gate junction field-effect transistor is proposed, which describes the features of its application in analog integrated circuits. Comparison of I-V characteristics of measurements results and created model simulation are presented. A small capacity and a reverse current of a double gate junction field-effect transistor top gate, an ability to compensate for the DC (direct current) component of an input current provide a significant improvement in the characteristics of analog integrated circuits such as electrometric operational amplifiers and charge-sensitive amplifiers. The developed double gate junction field-effect transistor can be used in signal readout devices required in the analog interfaces of space instrument sensors and nuclear electronics.
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Alexandrov, Peter, Xueqing Li, Matt O'Grady, and John Hostetler. "Analog and Logic High Temperature Integrated Circuits based on SiC JFETs." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000061–65. http://dx.doi.org/10.4071/hitec-tp12.

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Harsh environment applications such as electrical actuation on military and commercial aircraft, advanced engine controls, downhole energy exploration, propulsion systems of hybrid and all electric vehicles, and space exploration require sensor interfaces, control circuits, and power systems with electronics capable of operating at high temperatures. Wide band-gap materials such as SiC can be used to build devices with high operating temperatures due to their fundamental material properties. This paper presents initial results on developing basic analog and logic integrated circuits based on SiC JFET technology. Analog and logic integrated circuits were built using enhancement vertical channel lateral JFET transistors, metal film resistors and lateral p-n diodes. The analog circuits built include different types of operational amplifiers. The logic circuits include NOT, NAND, AND, NOR and OR gates. Transistors and integrated circuits were packaged in ceramic DIP packages and tested at temperatures up to 500 °C. The tested JFETs show proper operation up to the maximum tested temperature of 500 °C. The operational amplifiers remained functional at temperatures up to 430 °C. Basic logic circuits showed proper operation up to the maximum tested temperature of 500 °C.
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Massie, David R., and Stephen R. Delwiche. "Upgrading a High Performance Spectrophotometer." Journal of Near Infrared Spectroscopy 4, no. 1 (January 1996): 39–46. http://dx.doi.org/10.1255/jnirs.74.

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A spectrophotometer system was updated with a new computer and control circuitry to measure qualitative and quantitative characteristics of agricultural products between the ultraviolet and near infrared (NIR) regions of the electromagnetic spectrum. This single beam instrument, along with its computer, has a wavelength repeatability of 0.005 nm. This performance is required for proper system response compensation in a single beam system. Analog electronics are kept to a minimum by early conversion of the signal with a 10-μs 16-bit analog-to-digital (A/D) converter. A fast response real-time computer is required to service the A/D, wavelength drive and optical chopper. Herein, the development and selection of computer interfaces, data collection techniques and performance characteristics of this laboratory spectrophotometer system are described. The system is regularly used as the development tool in investigating new measurement techniques on agricultural products. It is also used to evaluate optical filters and other spectrophotometric systems.
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Dendouga, Abdelghani, Slimane Oussalah, Damien Thienpont, and Abdenour Lounis. "Multiobjective Genetic Algorithms Program for the Optimization of an OTA for Front-End Electronics." Advances in Electrical Engineering 2014 (August 13, 2014): 1–5. http://dx.doi.org/10.1155/2014/374741.

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The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) based circuit applications. Six performances are considered in this study, direct current (DC) gain, unity-gain bandwidth (GBW), phase margin (PM), power consumption (P), area (A), and slew rate (SR). We used the Matlab optimization toolbox to implement the program. Also, by using variables obtained from genetic algorithms, the operational transconductance amplifier (OTA) is simulated by using Cadence Virtuoso Spectre circuit simulator in standard TSMC (Taiwan Semiconductor Manufacturing Company) RF 0.18 μm CMOS technology. A good agreement is observed between the program optimization and electric simulation.
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Dissertations / Theses on the topic "Analog electronics and interfaces"

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Harikumar, Prakash. "Building Blocks for Low-Voltage Analog-to-Digital Interfaces." Licentiate thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111958.

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In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters. To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ while consuming 6.8 mW. Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain  frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR. Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist. Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.
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U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.

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Mosciatti, Thomas. "Nanostructured hybrid interfaces for supramolecular electronics." Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAF024/document.

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Cette thèse a exploré comment, en introduisant des interfaces nanostructurées dans des systèmes supramoléculaires pour l'électronique, il est possible de moduler, ajouter et étudier les propriétés des nano-objets. Sur ces applications de fonctionnalisation auto-assemblée des limites, le contrôle thermique sur les propriétés intrinsèques, la modulation lumineuse des structures chimiques et physiques ont été trouvés comme étant des techniques adaptées pour affecter le système supramoléculaire fonctionnalisé nano-structuré pour l'électronique organique. Des nanoparticules d'or ont été utilisées pour générer des interfaces qui ont été fonctionnalisés afin d'étudier l'effet de transport de charge dans un transistor à couche mince organique. Par conséquent, cette approche a été intensifiée en employant des molécules photochromiques et par le contrôle du piégeage de charge par irradiation de lumière. Le même principe a été utilisé pour moduler l'injection de charge dans les transistors à haute performances, par fonctionnalisation des électrodes appropriées avec des diaryléthènes. Enfin, une approche différente pour contrôler le dépôt de flocons de graphène sur surface diélectrique a été employée avec succès pour concevoir de nouveaux éléments de mémoire par ajustement de l'alignement des niveaux énergétiques du graphène après recuit thermique
This thesis explored how, by introducing nanostructured interfaces in supramolecular system for electronics, is possible to modulate, tune, add and study properties arising from nano-objects. On these purposes self-assembled functionalization of boundaries, thermal control on intrinsic properties, light modulation of chemical and physical structures have been found as tailored techniques to affect nano-structured functionalized supramolecular system for organic electronics. Gold nanoparticles have been used to generate interfaces that have been functionalized in order to study charge transport effect in organic thin film transistor. Therefore this approach has been stepped up employing photochromic molecules and controlling charge trapping with light irradiation. The same principle has been used to modulate charge injection in high performance transistors, by functionalizing electrodes with appropriate diarylethenes. Finally, a different approach of controlling deposition of graphene flakes on dielectric surface has been successfully employed to design new memory elements by tuning energetic level alignment of graphene with thermal annealing
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Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

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Wang, Haibo. "Field programmable analog array synthesis." Diss., The University of Arizona, 2002. http://hdl.handle.net/10150/289777.

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Field programmable analog arrays (FPAAs), the analog counterparts of digital field programmable gate arrays (FPGAs), are suitable for prototyping analog circuits and implementing dynamically re-configurable analog systems. Although various FPAA architectures have been recently developed, very little work has been reported in the area of design automation for field programmable analog arrays. The lack of sophisticated FPAA synthesis tools is becoming one of the key limitations toward fully exploiting the advantages of FPAAs. To address this problem, this dissertation presents a complete synthesis flow that can automatically translate abstract-level analog function descriptions into FPAA circuit implementations. The proposed synthesis flow consists of function decomposition, macro-cell synthesis, placement & routing, and post-placement simulation subroutines. The function decomposition subroutine is aimed at decomposing high-order analog functions into low-order sub-functions. This not only increases the accuracy of the realized analog functions, but also reduces the routing complexity of the synthesized circuits. The macro-cell synthesis subroutine generates circuit implementations for the decomposed sub-functions. Then, FPAA placement & routing is performed to map the synthesized analog circuits onto FPAA chips. The final stage of the synthesis flow is post-placement simulation, which is used to verify that the synthesized circuits meet performance specifications. The major contributions of this dissertation are techniques developed for implementing the FPAA synthesis flow. In the work of function decomposition, we developed theoretical proofs for two optimization criteria that were previously used to search optimal function decomposition solutions. In addition, we developed more efficient procedures to search optimal function decomposition solutions. To implement the macro-cell synthesis subroutine, we proposed a modified signal flow graph to represent FPAA circuits. Graph transformations are introduced for exploring alternative circuit structures in FPAA synthesis. Finally, in the work of FPAA placement and routing, an efficient method for estimating FPAA parasitic effects was developed. The effectiveness of the developed techniques is demonstrated by the experiments of synthesizing various FPAA circuits. The proposed synthesis methodologies will significantly simplify the use of FPAAs, and consequently make FPAAs more appealing in analog design.
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Chaumy, Guillaume. "Tunable metal-organic interfaces for spin electronics." Thesis, Strasbourg, 2019. http://www.theses.fr/2019STRAE030.

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L’objet de cette thèse est l’étude de l’interface entre les métaux et les matériaux organiques, avec pour objectif la réalisation de vannes de spin organiques. Pour ce faire, nous avons étudié des transistors organiques à effet de champ à grille électrolytique dans une structure planaire, et analysé leurs propriétés de transport et d’interface sous l’application de différents stimuli (température, dopage, champ magnétique…). Cette structure nous permet de nous rapprocher des conditions optimales pour l’injection et la détection de spin, mais elle nous a amenés à revoir la définition standard de la propriété intrinsèque des interfaces. Nous avons mis en évidence une résistance spécifique de contact particulièrement faible qui décroit avec la miniaturisation des dispositifs, ainsi que la magnétorésistance des résistances (spécifiques) d’interface
This thesis studies the interface between metals and organic materials, aiming the realization of organic spin-valves. To that end, we studied planar electrolyte-gated field-effect organic transistors and analysed their transport and interface properties under the application of different stimuli (temperature, doping, magnetic field…). This structure allowed us to approach the optimal conditions for spin injection and detection but led to redefine the standard intrinsic property of interfaces. We exhibited a very low specific contact resistance, that decreases with the downscaling of the devices, and the magnetoresistance of specific interface resistance
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Hematy, Arman. "Digitally programmable analog log-domain filters." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21302.

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Frequency filtering networks have numerous applications in consumer products. For high-speed and low-voltage systems, continuous-time filters are the preferred choice---these filters have become very popular with the wireless industry. Unfortunately, continuous-time filters have a high production cost since they are not geared toward mass production. This thesis proposes an analog filter structure that can be both mass produced and customized for a particular application. Such a structure is possible through the use of a state-space approach, and log-domain filtering.
First, a general state-space formulation is presented; a method of obtaining the state-space coefficients from an equivalent LC ladder network is described. Such a set of coefficients results in a realization with low noise and low sensitivity properties. Next, the effects of coefficient quantization on a state-space filter's response is examined. An optimization procedure is outlined to obtain the best approximation to the desired transfer function.
In order to implement the proposed filter structure, a universal log-domain cell is presented. Such a cell can be used to produce the stages required by any filter design (input, output, and integrator stages). Using the universal log-domain cell, a systematic approach to realizing any arbitrary-order filter is described. Next, the peripheral components needed to complete the filter are presented. Included are a novel 8-bit DAC, used to implement the programmable current sources that bias the filter, and V-to-I and I-to-V converters, used to interface the current-mode filter with voltage-mode instruments.
Finally, experimental results from several prototype boards are used to verify the feasibility of the proposed filter structure. These boards make use of ICs fabricated in a 0.8 mum BiCMOS technology; included are an IC with stand-alone programmable current sources, an IC with a third-order filter, as well as one with a fifth-order filter. The results from the test boards clearly demonstrate the programmability and functionality of digitally programmable state-space filters.
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Hawrysh, Evan M. (Evan Mark). "Digital architectures for analog signal generation." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24058.

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Analog and mixed-signal testing is far more complex than its digital equivalent. This thesis will identify the analog test requirements through an extensive analysis of integrated circuit testing, possible error sources, and the different levels of test hierarchy. The results will show that analog testing requires spectrally pure, high-quality predictable test signals. These signals are most robust when reproduced through digital techniques such as direct digital frequency synthesis. Delta-sigma ($ Delta Sigma$) modulation is perhaps the most versatile technique, as it can precisely encode arbitrary analog waveforms into a pulse-density modulated (PDM), infinite-length, single bit-wide pattern. The noise-shaping characteristics of the $ Delta Sigma$ modulator also allow for simple reconstruction of the embedded signal. Unfortunately, on-chip signal generation using this method is currently hindered by the high area overhead and limited programmability of $ Delta Sigma$ modulation oscillators. We will introduce the concept of forcing the PDM pattern to be finite in length and thus periodic. Although other periodic encoding algorithms exist, forced-periodic PDM patterns will be shown to be far superior for their precise control over signal amplitude, frequency, phase, and also for their ability to encode an arbitrary waveform. Its effectiveness will be demonstrated with several experiments of single- and multi-tone waveforms of varying degrees of complexity. By creating a fixed-length pattern, we can take advantage of many common digital built-in self-test (BIST) concepts such as scan and RAMBIST, found on most digital and mixed-signal integrated circuits, to supply the necessary hardware. We will show how analog signal generation can be integrated into digital ICs using any or all of the IEEE 1149.1-1990 standard, embedded RAMs, and scan chains. These applications will indeed prove that with very little additional hardware, on-chip, high-quality analog signal gene
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Harikumar, Prakash. "Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces." Doctoral thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-122730.

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential. The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2. The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2. The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.
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Shen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.

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This thesis studies the floating-point analog-to-digital converter (FP-ADC). The first attempt is to analyze the parallel architecture of the floating-point converter, which is our research base. The characteristics and specifications of the floating-point AID converter are described. Simulations of the parallel architecture of the floating-point A/D converter were conceived, run and presented here to support the theoretically derived FP-ADC transfer characteristics. After analyzing the parallel architecture of the floating-point A/D converter, the following work is to provide a way of minimizing the conversion time as well as keeping the precision of the floating point A/D converter (FP-ADC) by implementing the parallel architecture with Field Programmable Gate Arrays (FPGA). The thesis presents the design and practical implementation of the parallel FP-ADC, based on a FPGA and other hybrid components-of-the-shelf. The correctness of the design was verified by computer simulation, while the functionality of the implemented FP-ADC was tested on a test bench controlled by a PC. (Abstract shortened by UMI.)
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Books on the topic "Analog electronics and interfaces"

1

Roermund, Arthur van. Analog Circuit Design:: Sensor and Actuator Interface Electronics, Integrated High-Voltage Electronics and Power Management, Low-Power and High-Resolution ADC's. U.S.: Springer, 2005.

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Arthur H. M. van Roermund. Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012. New York, NY: Springer New York, 2013.

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Plassche, Rudy J. van de., Huijsing Johan H. 1938-, Sansen Willy M. C, and Workshop of Advances in Analogue Circuit Design (6th : 1997 : Como, Italy), eds. Analog circuit design: RF analog-to-digital converters, sensor and actuator interfaces : low-noise oscillators, PLLs and synthesizers. Boston: Kluwer Academic Publishers, 1997.

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1938-, Huijsing Johan H., Steyaert Michiel 1959-, and Roermund, Arthur H. M. van., eds. Analog circuit design: Sensor and actuator interface electronics, integrated high-voltage electronics and power management, low-power and high-resolution ADC's. Boston: Kluwer Academic, 2004.

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Plassche, Rudy J. Analog Circuit Design: RF Analog-to-Digital Converters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs and Synthesizers. Boston, MA: Springer US, 1997.

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Analog electronics. Oxford: Heinemann Newnes, 1990.

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Hickman, Ian. Analog electronics. Boca Raton, Fla: CRC Press, 1990.

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Hickman, Ian. Analog electronics. Oxford: Newnes, 1993.

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Hickman, Ian. Analog electronics. 2nd ed. Oxford: Newnes, 1999.

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Goodge, Malcolm. Analog Electronics. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1.

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Book chapters on the topic "Analog electronics and interfaces"

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Schnell, Gerhard, and Konrad Hoyer. "Digital/Analog- und Analog/Digitalwandler." In Interfaces und Datennetze, 78–96. Wiesbaden: Vieweg+Teubner Verlag, 1989. http://dx.doi.org/10.1007/978-3-322-90494-2_6.

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Goodge, Malcolm. "Introductory Topics." In Analog Electronics, 1–19. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_1.

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Goodge, Malcolm. "Pulse Circuits." In Analog Electronics, 310–33. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_10.

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Goodge, Malcolm. "Power Supplies." In Analog Electronics, 334–403. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_11.

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Goodge, Malcolm. "Electronic Devices and Components." In Analog Electronics, 20–52. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_2.

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Goodge, Malcolm. "Small-signal Amplifiers: Basics." In Analog Electronics, 53–109. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_3.

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Goodge, Malcolm. "Frequency Response." In Analog Electronics, 110–34. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_4.

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Goodge, Malcolm. "Feedback." In Analog Electronics, 135–53. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_5.

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Goodge, Malcolm. "Small-signal Amplifiers: Advanced Topics." In Analog Electronics, 154–83. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_6.

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Goodge, Malcolm. "Operational Amplifiers." In Analog Electronics, 184–240. London: Palgrave Macmillan UK, 1990. http://dx.doi.org/10.1007/978-1-349-20994-1_7.

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Conference papers on the topic "Analog electronics and interfaces"

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Doliwa, Sebastian, Andreas Erbsloh, Karsten Seidl, and Ioannis Iossifidis. "Development of an Analog Front-End for Brain-Computer Interfaces." In 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). IEEE, 2022. http://dx.doi.org/10.1109/prime55000.2022.9816757.

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Aguirre, J., N. Medrano, B. Calvo, S. Celma, and C. Azcona. "An analog lock-in amplifier for embedded sensor electronic interfaces." In 2011 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2011. http://dx.doi.org/10.1109/ecctd.2011.6043377.

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Saramov, Emil, and Margarita Georgieva. "Nonuniform Synchronous Sampling Analog Interface." In 2006 29th International Spring Seminar on Electronics Technology. IEEE, 2006. http://dx.doi.org/10.1109/isse.2006.365124.

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Dey, Samrat, Thomas K. Lewellen, Robert S. Miyaoka, and Jacques C. Rudell. "Impact of analog IC impairments in SiPM interface electronics." In 2012 IEEE Nuclear Science Symposium and Medical Imaging Conference (2012 NSS/MIC). IEEE, 2012. http://dx.doi.org/10.1109/nssmic.2012.6551818.

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Titov, A. E., N. N. Prokopenko, and N. V. Butyrlagin. "The instrumentation amplifier with double-channel low pass filter for analog interfaces sensors." In 2016 13th International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE). IEEE, 2016. http://dx.doi.org/10.1109/apeie.2016.7807025.

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Sobanski, Kurt, Ken Martin, Fong Shi, and Brad Greenway. "Gas Turbine Distributed Control Systems: Power Supply and Communication Data Bus Design Considerations." In ASME 1998 International Gas Turbine and Aeroengine Congress and Exhibition. American Society of Mechanical Engineers, 1998. http://dx.doi.org/10.1115/98-gt-414.

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Over the past several decades, gas turbine control systems have evolved from hydro-mechanical systems to full authority redundant electronic systems. One advanced technology with potential to revolutionize the way engine system designers build new products is high temperature distributed controls. Distributed control systems put electronics close to control functions and reduce the number of interconnects between central processors and sensors or effectors. In distributed systems, power and data buses take the place of multiple discrete analog wire bundles found in centralized control systems. Distributed modules interconnected with power and data buses control effectors such as hydraulic actuators or solenoid valves and read sensors to measure pressures, temperatures and speeds. With distributed controls, many gas turbine applications will require high temperature electronics ruggedized to survive the demanding environment. For these new systems, manufacturers must determine how to maximize the use of standard interfaces and electronic components and minimize the use of custom parts. Two particular areas would benefit the aerospace industry include distributed system power supplies and communication data buses since these designs play an important role in system cost, weight, size and reliability. Interface standardization will benefit engine manufacturers by lowering system cost and enabling inter-changeability of distributed engine control components from different suppliers. Careful attention to architectural design details for the power supplies and data buses can lead to systems that meet the needs of end users.
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Walbrou. "An analog to digital interface for digital video signal processing." In 1998 International Conference on Consumer Electronics. IEEE, 1989. http://dx.doi.org/10.1109/icce.1989.69136.

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Ghasemi, Shahrzad, and Soliman A. Mahmoud. "Analog Front-End CMOS Temperature Sensor Interface for Optogenetic Devices." In 2022 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS). IEEE, 2022. http://dx.doi.org/10.1109/iemtronics55184.2022.9795841.

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Tutwiler, R. L., J. P. Stitt, K. K. Shung, Q. Wu, T. A. Ritter, X. Yang, and J. Sabarad. "Control Architecture for 30MHz Linear Imaging Array." In ASME 2003 Pressure Vessels and Piping Conference. ASMEDC, 2003. http://dx.doi.org/10.1115/pvp2003-1864.

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The purpose of this system is to have the capability to characterize the performance of very high frequency transducers and arrays. The analog front end is computer controlled by a set of de-multiplexers and multiplexers. The output of the multiplexer network is connected to a TGC array, which is interfaced to a high-speed data acquisition system. A software GUI (Graphical User Interface) has been designed to accomplish this task [1]. A programmable digital I/O interface allows collection of RF channel data and has the capability to be interfaced to a very high frequency analog beam-former under construction. The system front-end electronics (pulsers, receivers, T/R switches, multiplexers, and demultiplexers) have been characterized [2, 3]. The digital I/O signal interface has been integrated and tested. The hardware front end has been integrated to the array interface distribution panel. The individual transducer elements impulse responses have been evaluated and the performance of the array has been tested with a wire test phantom to characterize lateral and axial resolution.
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Barile, Gianluca, Giuseppe Ferri, Francesca Romana Parente, Vincenzo Stornelli, Alessandro Depari, Alessandra Flammini, and Emiliano Sisinni. "A standard CMOS bridge-based analog interface for differential capacitive sensors." In 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2017. http://dx.doi.org/10.1109/prime.2017.7974162.

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Reports on the topic "Analog electronics and interfaces"

1

Nouidui, Thierry Stephane, Michael Wetter, Zhengwei Li, Xiufeng Pang, Prajesh Bhattacharya, and Philip Haves. BacNet and Analog/Digital Interfaces of the Building Controls Virtual Testbed. Office of Scientific and Technical Information (OSTI), November 2011. http://dx.doi.org/10.2172/1168733.

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Treanton, B., J. Palomo, B. Kroposki, and H. Thomas. Advanced Power Electronics Interfaces for Distributed Energy Workshop Summary: August 24, 2006, Sacramento, California. Office of Scientific and Technical Information (OSTI), October 2006. http://dx.doi.org/10.2172/894428.

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Warburton, Paul. High-Mobility Two-Dimensional Electron Gases at ZnO/ZnMgO Interfaces for Ultra-Fast Electronics Applications. Fort Belvoir, VA: Defense Technical Information Center, November 2014. http://dx.doi.org/10.21236/ada626925.

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Philpott, Rick A. Development of High Performance Electronics and Optical-to-Electrical Advanced Circuitry for Photonic Analog-to-Digital Converters. Fort Belvoir, VA: Defense Technical Information Center, February 2006. http://dx.doi.org/10.21236/ada444702.

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Boring, Ronald, Thomas Ulrich, Roger Lew, Casey Kovesdi, Brandon Rice, Christopher Poresky, Zach Spielman, and Kateryna Savchenko. Analog, Digital, or Enhanced Human-System Interfaces? Results of an Operator-in-the-Loop Study on Main Control Room Modernization for a Nuclear Power Plant. Office of Scientific and Technical Information (OSTI), September 2017. http://dx.doi.org/10.2172/1472062.

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