Journal articles: 'Analog and mixed-signal integrated circuits'

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Deeb, Ali, Abdalrahman Ibrahim, Mohamed Salem, Joachim Pichler, Sergii Tkachov, Anjeza Karaj, Fadi Al Machot, and Kyamakya Kyandoghere. "A Robust Automated Analog Circuits Classification Involving a Graph Neural Network and a Novel Data Augmentation Strategy." Sensors 23, no. 6 (March 9, 2023): 2989. http://dx.doi.org/10.3390/s23062989.

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Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified/classified. However, there currently needs to be a reliable industrial tool that can automatically identify/classify analog sub-circuits (eventually in the frame of a circuit design process) or automatically classify a given analog circuit at hand. Besides verification, several other processes would profit enormously from the availability of a robust and reliable automated classification model for analog circuit modules (which may belong to different levels). This paper presents how to use a Graph Convolutional Network (GCN) model and proposes a novel data augmentation strategy to automatically classify analog circuits of a given level. Eventually, it can be upscaled or integrated within a more complex functional module (for a structure recognition of complex analog circuits), targeting the identification of subcircuits within a more complex analog circuit module. An integrated novel data augmentation technique is particularly crucial due to the harsh reality of the availability of generally only a relatively limited dataset of analog circuits’ schematics (i.e., sample architectures) in practical settings. Through a comprehensive ontology, we first introduce a graph representation framework of the circuits’ schematics, which consists of converting the circuit’s related netlists into graphs. Then, we use a robust classifier consisting of a GCN processor to determine the label corresponding to the given input analog circuit’s schematics. Furthermore, the classification performance is improved and robust by involving a novel data augmentation technique. The classification accuracy was enhanced from 48.2% to 76.6% using feature matrix augmentation, and from 72% to 92% using Dataset Augmentation by Flipping. A 100% accuracy was achieved after applying either multi-Stage augmentation or Hyperphysical Augmentation. Overall, extensive tests of the concept were developed to demonstrate high accuracy for the analog circuit’s classification endeavor. This is solid support for a future up-scaling towards an automated analog circuits’ structure detection, which is one of the prerequisites not only for the stimuli generation in the frame of analog mixed-signal verification but also for other critical endeavors related to the engineering of AMS circuits.

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Gielen, G. G. E., and R. A. Rutenbar. "Computer-aided design of analog and mixed-signal integrated circuits." Proceedings of the IEEE 88, no. 12 (December 2000): 1825–54. http://dx.doi.org/10.1109/5.899053.

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Turflinger, T. L. "Single-event effects in analog and mixed-signal integrated circuits." IEEE Transactions on Nuclear Science 43, no. 2 (April 1996): 594–602. http://dx.doi.org/10.1109/23.490903.

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HOLMAN, W. T. "RADIATION-TOLERANT DESIGN FOR HIGH PERFORMANCE MIXED-SIGNAL CIRCUITS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 353–66. http://dx.doi.org/10.1142/s0129156404002405.

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Modern semiconductor processes can provide significant intrinsic hardness against radiation effects in digital and analog circuits. Current design techniques using commercial processes for radiation-tolerant integrated circuits are summarized, with an emphasis on their application in high performance mixed-signal circuits and systems. Examples of "radiation hardened by design" (RHBD) methodologies are illustrated for reducing the vulnerability of circuits and components to total dose, single-event, and dose-rate effects.

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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

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Hurst, S. L. "Analog signal generation for built-in self-test of mixed-signal integrated circuits." Microelectronics Journal 27, no. 1 (February 1996): 103–4. http://dx.doi.org/10.1016/s0026-2692(96)90016-6.

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Arabi, K., and B. Kaminska. "Testing analog and mixed-signal integrated circuits using oscillation-test method." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 7 (July 1997): 745–53. http://dx.doi.org/10.1109/43.644035.

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Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.

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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

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Esch, J. "Prolog to computer-aided design of analog and mixed-signal integrated circuits." Proceedings of the IEEE 88, no. 12 (December 2000): 1823–24. http://dx.doi.org/10.1109/jproc.2000.899052.

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Vera Casañas, César William, Thainann Henrique Pereira de Castro, Gabriel Antonio Fanelli de Souza, Robson Luiz Moreno, and Dalton Martini Colombo. "Review of CMOS Currente References." Journal of Integrated Circuits and Systems 17, no. 1 (April 30, 2022): 1–9. http://dx.doi.org/10.29292/jics.v17i1.592.

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A current reference is able to provide a precise and accurate current for other circuits inside a chip. This type of electronic circuit is employed as a building block in numerous analog and mixed-signal circuits. Moreover, it is a fundamental component of current-mode circuits. This work discusses the basic and essential concepts of designing CMOS integrated current references. A review of conventional topologies is presented, including current mirrors and current references. Temperature dependence is discussed, along with PTAT and CTAT topologies, and some low-power/low-voltage implementations are also presented.

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (June 30, 2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more designing than digital circuit design and Kobayashi and Kuwana firmly believe that 'beautiful' mathematics can facilitate truly great circuit design. Additional mathematics techniques employed by Kobayashi and the team are statistics, coding theory, modulation and signal processing algorithms and pairing pure mathematics theorems with electrical engineering is a key feature of the researchers' work. The team utilises theoretical analysis and simulations such as the circuit simulator (SPICE) and system simulator (MATLAB) to test its work and collaborates with semiconductor companies and electronic measurement instrument companies in Japan for smart circuit design and effective circuit testing. So far, results include that using SAR ADC configurations with Fibonacci sequence weights can improve the speeds and reliability of the SAR ADC. Also several new DAC architecutures and waveform sampling methods are derived based on mathematics.

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Sedra, A. S. "Analog MOS integrated circuits for signal processing." Proceedings of the IEEE 75, no. 11 (November 1987): 1550. http://dx.doi.org/10.1109/proc.1987.13922.

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Kim, Bruce, Sukeshwar Kannan, Anurag Gupta, and Naga Sai Evana. "Modeling and Simulation of 3D MEMS Integrated RF Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 002006–27. http://dx.doi.org/10.4071/2012dpc-wp35.

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Today's integrated packaging consists of analog, mixed-signal and RF circuits. These integrated packages are now available in 3-D which makes it extremely difficult to test for defects and their circuit functionalities. This paper provides 3D MEMS integrated packaging which provides self testing and calibrations to overcome process defects and out of spec circuits inside the package making the package self heal itself in case of faults and defects. We have worked on TSV based 3D packaging with MEMS switches to perform self calibrations. We developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated on an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. We used arrays of MEMS switches to perform self testing. We have considered a low noise amplifier as the reference RF circuit which operates between 4 GHz and 6 GHz. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. The paper presents defects in TSV due to mechanical stress and thermal changes.

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Barylo, Gryhoriy, Oksana Boyko, Ihor Helzhynskyy, Tetyana Marusenkova, Yurii Kryvenchuk, and Roman Holyaka. "HARDWARE-SOFTWARE EMBEDDED SYSTEM OF SIGNAL FREQUENCY SELECTION ON GYRATOR." Measuring Equipment and Metrology 82, no. 1 (2021): 37–42. http://dx.doi.org/10.23939/istcmtm2021.01.037.

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The work is devoted to the problem of frequency-selective signal conversion in microelectronic sensor devices. It has been shown that the signal path of such devices, in particular, sensor nodes in the concept of the Internet of Things, must meet the requirements of embedded systems using a mixed analog-digital front end. The analysis of the signal transformation of photovoltaic sensors, in particular the problem of a significant parasitic influence of extraneous non-informative optical radiation and electromagnetic interference, has been carried out. SPICE models of photovoltaic sensor signal circuits providing frequency selection on bandwidth filters have been synthesized. The main approaches of hardware-software implementation of the built-in system of frequency selection with the mixed-signal transformation are considered. The signal path of the embedded system includes a gyrator, a software-controlled amplifier, a synchronous demodulator, an analog-to-digital converter, and a digital filter. The implementation is carried out on the platform of the programmable system on a PSoC chip. The integrated circuits of the PSoC 5 LP Family Cypress Semiconductor Corporation are used with a wide range of programmable analog front-end nodes, in particular operating amplifiers, comparators, units on switching capacitors, reference voltage sources on the principle of the forbidden zone, analog multiplexers, signal synthesizers, etc. The efficiency of the mixed analog and digital signal conversion is shown.

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Luo, Pei-Wen, Jwu-E. Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, and Wen-Ching Wu. "Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 11 (November 2008): 2097–101. http://dx.doi.org/10.1109/tcad.2008.2006139.

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Rathinam, A., R. Srinivasa Raghavan, and R. Venkatraman. "Implementation of Simualtions of Analog, Digital & Mixed Signal Integrated Circuits Using Pspice." International Journal of Computer Applications 1, no. 27 (February 25, 2010): 71–77. http://dx.doi.org/10.5120/498-812.

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HU, G., H. WANG, and S. YANG. "Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits." IEICE Transactions on Information and Systems E91-D, no. 8 (August 1, 2008): 2134–40. http://dx.doi.org/10.1093/ietisy/e91-d.8.2134.

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Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

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Lee, Nai-Chi. "A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards." Journal of Electronic Testing 4, no. 4 (November 1993): 361–68. http://dx.doi.org/10.1007/bf00972160.

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Lee, Nai-Chi. "A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards." Analog Integrated Circuits and Signal Processing 4, no. 3 (November 1993): 261–68. http://dx.doi.org/10.1007/bf01239078.

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Li, Zihan. "Application of Integrated Circuits in Cardiac Pacemakers." Highlights in Science, Engineering and Technology 62 (July 27, 2023): 84–89. http://dx.doi.org/10.54097/hset.v62i.10428.

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This article briefly describes the application of integrated circuits in the medical field, such as wearable and implantable medical devices. The article introduces the development process of integrated circuits used in cardiac pacemakers, explaining how it evolved from bipolar junction transistors integrated circuits in the past to today's complementary metal oxide semiconductor integrated circuits. The basic components of the pacemaker are described from a system level, including the signal amplifier, pulse generator, battery management system, and analog-to-digital converter. This allows for a clear presentation of the working process of the pacemaker. Furthermore, the article explains how analog integrated circuits and digital integrated circuits can be used together to achieve the goal of low power consumption of cardiac pacemakers at a circuit level, with reference to some cutting-edge scientific and technological achievements. The necessity and advantages of integrated circuits in medical applications are demonstrated, and the future development of integrated circuits in related aspects is forecasted based on the current development situation.

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Maralani, A., Michael S. Mazzola, David C. Sheridan, Igor Sankin, and Volodymyr Bondarenko. "Characterization and Modeling of SiC LTJFET for Analog Integrated Circuit Simulation and Design." Materials Science Forum 615-617 (March 2009): 915–18. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.915.

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The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

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Gustard, N. C., and R. E. Massara. "On the optimal design of switched-capacitor filter circuits for analog and mixed-signal integrated circuit realization." Analog Integrated Circuits and Signal Processing 6, no. 3 (November 1994): 219–29. http://dx.doi.org/10.1007/bf01238890.

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Leyn, F., G. G. E. Gielen, and W. Sansen. "Analog small-signal modeling-part I: behavioral signal path modeling for analog integrated circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 7 (July 2001): 701–11. http://dx.doi.org/10.1109/82.958340.

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Zhang, Chaojie, Guo He, Jiankeng Yu, and Xionglong Pan. "Fault features analysis for soft faults of analog circuits with tolerance." MATEC Web of Conferences 232 (2018): 04017. http://dx.doi.org/10.1051/matecconf/201823204017.

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Soft faults of analog circuits are more difficult to diagnose than hard faults because the soft faults are caused by the deviations of component parameters. Node voltages were traditionally used as the testing signals to diagnose analog circuits. With the rapid development of integrated circuits technology, fewer and fewer circuit nodes are accessible. Only the output voltage can be tested in many cases. This cries for other new accessible signal except for the traditional voltage signal. In this paper, the fault features of testing signal in both time-domain and frequency-domain are analysed. The output voltage was acquired firstly. Its fault features were extracted and used for fault diagnosis. The results show that the soft faults of Tow-Thomas filter cannot be uniquely located by using this output voltage only. Then a new accessible signal, which named dynamic power supply current, was acquired and its fault features were analysed. And the results were compared with those using output voltages. The comparing results show the validity of dynamic power supply current. This signal contains information related with the circuits’ topology and can be used for fault diagnosis of analog circuits.

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Anisimov, Aleksei A., Alexander V. Belov, Timofei V. Sergeev, Elizaveta E. Sannikova, and Oleg A. Markelov. "Evolution of Bioamplifiers: From Vacuum Tubes to Highly Integrated Analog Front-Ends." Electronics 11, no. 15 (August 1, 2022): 2402. http://dx.doi.org/10.3390/electronics11152402.

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The past century has seen the ongoing development of amplifiers for different electrophysiological signals to study the work of the heart. Since the vacuum tube era, engineers and designers of bioamplifiers for recording electrophysiological signals have been trying to achieve similar objectives: increasing the input impedance and common-mode rejection ratio, as well as reducing power consumption and the size of the bioamplifier. This review traces the evolution of bioamplifiers, starting from circuits on vacuum tubes and discrete transistors through circuits on operational and instrumental amplifiers, and to combined analog-digital solutions on analog front-end integrated circuits. Examples of circuits and their technical features are provided for each stage of the bioamplifier development. Special emphasis is placed on the review of modern analog front-end solutions for biopotential registration, including their generalized structural diagram and table of comparative characteristics. A detailed review of analog front-end circuit integration in various practical applications is provided, with examples of the latest achievements in the field of electrocardiogram, electroencephalogram, and electromyogram registration. The review concludes with key points and insights for the future development of the analog front-end concept applied to bioelectric signal registration.

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Yu, Zhuizhuan, Xi Chen, Sebastian Hoyos, Brian M. Sadler, Jingxuan Gong, and Chengliang Qian. "Mixed-Signal Parallel Compressive Spectrum Sensing for Cognitive Radios." International Journal of Digital Multimedia Broadcasting 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/730509.

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Wideband spectrum sensing for cognitive radios requires very demanding analog-to-digital conversion (ADC) speed and dynamic range. In this paper, a mixed-signal parallel compressive sensing architecture is developed to realize wideband spectrum sensing for cognitive radios at sub-Nqyuist rates by exploiting the sparsity in current frequency usage. Overlapping windowed integrators are used for analog basis expansion, that provides flexible filter nulls for clock leakage spur rejection. A low-speed experimental system, built with off-the-shelf components, is presented. The impact of circuit nonidealities is considered in detail, providing insight for a future integrated circuit implementation.

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Spira, Steffen, Kurt Blau, Reiner Thomä, and Matthias A. Hein. "Agile multi-beam front-end for 5G mm-wave measurements." International Journal of Microwave and Wireless Technologies 13, no. 7 (June 8, 2021): 740–50. http://dx.doi.org/10.1017/s1759078721000842.

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AbstractThe 5th generation new radio (5G NR) standards create both enormous challenges and potential to address the spatio-spectral-temporal agility of wireless transmission. In the framework of a research unit at TU Ilmenau, various concepts were studied, including both approaches toward integrated circuits and distributed receiver front-ends (FEs). We report here on the latter approach, aiming at the proof-of-principle of the constituting FEs suitable for later modular extension. A millimeter-wave agile multi-beam FE with an integrated 4 by 1 antenna array for 5G wireless communications was designed, manufactured, and verified by measurements. The polarization is continuously electronically adjustable and the directions of signal reception are steerable by setting digital phase shifters. On purpose, these functions were realized by analog circuits, and digital signal processing was not applied. The agile polarization is created inside the analog, real-time capable FE in a novel manner and any external circuitry is omitted. The microstrip patch antenna array integrated into this module necessitated elaborate measurements within the scope of FE characterization, as the analog circuit and antenna form a single entity and cannot be assessed separately. Link measurements with broadband signals were successfully performed and analyzed in detail to determine the error vector magnitude contributions of the FE.

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Galkin, Y. D., O. V. Dvornikov, V. A. Tchekhovski, and N. N. Prokopenko. "Experimental studies and a double gate JFET model for analog integrated circuits." Doklady BGUIR 19, no. 7 (November 25, 2021): 5–12. http://dx.doi.org/10.35596/1729-7648-2021-19-7-5-12.

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One of directions of improving parameters of analog integrated circuits is a development of new and modernization of existing designs of integrated elements without significantly changing of a technological route of integrated circuit manufacturing with a simultaneous creation of new integrated elements models. The article considers the results of experimental studies of the double gate junction field-effect transistor manufactured according to the 3CBiT technological route of JSC Integral. Based on the obtained results, the electrical model of double gate junction field-effect transistor is proposed, which describes the features of its application in analog integrated circuits. Comparison of I-V characteristics of measurements results and created model simulation are presented. A small capacity and a reverse current of a double gate junction field-effect transistor top gate, an ability to compensate for the DC (direct current) component of an input current provide a significant improvement in the characteristics of analog integrated circuits such as electrometric operational amplifiers and charge-sensitive amplifiers. The developed double gate junction field-effect transistor can be used in signal readout devices required in the analog interfaces of space instrument sensors and nuclear electronics.

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Elmezayen, Mohamed R., Wei Hu, Amr M. Maghraby, Islam T. Abougindia, and Suat U. Ay. "Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits." Journal of Low Power Electronics and Applications 10, no. 3 (June 29, 2020): 21. http://dx.doi.org/10.3390/jlpea10030021.

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Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.

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Richelli, Anna. "EMI Susceptibility Issue in Analog Front-End for Sensor Applications." Journal of Sensors 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/1082454.

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The susceptibility to electromagnetic interferences of the analog circuits used in the sensor readout front-end is discussed. Analog circuits still play indeed a crucial role in sensor signal acquisition due to the analog nature of sensory signals. The effect of electromagnetic interferences has been simulated and measured in many commercial and integrated analog circuits; the main cause of the electromagnetic susceptibility is investigated and the guidelines to design high EMI immunity circuits are provided.

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Hafed, M. M., N. Abaskharoun, and G. W. Roberts. "A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits." IEEE Journal of Solid-State Circuits 37, no. 4 (April 2002): 499–514. http://dx.doi.org/10.1109/4.991388.

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KOSAKA, D., M. NAGATA, Y. MURASAKA, and A. IWATA. "Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E90-A, no. 2 (February 1, 2007): 380–87. http://dx.doi.org/10.1093/ietfec/e90-a.2.380.

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Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (January 2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

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The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C language. The Ngspice circuit simulator has been used as a fitness function creator and evaluator. A script file is written to provide an interface between the CS algorithm and the Ngspice simulator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature. The experimental simulation results obtained by the CS algorithm satisfy all desired specifications for this circuit.

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Severo, Lucas Compassi, and Wilhelmus Adrianus Maria Van Noije. "A Generic Test Board for the Electrical Characterization of ULP and ULV Fully-Differential Integrated Analog Circuits." Journal of Integrated Circuits and Systems 14, no. 3 (December 27, 2019): 1–7. http://dx.doi.org/10.29292/jics.v14i3.90.

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The characterization of ultra-low power (ULP) fully-differential/balanced amplifiers and active filters is challenging due to the incompatibility with the classical single-ended (SE) and 50 Ω impedance equipment. Interface circuits between the device under test (DUT) and the equipment are needed to perform the signal conversion and to work as voltage buffers. In this work, we propose a generic test circuits to be used in the characterization of ULP and ultra-low voltage (ULV) analog circuits. The test board includes balun transformers to the signal conversion, a high input impedance and low capacitance output driver and voltage regulators to provide the target DUT supply voltage. The characterization of the proposed PCB demonstrates a bandwidth of 30 MHz, output driver input impedance of 5 MΩ with 2.5 pF capacitance and low input-referred noise. The proposed circuit was applied to the electrical characterization of two fully-differential ULV and ULP analog integrated circuits.

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Touloupas, Konstantinos, and Paul Peter Sotiriadis. "Mixed-Variable Bayesian Optimization for Analog Circuit Sizing through Device Representation Learning." Electronics 11, no. 19 (September 29, 2022): 3127. http://dx.doi.org/10.3390/electronics11193127.

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In this work, a deep representation learning method is proposed to build continuous-valued representations of individual integrated circuit (IC) devices. These representations are used to render mixed-variable analog circuit sizing problems as continuous ones and to apply a low-budget black box Bayesian optimization (BO) variant to solve them. By transforming the initial search spaces into continuous-valued ones, the BO’s Gaussian process models (GPs), which typically operate on real-valued spaces, can be used to guide the optimization search towards the global optimum. The proposed Device Representation Learning approach involves using device simulation data and training a composite model of a Variational Autoencoder (VAE) and a dense Neural Network. The latent variables of the trained VAE model serve as the representations of the integrated device and replace the discrete-valued parametrizations of particular devices. A thorough explanation of the proposed methodology’s mathematical formulation is given and example sizing applications on real-world analog circuits and integrated devices underline its efficiency.

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Quan, Jiale, Zhen Liu, Bo Li, Chuanbin Zeng, and Jiajun Luo. "55 nm CMOS Mixed-Signal Neuromorphic Circuits for Constructing Energy-Efficient Reconfigurable SNNs." Electronics 12, no. 19 (October 5, 2023): 4147. http://dx.doi.org/10.3390/electronics12194147.

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The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achieve compact and biologically plausible SNNs while restricting power consumption, we propose a set of new neuromorphic building circuits, including an analog Leaky Integrate-and-Fire (LIF) neuron circuit, configurable synapse circuits and Spike Driven Synaptic Plasticity (SDSP) learning algorithm circuits. Specifically, we explore methods to minimize large leakage current and device mismatch effects, and optimize the design of these neuromorphic circuits to enable low-power operation. A reconfigurable mixed-signal SNN is proposed based on the building circuits, allowing flexible configuration of synapse weights and attributes, resulting in enhanced SNN functionality and reduced unnecessary power consumption. This SNN chip is fabricated using 55 nm CMOS technology, and test results indicate that the proposed circuits have the ability to closely mimic the behaviors of LIF neurons, synapses and SDSP mechanisms. By configuring synaptic arrays, we established varied connections between neurons in the SNN and demonstrated that this SNN chip can implement Pavlov’s dog associative learning and binary classification tasks, while dissipating less energy per spike of the order of Pico Joules per spike at a firing rate ranging from 30 Hz to 1 kHz. The proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors.

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Fu, Xiao An, Amita Patil, Philip G. Neudeck, Glenn M. Beheim, Steven Garverick, and Mehran Mehregany. "6H-SiC Lateral JFETs for Analog Integrated Circuits." Materials Science Forum 600-603 (September 2008): 1099–102. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1099.

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This paper reports fabrication and electrical characterization of 6H-SiC n-channel, depletion-mode, junction-field-effect transistors (JFETs) for use in high-temperature analog integrated circuits for sensing and control in propulsion, power systems, and geothermal exploration. Electrical characteristics of the resulting JFET devices have been measured across the wafer as a function of temperature, from room temperature to 450oC. The results indicate that the JFETs are suitable for high-gain amplifiers in high-temperature sensor signal processing circuits.

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A. Ashok, Kumar, and Narayanam Balaji. "A comparative analysis of different current mirror techniques in 65nm technology." i-manager's Journal on Circuits and Systems 11, no. 1 (2023): 10. http://dx.doi.org/10.26634/jcir.11.1.19778.

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The Current Mirror (CM) technique is widely used in mixed-mode and analog integrated circuits for tasks such as current amplification, biasing, and active loading. The overall effectiveness of these circuits relies heavily on their efficient designs. Current mirrors are primarily employed to accurately replicate currents in a circuit, offering high stability, simplicity, and scalability. They have become indispensable building blocks in analog and mixed-signal circuits, with their significance growing along with the demand for high-performance and low-power designs. Numerous techniques have been proposed to improve the performance metrics of current mirrors, including accuracy, input resistance, output resistance, and bandwidth. This study compares the advantages and disadvantages of these different current mirror techniques on a unified platform. It includes a comprehensive analysis of various contemporary mirror topologies, and classifies them based on their distinct characteristics. The performances of different current mirrors, including the basic CM, Wilson CM, cascode CM, and folded cascode CM circuits, were thoroughly examined in this analysis. The objective of this study is to select an appropriate current mirror for specific applications. The circuits considered in this study accurately mirror a current of 100 µA with a ±2% error using the Cadence Virtuoso software and UMC 65 nm technology. Process, Voltage, and Temperature (PVT) analysis, along with Monte Carlo simulations, were conducted under similar conditions using a supply voltage of 1.2V to ensure a fair comparison across the various current mirror approaches.

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Mao, Yuqing, Yoann Charlon, Yves Leduc, and Gilles Jacquemod. "LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology." Journal of Low Power Electronics and Applications 14, no. 1 (February 1, 2024): 8. http://dx.doi.org/10.3390/jlpea14010008.

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Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

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Jer-Jaw Hsu and C. Sechen. "DC small signal symbolic analysis of large analog integrated circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41, no. 12 (1994): 817–28. http://dx.doi.org/10.1109/81.340844.

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Mina, Rayan, Chadi Jabbour, and George E. Sakr. "A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation." Electronics 11, no. 3 (January 31, 2022): 435. http://dx.doi.org/10.3390/electronics11030435.

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Analog integrated circuit design is widely considered a time-consuming task due to the acute dependence of analog performance on the transistors’ and passives’ dimensions. An important research effort has been conducted in the past decade to reduce the front-end design cycles of analog circuits by means of various automation approaches. On the other hand, the significant progress in high-performance computing hardware has made machine learning an attractive and accessible solution for everyone. The objectives of this paper were: (1) to provide a comprehensive overview of the existing state-of-the-art machine learning techniques used in analog circuit sizing and analyze their effectiveness in achieving the desired goals; (2) to point out the remaining open challenges, as well as the most relevant research directions to be explored. Finally, the different analog circuits on which machine learning techniques were applied are also presented and their results discussed from a circuit designer perspective.

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Rencher, Mark. "Analog statistical simulation for bipolar integrated circuits." Analog Integrated Circuits and Signal Processing 1, no. 2 (October 1991): 157–64. http://dx.doi.org/10.1007/bf00161308.

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Ahlgren, D. C., S. J. Jeng, D. Nguyen-Ngoc, K. Stein, D. Sunderland, M. Gilbert, J. Malinowski, et al. "Si-Ge heterojunction bipolar technology for high-speed integrated circuits." Canadian Journal of Physics 74, S1 (December 1, 1996): 159–66. http://dx.doi.org/10.1139/p96-851.

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This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

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Pui-In Mak. "Explosive growth calls for more mixed-voltage analog integrated circuits." IEEE Potentials 28, no. 2 (March 2009): 35–36. http://dx.doi.org/10.1109/mpot.2009.931845.

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Gavriilidou, Vasiliki, Andriana Voulkidou, Thomas Noulis, Norocel Codreanu, and Ciprian Ionescu. "System on Chip Noise Integrity Simulation." Chips 1, no. 1 (April 28, 2022): 14–29. http://dx.doi.org/10.3390/chips1010003.

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In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

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Cheng, Ming Yuan, Kwan Ling Tan, Wei Guo Chen, Rui Qi Lim, Maria Ramona B. Damalerio, Lei Yao, Peng Li, Yuan Dong Gu, and Min Kyu Je. "Silicon-Based Multichannel Probe Integrated with a Front End Low Power Neural Recording IC for Acute Neural Recording." Advanced Materials Research 849 (November 2013): 189–94. http://dx.doi.org/10.4028/www.scientific.net/amr.849.189.

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This work presents a silicon-based multichannel probe integrated with a front end low power neural recording integrated circuit (IC) which is used in acute neural recording application. The low power neural recording IC contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. The 100-channel neural recording IC consumes 1.16-mW, making it the optimum solution for multi-channel neural recording systems. The neural recording IC and Si probe are integrated in a printed circuit board (PCB) which is fixed on the skull using dental resin. Digital neural signal is converted to analog signal and output by neural recording IC. The signal-to-noise ratio of neural recording signal can be increased through the reduction of interconnect length. The buckling strength of the fabricated probes was simulated using finite element analysis and measured by compression tester. The packaging method of 2D probe and neural recording IC was successfully demonstrated. The impedance of the assembled probe is also measured and discussed. To verify the functionality of Si probe integrated with neural recording IC, a pseudo neural signal acquisitions have been perform.

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Ali, Liakot, and Farshad. "Analog hardware trojan design and detection in OFDM based wireless cryptographic ICs." PLOS ONE 16, no. 7 (July 29, 2021): e0254903. http://dx.doi.org/10.1371/journal.pone.0254903.

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Due to Hardware Trojan (HT), trustworthiness of Integrated Circuit (IC) supply chain is a burning issue in Semiconductor Industry nowadays. Over the last decade, extensive research has been carried on HT detection methods for digital circuits. However, the HT issue remains largely unexplored in the domain of Analog Mixed Signal (AMS)/ RF circuit where it is now an appealing target for the attackers. The increasing popularity of Orthogonal Frequency Division Multiplexing (OFDM) based wireless cryptographic ICs in modern communication systems makes it a lucrative target for HT-based attacks which could have a devastating impact on data security. This paper presents a trigger-based Hardware Trojan Threat model that exploits the extended cyclic prefix (ECP) property of the OFDM communication scheme to leak the secret encryption key over low noise Additive White Gaussian Channel (AWGN) and developed a Cyclic Prefix (CP) checker based detection mechanism named “SENTRY” to detect such trojans once it is triggered.

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Journal articles on the topic 'Analog and mixed-signal integrated circuits'

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