Dissertations / Theses on the topic 'Amplificateur à gain variable'
To see the other types of publications on this topic, follow the link: Amplificateur à gain variable.
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'Amplificateur à gain variable.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Fechine, Sette Elmo Luiz. "Circuits intégrés millimétriques en bande Ka pour une antenne à pointage électronique pour les télécommunications avec des satellites géostationnaires ou des constellations de satellites." Electronic Thesis or Diss., Limoges, 2024. http://www.theses.fr/2024LIMO0002.
Abstract:
Ce travail présente la conception de circuits actifs intégrés en vue d'une intégration dans une antenne à dépointage électronique pour les télécommunications par satellite en bande Ka. Tout d'abord, le manuscrit présente le contexte dans lequel se déroule l'étude, abordant les principaux concepts et caractéristiques de ce type d'antenne. Par la suite, deux blocs clés de la chaîne d’émission sont étudiés en détail et conçus : un amplificateur de puissance à gain variable et trois déphaseurs pilotables. Les circuits sont réalisés en utilisant deux technologies SiGe BiCMOS: BiCMOS9MW et SG13G2. Enfin, les résultats de simulation post-layout sont exposés et comparés aux spécifications du projet ainsi qu'à l'état de l'artThis work presents the design of active integrated circuits intended for integration into an electronically steered antenna for Ka-band satellite communications. Firstly, the manuscript introduces the context of the study, discussing the main concepts and characteristics of this type of antenna. Subsequently, two key blocks of the transmission chain are studied in detail and designed: a variable gain power amplifier and three controllable phase shifters. The circuits are implemented using two SiGe BiCMOS technologies: BiCMOS9MW and SG13G2. Finally, the post-layout simulation results are presented and compared to the project specifications as well as the state of the art
2
Deza, Julien. "Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm." Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0680/document.
Abstract:
Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquenceThis thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation
3
Haghighitalab, Delaram. "Récepteur radio-logicielle hautement numérisé." Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066443.
Abstract:
Aujourd'hui, il y a une augmentation du nombre de normes étant intégré dans des appareils mobiles. Les problèmes principaux sont la durée de vie de la batterie et la taille de l'appareil. L'idée d'un Radio-Logiciel est de pousser le processus de numérisation aussi près que possible de l'antenne. Dans cette thèse, nous présentons la première mise en œuvre d'un récepteur radio-logiciel complet basé sur Sigma-Delta RF passe-bande, y compris un LNA à gain variable (VGLNA), un ADC Sigma-Delta RF sous-échantillonné, un mélangeur bas-conversion RF numérique et un filtre de décimation polyphasé multi-étage multi-taux. Le VGLNA élargit la gamme dynamique du récepteur multi-standard pour atteindre les exigences des trois normes sans fil ciblées. Aussi une architecture mixte, en utilisant à la fois Source-Coupled Logic (SCL) et des circuits CMOS, il est proposé d'optimiser la consommation des circuits RF numériques. Par ailleurs, nous proposons une architecture de filtre en peigne à plusieurs étages avec décomposition polyphase à réduire la consommation d'énergie. Le récepteur est mesuré pour trois normes différentes dans la bande de 2.4 GHz, la bande ISM. Les résultats des mesures montrent que le récepteur atteint 79 dB, 73 dB et 63 dB de plage dynamique pour les normes Bluetooth, ZigBee et WiFi respectivement. Le récepteur complet, mis en œuvre dans le procédé CMOS 130 nm, a une fréquence centrale accordable de 300 MHz et consomme 63 mW sous 1.2 V. Comparé à d'autres récepteurs, le circuit proposé consomme 30% moins d'énergie, la plage dynamique est de 21 dB supérieur, IIP3 est de 6 dB supérieur et le facteur de mérite est de 24 dB supérieurNowadays there is an increase in the number of standards being integrated in mobile devices. The main issues are battery life and the size of the device. The idea of a Software Defined Radio is to push the digitization process as close as possible to the antenna. Having most of the circuit in the digital domain allows it to be reconfigurable thus requiring less area and power consumption. In this thesis, we present the first implementation of a complete SDR receiver based on RF bandpass Sigma-Delta including a Variable-Gain LNA (VGLNA), an RF subsampled Sigma-Delta ADC, an RF digital down-conversion mixer and a polyphase multi-stage multi-rate decimation filter. VGLNA enlarges the dynamic range of the multi-standard receiver to achieve the requirements of the three targeted wireless standards. Also a mixed architecture, using both Source-Coupled Logic (SCL) and CMOS circuits, is proposed to optimize the power consumption of the RF digital circuits. Moreover, we propose a multi-stage comb filter architecture with polyphase decomposition to reduce the power consumption. The receiver is measured for three different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79 dB, 73 dB and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply. Compared to other SDR receivers, the proposed circuit consumes 30% less power, the DR is 21 dB higher, IIP3 is 6 dB higher and the overall Figure of Merit is 24 dB higher
4
Haghighitalab, Delaram. "Récepteur radio-logicielle hautement numérisé." Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066443.
Abstract:
Aujourd'hui, il y a une augmentation du nombre de normes étant intégré dans des appareils mobiles. Les problèmes principaux sont la durée de vie de la batterie et la taille de l'appareil. L'idée d'un Radio-Logiciel est de pousser le processus de numérisation aussi près que possible de l'antenne. Dans cette thèse, nous présentons la première mise en œuvre d'un récepteur radio-logiciel complet basé sur Sigma-Delta RF passe-bande, y compris un LNA à gain variable (VGLNA), un ADC Sigma-Delta RF sous-échantillonné, un mélangeur bas-conversion RF numérique et un filtre de décimation polyphasé multi-étage multi-taux. Le VGLNA élargit la gamme dynamique du récepteur multi-standard pour atteindre les exigences des trois normes sans fil ciblées. Aussi une architecture mixte, en utilisant à la fois Source-Coupled Logic (SCL) et des circuits CMOS, il est proposé d'optimiser la consommation des circuits RF numériques. Par ailleurs, nous proposons une architecture de filtre en peigne à plusieurs étages avec décomposition polyphase à réduire la consommation d'énergie. Le récepteur est mesuré pour trois normes différentes dans la bande de 2.4 GHz, la bande ISM. Les résultats des mesures montrent que le récepteur atteint 79 dB, 73 dB et 63 dB de plage dynamique pour les normes Bluetooth, ZigBee et WiFi respectivement. Le récepteur complet, mis en œuvre dans le procédé CMOS 130 nm, a une fréquence centrale accordable de 300 MHz et consomme 63 mW sous 1.2 V. Comparé à d'autres récepteurs, le circuit proposé consomme 30% moins d'énergie, la plage dynamique est de 21 dB supérieur, IIP3 est de 6 dB supérieur et le facteur de mérite est de 24 dB supérieurNowadays there is an increase in the number of standards being integrated in mobile devices. The main issues are battery life and the size of the device. The idea of a Software Defined Radio is to push the digitization process as close as possible to the antenna. Having most of the circuit in the digital domain allows it to be reconfigurable thus requiring less area and power consumption. In this thesis, we present the first implementation of a complete SDR receiver based on RF bandpass Sigma-Delta including a Variable-Gain LNA (VGLNA), an RF subsampled Sigma-Delta ADC, an RF digital down-conversion mixer and a polyphase multi-stage multi-rate decimation filter. VGLNA enlarges the dynamic range of the multi-standard receiver to achieve the requirements of the three targeted wireless standards. Also a mixed architecture, using both Source-Coupled Logic (SCL) and CMOS circuits, is proposed to optimize the power consumption of the RF digital circuits. Moreover, we propose a multi-stage comb filter architecture with polyphase decomposition to reduce the power consumption. The receiver is measured for three different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79 dB, 73 dB and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply. Compared to other SDR receivers, the proposed circuit consumes 30% less power, the DR is 21 dB higher, IIP3 is 6 dB higher and the overall Figure of Merit is 24 dB higher
5
Dasgupta, Abhijeet. "High efficiency S-Band vector power modulator design using GaN technology." Thesis, Limoges, 2018. http://www.theses.fr/2018LIMO0021/document.
Abstract:
L’évolution des systèmes de télécommunications, liée à une demande sans cesse croissante en termes de débit et de volume de données, se concrétise par le développement de systèmes proposant des bandes passantes très larges, des modulations à très hautes efficacités spectrales, de la flexibilité en puissance et en fréquence d’émission. Par ailleurs, la mise en œuvre de ces dispositifs doit se faire avec un souci permanent d’économie d’énergie d’où la problématique récurrente de l’amplification de puissance RF qui consiste à allier au mieux rendement, linéarité et bande passante. L’architecture conventionnelle d’une chaine d’émission RF consiste dans une première étape à réaliser l’opération de modulation-conversion de fréquence (Modulateur IQ) puis dans une deuxième étape l’opération de conversion d’énergie DC-RF (Amplificateur de Puissance), ces deux étapes étant traditionnellement traitées de manière indépendante. L’objectif de ces travaux de thèse est de proposer une approche alternative qui consiste à combiner ces deux opérations dans une seule et même fonction : le modulateur vectoriel de puissance à haute efficacité énergétique. Le cœur du dispositif, conçu en technologie GaN, repose sur un circuit à deux étages de transistors HEMT permettant d’obtenir un gain en puissance variable en régime de saturation. Il est associé à un modulateur de polarisation multi-niveaux spécifique également en technologie GaN. Le dispositif réalisé a permis de générer directement, à une fréquence de 2.5 GHz, une modulation vectorielle 16QAM (100Msymb/s) de puissance moyenne 13 W, de puissance crête 25W avec un rendement global de 40% et une linéarité mesurée par un EVM à 5%The evolution of telecommunications systems, linked to a constantly increasing demand in terms of data rate and volume, leads to the development of systems offering very wide bandwidths, modulations with very high spectral efficiencies, increased power and frequency flexibilities in transmitters. Moreover, the implementation of such systems must be done with a permanent concern for energy saving, hence the recurring goal of the RF power amplification which is to combine the best efficiency, linearity and bandwidth. Conventional architectures of RF emitter front-ends consist in a first step in performing the frequency modulation-conversion operation (IQ Modulator) and then in a second step the DC-RF energy conversion operation (Power Amplifier), these two steps being usually managed independently. The aim of this thesis is to propose an alternative approach that consists in combining these two operations in only one function: a high efficiency vector power modulator. The core of the proposed system is based on a two-stage GaN HEMT circuit to obtain a variable power gain operating at saturation. It is associated with a specific multi-level bias modulator also design using GaN technology. The fabricated device generates, at a frequency of 2.5 GHz, a 16QAM modulation (100Msymb/s) with 13W average power, 25W peak power, with an overall efficiency of 40% and 5% EVM
6
Ayad, Mohammed. "Etude et Conception d’amplificateurs DOHERTY GaN en technologie Quasi - MMIC en bande C." Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0027.
Abstract:
Ce travail répond à un besoin industriel accru en termes d’amplification des signaux sur porteuses à enveloppes variables utilisés par les systèmes de télécommunications actuels. Ces signaux disposent d’un fort PAPR et d’une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. La raison pour laquelle les industriels télécoms requièrent alors des amplificateurs de très fortes puissances de sortie, robustes, fiables et ayant une dépense énergétique optimale le long de la dynamique d’enveloppe associée à un niveau de linéarité acceptable. Ce document expose les résultats d’étude et de réalisation de deux Amplificateurs de Puissance Doherty (APD) à haut rendement encapsulés en boîtiers plastiques QFN. Le premier est un amplificateur Doherty symétrique classique (APD-SE) et le second est un amplificateur à deux entrées RF (APD-DE). Ces démonstrateurs fonctionnant en bande C sont fondés sur l’utilisation de la technologie Quasi-MMIC associant des barrettes de puissance à base des transistors HEMTs AlGaN/GaN sur SiC à des circuits d’adaptation en technologie ULRC. L’approche Quasi-MMIC associée à la solution d’encapsulation plastique QFN permettant une meilleure gestion des comportements thermiques offre des performances électriques similaires à celles de la technologie MMIC avec des coûts et des cycles de fabrication très attractifs. Durant ces travaux, une nouvelle méthode d’évaluation des transistors dédiés à la conception d’amplificateurs Doherty a été développée et mise en oeuvre. L’utilisation intensive des simulations électromagnétiques 2.5D et 3D a permis de bien prendre en compte les effets de couplages entre les différents circuits dans l’environnement du boîtier QFN. Les résultats des tests des amplificateurs réalisés fonctionnant sur une bande de 1GHz ont permis de valider la méthode de conception et ont montré que les concepts avancés associés à l’approche Quasi-MMIC ainsi qu’à des technologies d’encapsulation plastique, peuvent générer des fonctions micro-ondes innovantes. Les caractérisations de l’APD-DE ont relevé l’intérêt inhérent à la préformation des signaux d’excitation et des points de polarisation de chaque étage de l’amplificateurThis work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier
7
Lablonde, Laurent. "Etude des non-linéarites de gain d'un amplificateur optique à semi-conducteur." Limoges, 1996. http://www.theses.fr/1996LIMO0029.
Abstract:
Les non-linearites de gain d'un amplificateur optique a semi-conducteurs interviennent negativement ou positivement dans les reseaux de telecommunications optiques. Nous presentons dans ce memoire l'etude de ces non-linearites et des configurations permettant de les reduire ou de les exploiter selon l'orientation souhaitee. Un signal d'intensite saturante peut etre particulierement distordu a l'amplification lorsque sa variation d'intensite est au moins du meme ordre de grandeur que le temps de vie des porteurs de la zone active. La reduction du contraste et la derive frequentielle en sont les principales caracteristiques et augmentent de ce fait le taux d'erreurs d'une transmission numerique. La nouvelle technique de transmission d'un multiplex de longueurs d'onde est elle aussi handicapee en raison de la saturation du gain sur toute la bande passante. On peut augmenter l'intensite de saturation du module amplificateur en realisant une contre-reaction optique selective en longueur d'onde. Le gain est alors stabilise sur une plus large gamme de valeur d'intensite du signal. Nous avons etudie la stabilisation du gain obtenue par un tel systeme dans le cas d'une information numerique avec une cavite constituee de reseaux photoinscrits dans les fibres d'acces. D'autre part, ces non-linearites de gain peuvent etre utilisees pour realiser des fonctions optiques comme la conversion de longueur d'onde par saturation croisee de gain. Nous presentons dans ce travail les resultats experimentaux et une analyse theorique d'un nouveau dispositif que nous avons mis au point, permettant de regenerer le contraste d'un signal numerique converti. Il remet en valeur les convertisseurs a saturation croisee de gain, plus simples et robustes que les convertisseurs interferometriques en cours d'etude, qui peuvent par ailleurs aussi etre integres dans le dispositif propose
8
Oksasoglu, Ali 1960. "GAIN-BANDWIDTH EFFECTS IN THE STATE-VARIABLE FILTERS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276419.
9
Rahmatian, Behnoosh. "A 75-dB digitally programmable CMOS variable gain amplifier." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/32248.
Abstract:
A 75-dB DIGITALLY PROGRAMMABLE CMOS VARIABLE GAIN AMPLIFIER
Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems.
In this thesis, a monolithic low-power digitally programmable VGA with 75dB of gain range is
presented. The VGA is targeted for power line communication systems in particular for
automotive application; however, it is a generic block that can be use in other applications. The
core of the design is based on the low-distortion source-degenerated differential amplifier
structure. A gm-boosting circuit is also used to provide higher gain and improve gain accuracy.
In this work, to control the gain a new technique is used which is based on digitally controlling:
1) the source-degeneration resistance, and 2) an additional resistance between the differential
output nodes of each gain stage. The changes in the source-degeneration resistance handle the
coarse tuning, and the changes in the latter resistance are used for fine gain tuning.
The overall VGA consists of three such gain stages. As a proof of concept, a single gain stage
with a gain range of 24dB and programmable in 2dB gain steps has been fabricated in a 0.18μm
CMOS technology. The chip is tested and measurement results are obtained. Based on these
measurement results, the design of the gain stage is optimized and a three-stage 75dB VGA is
designed. Each stage has a digitally tunable gain range of 25dB, and fine gain tuning of 2.5dB
per step. The bandwidth of the VGA is higher than 140MHz, and the gain error is less than
0.3dB. The overall VGA draws 6.5mA from a 1.8V supply. The noise figure of the system at
maximum gain is 12.5dB, and the IIP3 is 14.4dBm at minimum gain. These performance
parameters are either better or compare favorably with the reported state-of-the-art VGAs.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
10
Jha, Nand Kishore. "Design of a complementary silicon-germanium variable gain amplifier." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.
11
Moreau, Aurélie. "Réseaux de Bragg intracavité en milieu amplificateur." Phd thesis, Télécom ParisTech, 2006. http://pastel.archives-ouvertes.fr/pastel-00001975.
Abstract:
Les réseaux de diffraction sont largement utilisés dans le traitement optique de l'information. Toutefois, les applications nécessitent des efficacités de diffraction importantes, d'excellentes résolutions dans le domaine des fréquences spatiales et des temps de réponses appropriés à la fonction recherchée (grande durée de vie pour les mémoires, temps de réponses rapide pour les opérations de traitements de l'information...). Ces qualités étant difficiles à obtenir à l'aide des matériaux existants, une solution consiste à placer le matériau non-linéaire à l'intérieur d'une cavité Fabry-Pérot, avec le double avantage d'obtenir une efficacité de diffraction fortement accrue et une résolution dans le domaine des fréquences spatiales améliorée. Le mémoire rapporte comment l'utilisation d'un milieu intracavité amplificateur permet d'accroître encore davantage la puissance du faisceau diffracté, avec des efficacités de diffraction largement supérieures à l'unité. Les propriétés diffractives des réseaux d'indice et/ou de gain insérés dans un résonateur de Fabry-Pérot amplificateur de longueur supérieure ou égale à l'épaisseur du réseau sont analysées théoriquement et expérimentalement. Un modèle analytique a été élaboré et a permis de montrer l'immense potentiel de tels dispositifs, en terme de sélectivité angulaire et d'efficacité de diffraction, cette dernière pouvant être très largement supérieure à l'unité. Un dispositif expérimental a ensuite été conçu afin de prouver la faisabilité du concept et de valider le modèle analytique. Le milieu non-linéaire intracavité est un cristal de Nd:YVO4. Le réseau est inscrit optiquement par absorption de la figure d'interférence de deux faisceaux d'écriture. La diffraction du signal de lecture est analysée autour de la double résonance de Bragg et de Fabry-Pérot, ainsi qu'à proximité de l'une ou de l'autre résonance séparément, afin de remonter aux propriétés diffractives du réseau. Les résultats expérimentaux sont en bon accord avec les calculs numériques issus du modèle analytique. La comparaison avec le réseau de Bragg hors cavité montre l'amélioration significative apportée par la cavité amplificatrice: l'efficacité de diffraction est augmentée d'un facteur 5000 et la sélectivité angulaire d'un facteur proche de 20. Ces résultats sont très encourageants pour une application de ce type de dispositif au traitement optique de l'information, surtout dans le cas où une très forte sortance est nécessaire.
12
Krishnanji, Sivasankari. "Design of a variable gain amplifier for an ultrawideband receiver." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2576.
Abstract:
A fully differential CMOS variable gain amplifier (VGA) has been designed for
an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by
a post amplifier stage. The interface between the digital control block and the analog
VGA is formed by a digital-to-analog converter and an exponential voltage generator.
The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control
voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz
throughout the gain range to cater to the requirements of the ultra-wideband system. The
noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low
gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting.
All three stages use common mode feedback to fix and stabilize the output DC levels at
a particular voltage depending on the input common-mode requirement of the following
stage. DC offset cancellation has also been incorporated to minimize the input referred
DC offset caused by systematic and random mismatches in the circuit. Compensation
schemes to minimize the effects of temperature, supply and process variations have been
included in the design. The circuit has been designed in 0.18??m CMOS technology, and
the post layout simulations are in good agreement with the schematic simulations.
13
Bohémond, Christian. "Mélangeur de signaux hyperfréquences basé sur la modulation croisée du gain d’un amplificateur optique à semi-conducteurs." Brest, 2010. http://www.theses.fr/2010BRES2023.
Abstract:
L’amplificateur optique à semi-conducteurs (SOA) est désormais un composant multifonctiormel capable d’intégrer une liaison opto-hyperfréquence et de réaliser des fonctions tout-optiques. Dans cette étude, nous utilisons le SOA comme convertisseur de signaux hyperfréquences (HP) en exploitant la modulation croisée de son gain (XGM). Deux architectures ont été étudiées : tout d’abord le SOA a été utilisé comme mélangeur tout-optique et ensuite comme mélangeur électro-optique. Cette étude est réalisée à la fois expérimentalement sur un banc de mesures, théoriquement à partir d’équations petit-signal, et par simulation à l’aide d’un modèle développé sous le logiciel ADS-d’Agilent Technologies. Les résultats théoriques et les simulations ont été validés suite à leur confrontation aux résultats expérimentaux. Ils ont été ensuite utilisés tout au long de cette étude. Nous avons mesuré les performances statiques et dynamiques ainsi que la linéarité du mélangeur tout-optique. Le gain de conversion a été étudié en fonction des différents paramètres du mélange et nous avons montré qu’il est directement lié au gain optique du SOA et qu’il lui est toujours inférieur. L’émission spontanée amplifiée (ASE) générée par le SOA a été étudiée comme une source optique modulée participant au phénomène du mélange et le bruit de phase du signal converti a aussi été analysé. Les deux mélangeurs ont réalisé la conversion de signaux codés selon différents formats de modulation numérique complexes (QPSK, 16 et 64 QAM). Une conversion efficace avec un gain de conversion positif, sans distorsion ni dégradation significative sur les données numériques converties, a pu être réalisée, prouvant la capacité de nos mélangeurs à être insérés dans un système de communication completThe Semiconductor Optical Amplifier (SOA) is a multifunctional device that can be integrated into a Radiofrequency-optical link and carry out all-optical functions. In this study, the SOA is used as a hyperfrequency (HP) converter based on Cross Gain Modulation (XGM). Two architectures have been studied: an SOA is firstly used as an all-optical microwave mixer and secondly as an electro-optical mixer. This study is realized both experimentally and theoretically both with small-signal modelling and a model developed under ADS software (Agilent Technologies). The theoretical results have been compared to the simulation results obtained with the aid of ADS and to the experimental results. All the obtained results are in good agreernent and the SOA model developed under ADS has been validated and uses throughout this study. We have measured the static and dynamic performances and the linearity of the all-optical mixer. The conversion gain has been studied with different parameters of the mixer and we have proved that it is directly related to the optical gain of SOA. The Amplified Spontaneous Emission (ASE) generated by the SOA acts as an optical modulated source participing in mixing phenomenon. The phase noise of the converted signal has been also analyzed. The two mixers allow the conversion of digital signals with complex modulation formats (QPSK, 16 and 64 QAM). An effective conversion with a positive conversion gain, without significant distortion or degradation of the converted numerical data, has been found, proving the ability of our mixers to be used as a part of a complete communication system
14
Feng, Mabel Y. "Frequency translation method for low frequency variable gain amplification and filtering." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/41642.
Abstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (leaves 75-78).
This thesis discusses an innovative solution to an industry challenge. A frequency translation method is designed to shift low frequency signals to intermediate frequencies in order to utilize higher-frequency components. This solution, appropriate for applications involving 1-10MHz signals, can provide continuously variable gain and filtering at little cost in dynamic performance. The working system converts the low frequency signals up to the 70MHz band to achieve up to 28dB attenuation and 60-86MHz variable filtering. A Single Side Band system has a Signal-to-Noise Ratio (SNR) of 71dB with a 73dB SNR Analog-to-Digital Converter (ADC), 44 dB Output Third-Order Intercept Point (OIP3), and a Noise Figure (NF) of 14dB. Ultrasound and other applications in the 1-10MHz range benefit greatly from this upconversion scheme.
by Mabel Y. Feng.
M.Eng.
15
Diab-el-Arab, Hilda. "Conception et réalisation d'un filtre actif de type RC utilisant un amplificateur de gain fini en technologie MMIC." Paris 11, 2001. http://www.theses.fr/2001PA112330.
Abstract:
Ce travail traite de la conception de filtres analogiques utilisant des amplificateurs de tension. Cette étude résulte de la transposition aux fréquences micro-ondes des principes utilisés aux basses fréquences. D'abord nous avons étudié le filtre dans sa structure générale pour en déduire une structure optimale. En choisissant judicieusement les valeurs des éléments passifs de cette dernière, nous pouvons réaliser un filtre passe-bande stable, accordable et facile à intégrer dans d'autres cellules élémentaire. De plus, nous avons étudié la non-idéalité de l'amplificateur sur les performances du filtre. Nous avons recherché une topologie d'amplificateur à gain fini utilisant le principe de la contre-réaction. Une seule structure a été retenue pour sa stabilité et ses performances proche de celles désirées, à savoir un gain de module constant et une phase quasi nulle dans la bande de freéquence de travail. .This work deals with the design of analog biquadratic filters using voltage amplifiers. This study results from the transposition of such filter into microwaves. At first the filter was studied in its holistic struture in order to obtain its optimal configuration. By choosing wisely passive elements values of the later a band-pass filter was realized, which is stable accordable and simple to integrate in other cellular elements. However, this filter is highly sensitive to its constitutive elements. Among the elements that might influence the filter performance is the no-ideality of the amplifier. These things were examined and it was revealed that the no-ideality impair the filter fonction. Furthermore, a major part of this study focused on searching for a topology of a finite gain amplifier based on a feedback principle. .
16
Lo, Keng Wai. "Wideband active-balun variable-gain low-noise amplifier for mobile-TV applications." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2148237.
17
De, Souza Marcelo. "Conception d'amplificateur faible bruit reconfigurable en technologie CMOS pour applications de type radio adaptative." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0295/document.
Abstract:
Les systèmes de communication mobiles permettent l’utilisation de l’information en environnements complexes grâce à des dispositifs portables qui ont comme principale restriction la durée de leurs batteries. Des nombreux efforts se sont focalisés sur la réduction de la consommation d’énergie des circuits électroniques de ces systèmes, une fois que le développent des technologies des batteries ne avance pas au rythme nécessaire. En outre, les systèmes RF sont généralement conçus pour fonctionner de manière fixe, spécifiés pour le pire cas du lien de communication. Toutefois, ce scénario peut se produire dans une petite partie du temps, entraînant ainsi en perte d’énergie dans le reste du temps. La recherche des circuits RF adaptatifs, pour adapter le niveau du signal d'entrée pour réduire la consommation d'énergie est donc d'un grand intérêt et de l'importance. Dans la chaîne de réception radiofréquence, l'amplificateur à faible bruit (LNA) se montre un composant essentiel, autant pour les performances de la chaîne que pour la consommation d'énergie. Au cours des dernières décennies, des techniques pour la conception de LNAs reconfigurables ont été proposées et mises en oeuvre. Cependant, la plupart d'entre elles s’applique seulement au contrôle du gain, sans exploiter Le réglage de la linéarité et du bruit envisageant l'économie d'énergie. De plus,ces circuits occupent une grande surface de silicium, ce qui entraîne un coût élevé, ou NE correspondent pas aux nouvelles technologies CMOS à faible coût. L'objectif de cette étude est de démontrer la faisabilité et les avantages de l'utilisation d'un LNA reconfigurable numériquement dans une chaîne de réception radiofréquence, du point de vue de la consommation d'énergie et de coût de fabricationMobile communication systems allow exploring information in complex environments by means of portable devices, whose main restriction is battery life. Once battery development does not follow market expectations, several efforts have been made in order to reduce energy consumption of those systems. Furthermore, radio-frequency systems are generally designed to operate as fixed circuits, specified for RF link worst-case scenario. However, this scenario may occur in a small amount of time, leading to energy waste in the remaining periods. The research of adaptive radio-frequency circuits and systems, which can configure themselves in response to input signal level in order to reduce power consumption, is of interest and importance. In a RF receiver chain, Low Noise Amplifier (LNA) stand as critical elements, both on the chain performance or power consumption. In the past some techniques for reconfigurable LNA design were proposed and applied. Nevertheless, the majority of them are applied to gain control, ignoring the possibility of linearity and noise figure adjustment, in order to save power. In addition, those circuits consume great area, resulting in high production costs, or they do not scale well with CMOS. The goal of this work is demonstrate the feasibility and advantages in using a digitally controlled LNA in a receiver chain in order to save area and power
Os sistemas de comunicação móveis permitem a exploração da informação em ambientes complexos através dos dispositivos portáteis que possuem como principal restrição a duração de suas baterias. Como o desenvolvimento da tecnologia de baterias não ocorre na velocidade esperada pelo mercado, muitos esforços se voltam à redução do consumo de energia dos circuitos eletrônicos destes sistemas. Além disso, os sistemas de radiofrequência são em geral projetados para funcionarem de forma fixa, especificados para o cenário de pior caso do link de comunicação. No entanto, este cenário pode ocorrer em uma pequena porção de tempo, resultando assim no restante do tempo em desperdício de energia. A investigação de sistemas e circuitos de radiofrequência adaptativos, que se ajustem ao nível de sinal de entrada a fim de reduzir o consumo de energia é assim de grande interesse e importância. Dentro de cadeia de recepção de radiofrequência, os Amplificadores de Baixo Ruído (LNA) se destacam como elementos críticos, tanto para o desempenho da cadeia como para o consumo de potência. No passado algumas técnicas para o projeto de LNA reconfiguráveis foram propostas e aplicadas. Contudo, a maioria delas só se aplica ao controle do ganho, deixando de explorar o ajuste da linearidade e da figura de ruído com fins de economia de energia. Além disso, estes circuitos ocupam grande área de silício, resultando em alto custo, ou então não se adaptam as novas tecnologias CMOS de baixo custo. O objetivo deste trabalho é demonstrar a viabilidade e as vantagens do uso de um LNA digitalmente configurável em uma cadeia de recepção de radiofrequência do ponto de vista de custo e consumo de potência
18
Ehteshamuddin, Mohammed. "Design of a High Temperature GaN-Based Variable Gain Amplifier for Downhole Communications." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/74958.
Abstract:
The decline of easily accessible reserves pushes the oil and gas industry to explore deeper wells, where the ambient temperature often exceeds 210 °C. The need for high temperature operation, combined with the need for real-time data logging has created a growing demand for robust, high temperature RF electronics. This thesis presents the design of an intermediate frequency (IF) variable gain amplifier (VGA) for downhole communications, which can operate up to an ambient temperature of 230 °C. The proposed VGA is designed using 0.25 μm GaN on SiC high electron mobility transistor (HEMT) technology. Measured results at 230 °C show that the VGA has a peak gain of 27dB at center frequency of 97.5 MHz, and a gain control range of 29.4 dB. At maximum gain, the input P1dB is -11.57 dBm at 230 °C (-3.63 dBm at 25 °C). Input return loss is below 19 dB, and output return loss is below 12 dB across the entire gain control range from 25 °C to 230 °C. The variation with temperature (25 °C to 230 °C) is 1 dB for maximum gain, and 4.7 dB for gain control range. The total power dissipation is 176 mW for maximum gain at 230 °C.Master of Science
19
Richard, Gaetan C., and Daniel G. Gonzales. "A NEW VARIABLE BEAMWIDTH ANTENNA FOR TELEMETRY TRACKING SYSTEMS." International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/608402.
Abstract:
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, NevadaThis paper presents a new variable beamwidth antenna designed for use in telemetry tracking systems when a high gain/low gain antenna configuration is required. This antenna can be commanded to continuously vary its beamwidth between a high gain/narrow beamwidth mode of operation and a low gain/ wide beamwidth mode of operation. A design goal of a 4:1 increase in beamwidth has been set and a 3.0:1 increase has been achieved without causing any significant degradation in the shape of the antenna patterns and without generating exceedingly high sidelobes in the low gain setting. The beamwidth variation occurs continuously without any loss of data, boresight shift or jitter such as experienced with the operation of conventional implementations of the high gain/low gain antenna technique.
20
Al-Sweiti, Yousef M. "Modeling and control of an elastic ship mounted crane using variable gain model based controller." [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=980984157.
21
Chen, Lin. "A low power, high dynamic-range, broadband variable gain amplifier for an ultra wideband receiver." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5843.
Abstract:
A fully differential Complementary Metal-Oxide Semiconductor (CMOS) Variable
Gain Amplifier (VGA) consisting of complementary differential pairs with source
degeneration, a current gain stage with programmable current mirror, and resistor loads is
designed for high frequency and low power communication applications, such as an Ultra
Wideband (UWB) receiver system. The gain can be programmed from 0dB to 42dB in 2dB
increments with -3dB bandwidth greater than 425MHz for the entire range of gain. The 3rd-order
intercept point (IIP3) is above -13.6dBm for 1Vpp differential input and output
voltages. These low distortion broadband features benefit from the large linear range of the
differential pair with source degeneration and the low impedance internal nodes in the
current gain stages. In addition, common-mode feedback is not required because of these
low impedance nodes. Due to the power efficient complementary differential pairs in the
input stage, power consumption is minimized (9.5mW) for all gain steps. The gain control
scheme includes fine tuning (2dB/step) by changing the bias voltage of the proposed
programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. A capacitive frequency compensation
scheme is used to further extend the VGA bandwidth.
22
Amaya, Mohammad. "Amélioration des performances d'un amplificateur optique à semi-conducteurs par injection optique à la transparence du gain pour les réseaux de télécommunications optiques." Brest, 2006. http://www.theses.fr/2006BRES2025.
Abstract:
L'amplificateur optique à semi-conducteurs (SOA) est un composant attractif pour les futurs réseaux de télécommunications tout-optiques multicolores métropolitains. Ce travail présente une étude théorique et expérimentale des performances statiques et dynamiques d'un SOA, lors de l'injection optique à la transparence du gain dans sa zone active dans l'objectif d'établir les effets intéressants de cette technique. Nos travaux ont montrée que la pompe optique apporte une amélioration importante en terme de la puissance de saturation de sortie, de la durée de vie des porteurs et du temps de récupération du gain du soa, sur une grande plage de longueurs d'onde et de puissances du signal d'entrée, sans sacrifier le niveau du gain non saturé ni dégrader le facteur de bruit (NF). Nos résultats théoriques et expérimentaux ont montré que l'injection de la pompe optique en sens contra-propagatif par rapport au signal incident est plus efficace que l'injection en sens co-propagatif. Nous avons employé la pompe optique dans un système de transmission multicanaux (WDM) à base de SOA afin de réduire la diaphonie entre les signaux optiques transmis, due aux effets de la modulation croisée du gain (XGM), et d'améliorer ainsi le taux d'erreurs binaires (TEB). Enfin, l'étude présentée a également permis de développer un outil de simulation qui donne des résultats en accord avec ceux obtenus par mesuresSemiconductor optical amplifier (SOA) is an attractive component for future metropolitan multicolor all-optical telecommunication networks. This work focuses on the theoretical and experimental study of the SOA static and dynamic performances, when injecting a continuous wave (CW) high power as a holding beam (HB) at the gain transparency wavelength into its cavity with the aim of pointing out the interesting effects of this technique. Our work has shown that employing the holding beam, improves the soa saturation output power, the carrier lifetime and the device gain recovery time, over a wideband of incident signal wavelengths and powers without sacrificing the amplifier gain level neither degrading its noise figure (NF). Our theoretical and experimental results point out that injecting the holding beam in counter-propagative configuration with respect to the optical incident signal is more efficient than that in co-propagative one. We have employed the holding beam injection in an SOA based WDM multichannel transmission system with the purpose of reducing the cross-gain modulation (XGM) induced inter-channel crosstalk, hence, of improving the signals bit error rate (BER). Finally, a simulation model which gives results close to the measured ones has been obtained during this work as well
23
Azmat, Rehan. "Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449.
Abstract:
The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.
24
Mitra, Dipankar. "A Variable High Gain and High Dynamics Range CMOS Phase Shifter for Phased Array Antenna Applications." Thesis, North Dakota State University, 2016. https://hdl.handle.net/10365/28033.
Abstract:
Phase shifters can adjust phases electronically and hence is very popular for phased array antenna applications where radiation angle can be scanned electronically avoiding bulky mechanical rotation arrangement. In this research a variable gain phase shifter was investigated, capable of controlling precisely both phase and gain simultaneously. The phase shifter was fabricated using 0.18um CMOS process and the measured results showed continuous phase shift of 3030 with 9-dB variable gain at 3.5 GHz. Based on the measured results, a modified phase shifter was proposed and designed which can achieve continuous phase rotation of 3600 with small 22.50 steps, a low RMS phase error of 20 providing high resolution, a very high conversion gain of 14.2 dB with dynamic gain control range of 20 dB. These performances will create a potential future for smart communication radar applications where both beamforming and nulling can be achieved.ND NASA EPSCoR under the agreement FAR0020852
25
Zhou, Hao. "Numerical Investigation of the Nonlinear Dynamics of a Hybrid Acousto-Optic Bragg Cell with a Variable Feedback Gain." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1406666390.
26
Mimeche, Naamane. "Conception assistée par ordinateur de circuits translinéaires analogiques à gain controlé et applications au filtrage." Châtenay-Malabry, Ecole centrale de Paris, 1994. http://www.theses.fr/1994ECAP0343.
Abstract:
Plusieurs configurations pour des circuits miroirs de courant avec courant de sortie contrôlé en courant sont comparées. Les circuits convoyeurs de courant à gain contrôlé du premier et du second type qui s'en déduisent permettent la réalisation d'amplificateurs contrôlés et de filtres réglables. Deux exemples sont étudiés. Divers circuits amplificateurs opérationnels de transconductance (OTA) avec courants de sortie en opposition de phase, mis en œuvre à partir d'éléments translinéaires, sont étudiés et comparés à la réalisation conventionnelle. Un macromodèle amélioré relatif à ces circuits, qui prend entre autre en compte la non-linéarité de la transconductance, la modification de l'entendue de la bande passante liée à la variation du courant de polarisation et l'effet de la température, est décrit. Plusieurs filtres actifs du second ordre réglables, opérant en mode tension ou en mode courant et conçus à partir des amplificateurs de transconductance précédents sont étudiés. L'incidence des différents éléments parasites sur les réponses en fréquence y est analysée. Les règles de passage qui permettent de transformer un circuit avec convoyeurs de courant en la topologie équivalente avec amplificateurs de transconductance et vice-versa, sont établies. Deux exemples qui illustrent ces transformations sont examinés. La simulation électrique, utilisant les paramètres SPICE associés aux transistors des réseaux bipolaires prédiffusés ALA200 de la societe ATT, a été utilisée pour caractériser les différents circuits
27
Häkkinen, J. (Juha). "Integrated RF building blocks for base station applications." Doctoral thesis, University of Oulu, 2003. http://urn.fi/urn:isbn:951426908X.
Abstract:
Abstract
This thesis studies the level of performance achievable using today's standard IC processes in the integrated RF subcircuits of the modern GSM base station. The thesis concentrates on those circuit functions, i.e. I/Q modulators, variable gain amplifiers and frequency synthesizers, most relevant for integration in the base station environment as pinpointed by studying the receiver/transmitter architectures available today.
Several RF integrated circuits have been designed, fabricated and their level of performance measured. All main circuits were fabricated in a standard double-metal double-poly 1.2 and 0.8 μm BiCMOS process. Key circuit structures and their measured properties are: 90° phase shifter with ±1° phase error with VCC = 4.5…5.5 V and T = -10…+85 °C, I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz (2.0 mm × 2.0 mm, 100 mA, 5.0 V) with LO suppression of 38 dBc and image rejection of 41 dBc, temperature compensated DC to 1.5 GHz variable gain amplifier (1.15 mm × 2.00 mm, 100 mA, 5.0 V) with a linear 50 dB gain adjustment range, maximum gain of 18.5 dB and gain variation of 1 dB up to 700 MHz over the whole operating conditions range of VCC = 4.5…5.5 V and T = -10…+85 °C, a complete bipolar semicustom synthesizer (90…122 mA, 5.0 V) and two complete full-custom BiCMOS synthesizer chips including all building blocks of a PLL-based synthesizer except for the voltage controlled oscillator and the loop filter. The synthesizers include circuit structures such as ∼2 GHz multi-modulus divider and low-noise programmable phase detector/charge pump (18.7 pA/√Hz at Iout = 500 μA) and have an exemplar phase noise performance of -110 dBc/Hz at 200 kHz offset.
One of the main problems of the integer-N PLL based synthesizer when used in a multichannel telecommunications system is the level of spurious signals at the output, when the synthesizer is optimised for fast frequency switching. Therefore, a method using only two current pulses to make the frequency step response of the loop faster, thus allowing a narrower loop bandwidth to be used for additional spur suppression, is proposed. The operation of the proposed speed-up method is analysed mathematically and verified by measurements of an existing RF-IC synthesizer operating at 800 MHz. Measurements show that simple current pulses can be used to speed up the channel switching of a practical RF synthesizer having a frequency step time in the tens of μs range. In the example, a 7.65 MHz frequency step was made seven times faster using the proposed method.
28
PATEL, PRERNA D. "DESIGN OF A PIXEL SCALE OPTICAL POWER METER SUITABLE FOR INCORPORATION IN A MULTI-TECHNOLOGY FPGA." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1066421274.
29
Lind, Fredrik, and Escalante Andrés Diaz. "Maximizing performance gain of Variable Rate Shading tier 2 while maintaining image quality : Using post processing effects to mask image degradation." Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-21868.
Abstract:
Background. Performance optimization is of great importance for games as it constrains the possibilities of content or complexity of systems. Modern games support high resolution rendering but higher resolutions require more pixels to be computed and solutions are needed to reduce this workload. Currently used methods include uniformly lowering the shading rates across the whole screen to reduce the amount of pixels needing computation. Variable Rate Shading is a new hardware supported technique with several functionality tiers. Tier 1 is similar to previous methods in that it lowers the shading rate for the whole screen. Tier 2 supports screen space image shading. With tier 2 screen space image shading, various different shading rates can be set across the screen which gives developers the choice of where and when to set specific shading rates. Objectives. The aim of this thesis is to examine how close Variable Rate Shading tier 2 screen space shading can come to the performance gains of Variable Rate Shading tier 1 while trying to maintain an acceptable image quality with the help of commonly used post processing effects. Methods. A lightweight scene is set up and Variable Rate Shading tier 2 methods are set to an acceptable image quality as baseline. Evaluation of performance is done by measuring the times of specific passes required by and affected by Variable Rate Shading. Image quality is measured by capturing sequences of images with no Variable Rate Shading on as reference, then with Variable Rate Shading tier 1 and several methods with tier 2 to be compared with Structural Similarity Index. Results. Highest measured performance gains from tier 2 was 28.0%. The result came from using edge detection to create the shading rate image in 3840x2160 resolution. This translates to 36.7% of the performance gains of tier 1 but with better image quality with SSIM values of 0.960 against tier 1’s 0.802, which corresponds to good and poor image quality respectively. Conclusions. Variable Rate Shading tier 2 shows great potential in increasing performance while maintaining image quality, especially with edge detection. Postprocessing effects are effective at maintaining a good image quality. Performance gains also scale well as they increase with higher resolutions.Bakgrund. Prestandaoptimering är väldigt viktigt för spel eftersom det kan begränsa möjligheterna av innehåll eller komplexitet av system. Moderna spel stödjer rendering för höga upplösningar men höga upplösningar kräver beräkningar för mera pixlar och lösningar behövs för att minska arbetsbördan. Metoder som för närvarande används omfattar bland annat enhetlig sänkning av skuggningsförhållande över hela skärmen för att minska antalet pixlar som behöver beräkningar. Variable Rate Shading är en ny hårdvarustödd teknik med flera funktionalitetsnivåer. Nivå 1 är likt tidigare metoder eftersom skuggningsförhållandet enhetligt sänks över hela skärmen. Nivå 2 stödjer skärmrymdsbildskuggning. Med skärmrymdsbildskuggning kan skuggningsförhållanden varieras utspritt över skärmen vilket ger utvecklare valmöjligheter att bestämma var och när specifika skuggningsförhållanden ska sättas. Syfte. Syftet med examensarbetet är att undersöka hur nära Variable Rate Shading nivå 2 skärmrymdsbildskuggning kan komma prestandavinsterna av Variable Rate Shading nivå 1 samtidigt som bildkvaliteten behålls acceptabel med hjälp av vanligt använda efterbearbetningseffekter. Metod. En simpel scen skapades och metoder för Variable Rate Shading nivå 2 sattes till en acceptabel bildkvalitet som utgångspunkt. Utvärdering av prestanda gjordes genom att mäta tiderna för specifika pass som behövdes för och påverkades av Variable Rate Shading. Bildkvalitet mättes genom att spara bildsekvenser utan Variable Rate Shading på som referensbilder, sedan med Variable Rate Shading nivå 1 och flera metoder med nivå 2 för att jämföras med Structural Similarity Index. Resultat. Högsta uppmätta prestandavinsten från nivå 2 var 28.0%. Resultatet kom ifrån kantdetektering för skapandet av skuggningsförhållandebilden, med upplösningen 3840x2160. Det motsvarar 36.7% av prestandavinsten för nivå 1 men med mycket bättre bildkvalitet med SSIM-värde på 0.960 gentemot 0.802 för nivå 1, vilka motsvarar bra och dålig bildkvalitet. Slutsatser. Variable Rate Shading nivå 2 visar stor potential i prestandavinster med bibehållen bildkvalitet, speciellt med kantdetektering. Efterbearbetningseffekter är effektiva på att upprätthålla en bra bildkvalitet. Prestandavinster skalar även bra då de ökar vid högre upplösningar.
30
Chen, Yun-ju, and 陳韻如. "Design of CMOS Variable Gain Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/47315197247618226962.
Abstract:
碩士逢甲大學
電子工程所
97
A CMOS variable gain amplifier （VGA） is presented, which consists of exponential control circuit, amplifier circuit and buffer circuit. The exponential control circuit adopts an approximate exponential equation. The amplifier circuit includes a common mode feedback circuit, the common mode feedback is required in order to prevent any of the transistors from entering linear mode operation and to maintain a specific dc value for the biasing of the next stage. The VGA is implemented in 0.35um CMOS technology and total power dissipation is 58mW at 3.3V supply. The chip size is 0.93mm2.
31
Wu, Wei-ruen, and 吳威潤. "Voltage-Controlled Variable-Gain Optical Receiver." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/78197469140607056041.
Abstract:
碩士國立雲林科技大學
電子與資訊工程研究所
99
A Voltage-controlled variable-gain optical receiver for optical wireless communication is described. Under a photodiode capacitance of 5pF, the transimpedance gain, bandwidth, and power consumption of the optical receiver are 77dBΩ, 103MHz, and 34 mW respectively. A CMOS voltage-control resistor is adopted in the feedback transimpedance amplifier. The receiver is designed and implemented using a 0.35μm 2P4M CMOS technology with 3.3V supply voltage. The final implementation occupies a total area of 825um × 666um.
32
Lai, Bing-Jiun, and 賴炳均. "Integrated Radio Frequency Variable Gain Amplifier." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/79487323239286597680.
Abstract:
碩士國立中正大學
電機工程所
96
The first stage of a receiver is typically a low noise amplifier, whose main features are to provide enough gain and minimize the influence to subsequent stages due to the noise generated in itself. In general, variable gain amplifier is employed for automatic gain control, which is used for automatically adjusting gain of the receiver path, so that the received RF signal can be easily processed by subsequent circuits. The requirements for the tuner front-ends are low power consumption, dB-linear, dynamic range, linearity and gain performance. The first part of this thesis is devoted itself abut the variable gain amplifier which was manufactured by the TSMC 0.18 μm CMOS process. It is applied to WiMAX system. The first one is the variable gain low noise amplifier in which the differential topology being used due to its inherent feature of low interference. The second is the variable gain amplifier, which is addressed on the high tunable gain range. It can be use in the transmitter just before the power amplifier or used in receiver after the low noise amplifier. The second part of this thesis is the wideband variable gain low noise amplifier which was fabricated by a standard TSMC 0.35 μm SiGe BiCMOS technology. In order to improve the bandwidth, two types of feedback are employed, and then using the Darlington pair to double the cutoff frequency.
33
Liu, Hung-Hsi, and 劉洪禧. "FPGA implements variable gains control of the variable gain amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/01974566430523855947.
Abstract:
碩士中原大學
電子工程研究所
97
Field Programmable Gate Array (FPGA) can be used to implement complex logic function and provide rapid field re-programmable ability in a single chip design application. This thesis describes the use of hardware design language Verilog and the implementation of a variable gain controller in a Variable Gain Amplifier. A top-down methodology is applied in this design to make the design clearer and easier for maintenance. A look up table (LUT) mechanism is applied to realize faster computing and simplify the design complexity. The design is simulated by Modelsim and implemented by Altera FPGA EP1C6.
34
Wang, Lin-Sen, and 王林森. "Designs of CMOS Variable Gain Amplifiers for Wide-Gain-Range Applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/t67e96.
Abstract:
碩士國立臺灣大學
電子工程學研究所
105
Several gain control mechanisms for the design of programmable gain amplifier (PGA) and variable gain amplifier (VGA) are presented in this thesis. In RF wireless receivers, an accurate decibel (dB)-linear PGA or VGA is required to convert the dynamic range of received signal into an acceptable range for the analog-to-digital converter (ADC). Several variable gain amplifier architectures and exponential-approximation functions are discussed and analyzed in this thesis. In order to obtain a wide dB-linear gain range, a cascading gain-error-shifting and a single-stage gain-shifting technique are proposed and adopted in the PGA and VGA, respectively. Both PGA and VGA are fabricated in the 0.18-μm CMOS process for comparison. The cascading PGA can achieve a small gain error characteristic, while the single-stage VGA can provide a better area and power performance.
35
Ko, Po-Ting, and 柯柏廷. "Designs of CMOS Variable Gain Amplifiers for Low-Gain-Error Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bknnkc.
Abstract:
碩士國立臺灣大學
電子工程學研究所
107
Several gain control mechanisms for the design of programmable gain amplifier (PGA) and variable gain amplifier (VGA) are presented in this thesis. In wireless communication systems, the received signal changes significantly. Therefore, an accurate decibel (dB)-linear PGA or VGA is required to convert the dynamic range of received signal into an acceptable range for the analog-to-digital converter (ADC). Several variable gain amplifier architectures and exponential-approximation functions are discussed and analyzed in this thesis. In order to obtain the characteristics of wide dB-linear gain range and small gain error, the gain-range-compensating technique and a pseudo-exponential approximation method are proposed and adopted in the cascading PGA and the single-stage VGA, respectively. Both PGA and VGA are fabricated in the 0.18-μm CMOS process. The cascading PGA occupies an area of 0.08 mm2, consuming a dc power of 3.83 mW. A gain range of 69.9 dB with 0.21 dB gain error is achieved. The 3-dB bandwidth is measured from 19 MHz to 315 MHz in the maximum and minimum gain setting, respectively. The single-stage VGA occupies an area of 0.035 mm2. The power consumption of the core circuit is 0.92 mW. A gain range of 40.2 dB with 0.35 dB gain error is achieved. The 3-dB bandwidth is measured from 20.9 MHz to 240 MHz in the maximum and minimum gain setting, respectively.
36
Chen, Hsin-Hao, and 陳信豪. "Variable Gain Amplifier for Ultrasound Imaging Receiver." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/26783570570803995937.
37
陳東山. "Radio frequency heterojunctio bipolar transistor variable frequency oscillator and variable gain amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/93466629235737130612.
Abstract:
碩士國立中興大學
電機工程學系
91
Fabricated through a GaInP/GaAs HBT technology, a monolithic variable frequency oscillator (VFO) and a monolithic variable gain amplifier (VGA) were measured and reported in this thesis. A number of issues on the VFO and VGA were detailed as well. A new circuitry, called a Variable Impedance Converter (VIC), was adopted to mimic a variable capacitor, which was essentially an important element for frequency tuning in a LC-based oscillator design.A negative-impedance converter not only provides the necessary negative resistance for oscillation, but also functions as the voltage level shifters for the VIC. A classic circuit, called a translinear circuit, makes full advantage of the exponential I-V characteristic to linearize the tuning curve of the VFO. No external but two on-chip inductors were used in the VFO. Several operating principles for a VGA were explored in the VGA chapter. Based these principles we discussed, a wide gain control range VGA was achievable. The designed VGA consisted of a fixed gain preamplifier, a variable attenuator, and a tunable transconductance common-emitter (CE) amplifier, in which the input impedance is also controllable by a voltage controlled resistor. Therefore, by cleverly composing these functions of the controllable components, a low noise VGA with 50dB gain control range result.
38
Liu, Bang-Zhi, and 劉邦志. "Implementation of 6-Bit Digital control Variable Gain Amplifier with High Linear Gain." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/40855833975865745996.
Abstract:
碩士中華大學
電機工程學系碩士班
102
The propose of this thesis is to design and implement the circuits of a Digital control Variable Gain Amplifier with High Linear Gain. We use HSPICE and MATLAB for circuit simulation and analysis. Circuit layout is used the Laker which provided by CIC. The Chip is fabricated by TSMC 0.18 um CMOS process. In this thesis, the variable gain amplifier is divided into two parts: Amplifier circuit and control circuit. The amplifier circuit is designed by exponential function which approximated by second order Taylor’s polynomial. The control circuit is designed by one set of segmentation control circuit. The amplifier circuit is designed by four sets of second order Taylor’s polynomial circuit at different input points and one set of segmentation control circuit. The simulated result is based on the input range of -10μA to 10μA, the power supply of 1.8V and the linear gain error within±0.5dB. The linear gain range is 108dB, the bandwidth is 37MHz to 268MHz, the power consumption is from 7.8mW to 10.1mW and the area of chip is 0.432*0.32(mm2).
39
Tsou, Shan-Chih, and 鄒善智. "CMOS Variable Gain Amplifier for Multi-Standard Receiver." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/31899508987093420198.
Abstract:
碩士國立清華大學
電機工程學系
92
With the rapid growth of higher data rate, integrating the analog circuit block with wide bandwidth in the baseband will be an indispensable trend in the future. On the other hand, a single circuit block which can be used for multi-standard receiver is an economic implementation way to enhance the usability of the cell phone. A CMOS variable gain amplifier (VGA) for multi-standard receiver described in this thesis aims to meet these two demands. In general, VGA is controlled by an automatic gain control (AGC) loop. As the data rate increases, the data slot which is used for the AGC loop to settle is getting smaller. A fast gain settling of the AGC loop becomes more and more important to make sure the data transfer is correct. The performance of the AGC loop can be characterized not only by a fast gain settling, but also the precise gain settling, the stable gain settling, and a low-distortion output signal. Alinear model of the AGC loop is set up and simulated with the performance of VGA modeled as the proposed one to see the dynamics of the loop. In this thesis, a proposed VGA for the multi-standard receiver is analyzed, designed, and implemented using the standard 0.18um 1P6M CMOS technology. The output signal of the VGA can be of constant signal level and contant group delay. The bandwidth of the VGA is extended from GSM 100KHz, WCDMA 2MHz to WLAN 10MHz, and designed to be adjustable for the noise and linearity concern of the total architecture. The gain of tha VGA ranges from -10dB to 20dB, and the constant bandwidth peroperty with different gain settings helps the simplification of DSP circuitry in the baseband. The total power consumption of the VGA is 2.43mW at 1.8V supply voltage. The chip area is 0.645mm x 0.465mm.
40
Song, Guang-Fong, and 宋光峰. "The Design of A Variable Gain Instrumentation Amplifier." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/24520553586227143218.
Abstract:
碩士中原大學
電子工程學系
87
A variable gain instrumentation amplifier (IA) has been designed in this thesis. Buffered two-stage operational amplifier and poly resistors construct the core of the instrumentation amplifier. In order to obtain good amplifier performance, the circuit configuration of the IA and its output stage, the offset and noise effects have been analyzed and investigated in this thesis. We also present key layout methods such as common-centroid structure, dummy device and guard-ring option for differential input transistor pair, compensated capacitor and poly resistors. Full custom design flow has been used in the instrumentation amplifier design. The circuit has been integrated in a 0.5mm double poly double metal n-well CMOS process. In this research, several characterization methods have been developed to measure instrumentation amplifier. In order to assure the measurements, the commercial IA device has been also tested in this research. The test results show that the proposed IA has a variable gain of 0 dB to 40dB and a common-mode rejection ratio (CMRR) of more than 85dB. The minimum input offset voltage of less than 1mV has been measured. The amplifier has an acceptable die size of 810×400mm2 and its power consumption is 13mW at 5V operation.
41
Hu, Yun-Chung, and 胡運忠. "Low Power Variable Gain Amplifier for UWB systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/13040808438308906179.
Abstract:
碩士中原大學
電子工程研究所
95
The booming development of the wireless communication technology in recent years make the relevant products, such as GSM, CDMA, Bluetooth, 802.11 (Wi-Fi), ZigBee and Ultra wide band (UWB) widely used in our daily life and became important research topics. This thesis proposes a Variable Gain Amplifier (VGA) that is suitable for UWB system. It consists of a main amplifier, gain control circuit, and a common mode feedback loop. The main amplifier is realized by a folded cascode amplifier with feedback and the gain control function is utilized by a source-coupled pair to realize controllable gain. A modified pseudo-exponential equation is proposed to improve the linearity of the proposed VGA. The circuit is designed and simulated in TSMC 0.18um CMOS process. The gain range of 18dB and the 3dB frequency of 610MHz at the maximum gain that meets the specification of UWB system is obtained. The power dissipation is less then 2mW at 1.8V supply voltage.
42
Lee, Jun-Yi, and 李俊億. "Design of a variable-gain CMOS Optical Receiver." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/03963634580322183010.
Abstract:
碩士國立雲林科技大學
電子與光電工程研究所碩士班
100
A Voltage-controlled variable-gain optical receiver for optical wireless communication is described. A stable variable-gain fully-differential transimpedance feedback amplifier is designed employing a current-mode amplifier as the feedforward gain element. Using a photodiode capacitance of 5pF, the transimpedance gain, bandwidth, and power consumption of the optical receiver are 98dBΩ, 119MHz, and 88mW respectively. A voltage-control resistor is adopted in the feedback transimpedance amplifier. The receiver is designed and implemented using a 0.35μm 2P4M CMOS technology with 3.3V supply voltage. The optical receiver occupies a total chip area of 566um × 655um.
43
Chen, Sz-Han, and 陳思涵. "A 1.5-GHz Variable-Gain Amplifier and Filter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3kjgaf.
Abstract:
碩士國立交通大學
電子研究所
108
For the fifth generation (5G) communication system, we use variable gain amplifier (VGA) to amplifier the baseband signal at receiver and use filter to filter out noise and any other signals which are not in the signal band. After that, we use analog-to-digital converter (ADC) to convert analog signal to digital signal for digital circuits and complete the baseband front-end receiver circuit of the fifth generation communication system. This paper is about VGA and filter. ar Due to the specification of bandwidth is wider in the fifth generation communication system, we use Gm-Miller-C filter instead of switch-capacitor filter and active-RC filter to reach the specification. The Gm-Miller-C filter is more suitable for high speed system, but the main disadvantage is the worse linearity. It is the most important part for us to improve the linearity. ar The VGA structure is based on the design of Gm-Miller-C filter and we can change the value of resistors to get programmable voltage gain. We applied the VGA and Gm-Miller-C filter as a third-order baseband chain in the fifth generation communication system and get 1.5625 GHz -3dB frequency also we can change the voltage gain from 8 dB to 40 dB for each 1 dB step. Also, we use DC-offset cancellation technique with negative feedback topology. Comparing the positive and negative output voltage and feedback to the first stage after amplifier the mismatch to reduce the impact of offset. ar This design use TSMC 28 nm CMOS process and the layout area is 198.07 x 90.88 um$^{2}$. the main circuit operate at 1 V and 1.5 V for the last stage to meet the output swing of +/- 400 mV. For the input signal bandwidth is from 5 MHz to 1.5625 GHz and input swing is +/- 150 mV, we can get SFDR is more than 47 dB, SNDR is more than 36 dB and THD is more than -38 dB. The whole design consumes 48 mW.
44
Yang, Hui-Chen, and 楊蕙甄. "A Short-Channel Variable Gain Amplifier with DC Offset Cancellation and Gain Calibration Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/63026791132656734491.
Abstract:
碩士國立清華大學
電機工程學系
98
In this thesis, a short-channel variable gain amplifier with digital feedback loops is proposed. For the purpose of area saving, the entire work is implemented with minimum gate length CMOS devices. This results in severe circuit process variations. To overcome this problem, two digital feedback loops are needed for the DC offset cancellation and gain calibration. The VGA circuit is based on a fully-differential gain stage with a degeneration resistor network. The resistance of this resistor network is digitally controlled to provide enough gain range and resolution. To properly set the VGA gain, the digital gain calibration loop is enabled before the VGA operates. The DC offset cancellation loop is always active to prevent the VGA output from DC saturation. With the aid of both loops, the proposed VGA is robust against process variations. An experimental chip is fabricated in TSMC 0.18-μm 1P6M CMOS process. The core area occupies 292 μm × 592 μm. The available gain range of the VGA is -3.9 ~ 48.3 dB. For a 6-dB gain step requirement, the gain error is less than 0.5 dB. The bandwidth at the maximum gain setting is 10.85 MHz. With 10-MHz 400-mVppd sinusoidal output waveform, the total harmonic distortion (THD) at maximum and minimum gain setting are -33.82 dB and -48.08 dB respectively. The output DC offset voltage is less than 20 mV when the input DC offset voltage is within -70 ~ +50 mV. The current consumption from a single 1.8-V power supply is 12.1 mA.
45
Krstic, Marko. "An Optimized, Variable-Gain Switched-Capacitor DC-DC Converter." Thesis, 2013. http://hdl.handle.net/1974/7868.
Abstract:
A novel, variable-gain switched-capacitor DC-DC converter is designed, constructed and tested. The proposed converter minimizes many of the problems which have traditionally hindered switched-capacitor DC-DC converters. The converter has high efficiency, strong regulation and low output voltage ripple across a wide variation in the line and load. The converter utilizes an optimized switching configuration that contains the maximum number of ideal conversion ratios for the given number of capacitors driven by a two-phase clock. The switched-capacitor converter is controlled by a gain-hopping feedforward control scheme in conjunction with duty-cycle, pulse-width modulation feedback control. The proposed control technique enhances the efficiency and regulation capability of switched-capacitor DC-DC converters, which are typically limited when there is a large variation in the line. Because the converter is optimized, programmable and capable of providing buck and/or boost operation (stepping-up and/or stepping-down the input voltage), the new switched-capacitor DC-DC converter is well-suited for a variety of applications and operating conditions.
In addition, a novel algorithm based on graph theory and network analysis is developed which enumerates all possible ideal conversion ratios for a given switched-capacitor DC-DC converter structure. In particular, this algorithm can be used as a design tool to greatly improve the operation of multi-gain switched-capacitor converters, where the aim is to maximize the number of ideal conversion ratios while minimizing the number of switches and capacitors.
Furthermore, the structure of all attainable positive, ideal conversion ratios of a two-phase switched-capacitor DC-DC converter, utilizing up to five capacitors, is enumerated. As a result, the design process for switched-capacitor converters is greatly simplified and a suitable converter structure can be more easily selected for a given application.Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-04-03 23:27:24.183
46
Chen, Chia-Jung, and 陳佳蓉. "Investigation of a variable-gain circuit for hydrogen detector." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/92400931422928360611.
Abstract:
碩士朝陽科技大學
資訊工程系碩士班
97
In this thesis, a 3×3 gas sensors array with on chip multiple input integrated circuitry by using microelectromechanical system (MEMS) was fabricated. Hydrogen sensors fabricated with different structures can be measured simultaneously. The hydrogen sensing chip has two advantages. First, the structure of the array has a cantilever beam, it can prevent the hot effect. Second the fabrication can consistent with CMOS technology. It’s easy to measure and analysis by using the chip with variable-gain.Traditionally, the hydrogen sensing device and the sensing chip were divided. It will restrict the application due to the noise at the interface between the device and chip. Our device integrate the hydrogen sensing device and sensing circuit on the same chip. Palladium (Pd) is selected as the catalytic metal. Further more in contrast to the conventional amplifier, using resistance-ratio, our design amplifier base on capacitance-ratio can prevent the influence of fabrication parameters. The DC offset also can be improved. Finally, the designed circuit has the advantages of low cost and low power consumption.
47
Lin, Yi-Chen, and 林宜蓁. "CMOS Dual-Band Constant-IF-Bandwidth Variable Gain Up-Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/97256719958668456921.
Abstract:
碩士國立交通大學
電信工程系所
96
In this thesis, we focus on Radio Frequency Integrated Circuits. We combine IF variable gain amplifier with up-converter by using a new modified V-to-I transconductor stage, therefore, both frequency up-conversion and variable-gain amplification are achieved by using current-mode operation in a single chip. We implement several variable gain up-converter with constant IF bandwidth for WLAN and UWB communication systems by using TSMC 0.18μm CMOS technology and TSMC 0.35μm SiGe BiCMOS technology. Moreover, in order to do multi-band multi-mode signal processing by a single chip, we also implement a CMOS dual-band (2.4/5.7GHz) variable gain up-converter with constant IF bandwidth for IEEE 802.11a/b/g applications.
48
Hung, Chia-Cheng, and 洪家正. "A Low Voltage, Variable Gain Design for Low Noise Amplifier." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/15654715837525270170.
Abstract:
碩士長庚大學
電子工程研究所
92
In the thesis, an integrated RF circuit topology that can be used to realize low voltage ( i.e. 1V ) low noise amplifier is presented. The design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated circuits. Based on a LC-folded cascode LNA topology, it is implemented with a modified LC-folded cascode LNA configuration using two common source transistors to improve linearity. The linearity is improved about 2 to 3 dB. On LC-folded cascode topology, another merit that only increases in the LNA circuit complexity is an extra gain control signal, Vtune. Gain variation is achieved by controlling the Vtune, hence adjusting the overall gain of the LNA without affecting the input noise and impedance matching. The technique is applied to the design of a proposed LNA operating at 2.4 GHz using a TSMC 0.18 μm mixed signal ( 1P6M ) CMOS technology. A low voltage, variable gain design for low noise amplifier is fully on chip between input and output. The proposed LNA chip achieves measured results of 11.14 dB for power gain, 3.981 dB for noise figure, the input and output return loss of -26.06 dB and -6.827 dB, the 1-dB compression point and IIP3 of -14 dBm and -5 dBm, respectively. The circuit has 10 dB of gain tuning, and can operate at a low supply voltage of 1 V.
49
Wang, Po-Sheng, and 王柏勝. "Design of Variable-Gain Low-Noise Amplifiers in CMOS Technology." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/46392548950397376660.
Abstract:
碩士國立中正大學
電機工程所
98
This thesis presents three enhanced CMOS low-noise amplifiers (LNA). First, a differential wideband low-noise amplifier was designed by using a shunt-shunt feedback in 0.18-μm CMOS technology. The measured power gain is 8.1?0.6 dB and noise figure is 3.5?0.3 dB in 2.3–4 GHz. The 3-dB gain bandwidth is 1–4.2 GHz. The input return losses is greater than 10.4 dB. The measured input 1-dB-compressed power is -8.8 dBm and input-referred third-order intercept (IIP3) is 0 dBm at 3 GHz. The power consumption is 19.8 mW from a 1.8 V supply. The second design is a wideband inductor-less low-noise amplifier with tunable power gain in 0.18-μm CMOS technology. The 3-dB gain bandwidth is 0.7–3.58 GHz. The power consumption is 25.2 mW from a 1.8 V supply. The measured power gain is 14.7?2.3 dB and noise figure is 3.3?0.6 dB. The input return losses is larger than 10.1. The input 1-dB-compressed power is -13.8 dBm and input-referred third-order intercept (IIP3) is -6 dBm at 3 GHz. The gain tuning range is from -2.5 to 16 dB at 3 GHz. The last design is a gm-boosted variable-gain low-noise amplifier in 0.18-μm CMOS technology. The simulation power gain is 10.13–12.91 dB and a noise figure of 3.16–3.45 dB at 3.5 GHz. The input return is greater than 14.0 dB. The simulation input 1-dB-compressed power is -20.3 dBm and input-referred third-order intercept (IIP3) is -12.2 dBm. The gain tuning range is from -1.27 dB to 12.79 dB. The power consumption is 3.4 mW from 1.2 V.
50
洪德儒. "A Variable-Gain 0.35um SiGe 5.25GHz RF Front-End Integrated Circuit." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/66180291387058812835.