Relevant bibliographies by topics / Algorithm co-design

Academic literature on the topic 'Algorithm co-design'

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Published: 10 December 2022
Last updated: 29 January 2023

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Journal articles on the topic "Algorithm co-design"

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Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (October 18, 2018): 122. http://dx.doi.org/10.3390/jimaging4100122.

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Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images.
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Drumond, Mario, Alexandros Daglis, Nooshin Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi, Boris Grot, and Dionisios Pnevmatikatos. "Algorithm/Architecture Co-Design for Near-Memory Processing." ACM SIGOPS Operating Systems Review 52, no. 1 (August 28, 2018): 109–22. http://dx.doi.org/10.1145/3273982.3273992.

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Li, Min, Frederico Guimarães, and David A. Lowther. "Competitive co-evolutionary algorithm for constrained robust design." IET Science, Measurement & Technology 9, no. 2 (March 1, 2015): 218–23. http://dx.doi.org/10.1049/iet-smt.2014.0204.

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López, M., J. Daugman, and E. Cantó. "Hardware–software co-design of an iris recognition algorithm." IET Information Security 5, no. 1 (2011): 60. http://dx.doi.org/10.1049/iet-ifs.2009.0267.

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Li, Shih-An, Chen-Chien Hsu, Ching-Chang Wong, and Chia-Jun Yu. "Hardware/software co-design for particle swarm optimization algorithm." Information Sciences 181, no. 20 (October 2011): 4582–96. http://dx.doi.org/10.1016/j.ins.2010.07.017.

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Krawczyk, Kamil, Paweł Tomaszewicz, and Mariusz Rawski. "Whirlpool SoPC Implementation - Hardware/Software Co-Design Example." International Journal of Electronics and Telecommunications 58, no. 1 (March 1, 2012): 21–26. http://dx.doi.org/10.2478/v10177-012-0003-9.

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Whirlpool SoPC Implementation - Hardware/Software Co-Design Example The aim of this work was to design a System on Programmable Chip (SoPC), that implements the Whirlpool Hash Function (WHF) algorithm. An assumption of the project was to use an embedded soft-processor NIOS II controlling the whole system, which functionality was extended by a custom logic in order to improve the used algorithm efficiency. This paper presents the Whirlpool Hash Function realized in several SoPC configurations, which differ in implementation complexity and performance.
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Byun, Kwang-Sub, Chang-Hyun Park, and Kwee-Bo Sim. "Co-Evolution of Fuzzy Controller for the Mobile Robot Control." Journal of Advanced Computational Intelligence and Intelligent Informatics 8, no. 4 (July 20, 2004): 356–61. http://dx.doi.org/10.20965/jaciii.2004.p0356.

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In this paper, we design the fuzzy rules using a modified Nash Genetic Algorithm. Fuzzy rules consist of antecedents and consequents. Because this paper uses the simplified method of Sugeno for the fuzzy inference engine, consequents have not membership functions but constants. Therefore, each fuzzy rule in this paper consists of a membership function in the antecedent and a constant value in the consequent. The main problem in fuzzy systems is how to design the fuzzy rule base. Modified Nash GA coevolves membership functions and parameters in consequents of fuzzy rules. We demonstrate this co-evolutionary algorithm and apply to the design of the fuzzy controller for a mobile robot. From the result of simulation, we compare modified Nash GA with the other co-evolution algorithms and verify the efficacy of this algorithm.
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Raghunathan, Shriram, Sumeet K. Gupta, Himanshu S. Markandeya, Kaushik Roy, and Pedro P. Irazoqui. "A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications." Journal of Neuroscience Methods 193, no. 1 (October 2010): 106–17. http://dx.doi.org/10.1016/j.jneumeth.2010.08.008.

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Alecsa, Bogdan, and Alexandru Onea. "Hardware-Software Co-Design for BLDC Motor Speed Controller Design." Advanced Materials Research 463-464 (February 2012): 1256–59. http://dx.doi.org/10.4028/www.scientific.net/amr.463-464.1256.

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This paper proposes a combined hardware-software approach for a controller design. The case of a brushless DC (BLDC) motor speed controller is studied. A hardware controller is implemented inside a field programmable gate array (FPGA) device, together with soft core processors that implement by software non-critical tasks, like liquid crystal display (LCD) interface and serial data communication to a host computer. This way, the control algorithm is executed in hardware, as fast as possible, while the monitoring tasks are performed by the software. Experimental results are provided, showing the working design.
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Benxian Yue, Yishou Wang, Yanjun Shi, and Hongfei Teng. "Satellite Payloads Configuration and Layout Design Using Co-evolutionary Algorithm." International Journal of Advancements in Computing Technology 3, no. 11 (December 31, 2011): 223–30. http://dx.doi.org/10.4156/ijact.vol3.issue11.28.

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Dissertations / Theses on the topic "Algorithm co-design"

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Zhang, Zhengdong Ph D. Massachusetts Institute of Technology. "Efficient computing for autonomous navigation using algorithm-and-hardware co-design." Thesis, Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/122691.

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This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 211-221).
Autonomous navigation algorithms are the backbone of many robotic systems, such as self-driving cars and drones. However, state-of-the-art autonomous navigation algorithms are computationally expensive, requiring powerful CPUs and GPUs to enable them to run in real time. As a result, it is prohibitive to deploy them on miniature robots with limited computational resources onboard. To tackle this challenge, this thesis presents an algorithm-and-hardware co-design approach to design energy-efficient algorithms that are optimized for dedicated hardware architectures at the same time. It covers the design for three essential modules of an autonomous navigation system: perception, localization, and exploration.
Compared with previous research that considers either algorithmic improvements or hardware architecture optimizations, our approach leads to algorithms that not only have lower time and space complexity but also map efficiently to specialized hardware architectures, resulting in significantly improved energy efficiency and throughput. First, this thesis studies how to design an energy-efficient visual perception system using the deformable part models (DPM) based object detection algorithm. It describes an algorithm that enforces sparsity in the data stored on a chip, which reduces the memory requirement by 34% and lowers the cost of the classification by 43%. Together with other hardware optimizations, this technique leads to an object detection chip that runs at 30 fps on 1920 x 1080 videos while consuming only 58.6mW of power.
Second, this thesis describes a systematic way to explore algorithm-hardware design choices to build a low-power chip that performs visual inertial odometry (VIO) to localize a vehicle. Each of the components in a VIO pipeline has multiple algorithmic choices with different time and space complexity. However, some algorithms of lower time complexity can be more expensive when implemented on-chip. This thesis examines each of the design choices from both the algorithm and hardware's point of view and presents a design that consumes 24mW of power while running at up to 90 fps and achieving near state-of-the-art localization accuracy Third, this thesis presents an efficient information theoretic mapping system for exploration. It features a novel algorithm called Fast computation of Shannon Mutual Information (FSMI) that computes the Shannon mutual information (MI) between perspective range measurements and the environment.
FSMI algorithm features an analytic solution that avoids the expensive numerical integration required by the previous state-of-the-art algorithms, enabling FSMI to run three orders-of-magnitude faster in practice. We also present an extension of the FSMI algorithm to 3D mapping; the algorithm leverages the compression of a large 3D map using run-length encoding (RLE) and achieves 8x acceleration in a real-world exploration task. In addition, this thesis presents a hardware architecture designed for the FSMI algorithm. The design consists of a novel memory banking method that increases the memory bandwidth so that multiple FSMI cores can run in parallel while maintaining high utilization. A novel arbiter is proposed to resolve the memory read conflicts between multiple cores within one clock cycle. The final design on an FPGA achieves more than 100x higher throughput compared with a CPU while consuming less than 1/10 of the power.
by Zhengdong Zhang.
Ph. D.
Ph.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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Sherbaf, Behtash Mohammad. "A Decomposition-based Multidisciplinary Dynamic System Design Optimization Algorithm for Large-Scale Dynamic System Co-Design." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535468984437623.

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Chee, Kenneth W. "APPLIED HW/SW CO-DESIGN: Using the Kendall Tau Algorithm for Adaptive Pacing." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1038.

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Microcontrollers, the brains of embedded systems, have found their way into every aspect of our lives including medical devices such as pacemakers. Pacemakers provide life supporting functions to people therefore it is critical for these devices to meet their timing constraints. This thesis examines the use of hardware co-processing to accelerate the calculation time associated with the critical tasks of a pacemaker. In particular, we use an FPGA to accelerate a microcontroller’s calculation time of the Kendall Tau Rank Correlation Coefficient algorithm. The Kendall Tau Rank Correlation Coefficient is a statistical measure that determines the pacemaker’s voltage level for heart stimulation. This thesis explores three different hardware distributions of this algorithm between an FPGA and a pacemaker’s microcontroller. The first implementation uses one microcontroller to establish the baseline performance of the system. The next implementation executes the entire Kendall Tau algorithm on an FPGA with varying degrees of parallelism. The final implementation of the Kendall Tau algorithm splits the computational requirements between the microcontroller and FPGA. This thesis uses these implementations to compare system-level issues such as power consumption and other tradeoffs that arise when using an FPGA for co-processing.
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Narasimhan, Seetharam. "Ultralow-Power and Robust Implantable Neural Interfaces: An Algorithm-Architecture-Circuit Co-Design Approach." Case Western Reserve University School of Graduate Studies / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=case1333743306.

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Tzou, Nicholas. "Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51876.

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Cost reduction has been and will continue to be a primary driving force in the evolution of hardware design and associated technologies. The objective of this research is to design low-cost signal acquisition systems for characterizing wideband and high-speed signals. As the bandwidth and the speed of such signals increase, the cost of testing also increases significantly; therefore, innovative hardware and algorithm co-design are needed to relieve this problem. In Chapter 2, a low-cost multi-rate system is proposed for characterizing the spectra of wideband signals. The design is low-cost in the sense of the actual component cost, the system complexity, and the effort required for calibration. The associated algorithms are designed such that the hardware can be implemented with low-complexity yet be robust enough to deal with various hardware variations. A hardware prototype is built not only to verify the proposed hardware scheme and algorithms but to serve as a concrete example that shows that characterizing signals with sub-Nyqusit sampling rate is feasible. Chapter 3 introduces a low-cost time-domain waveform reconstruction technique, which requires no mutual synchronization mechanisms. This brings down cost significantly and enables the implementation of systems capable of capturing tens of Gigahertz (GHz) signals for significantly lower cost than high-end oscilloscopes found in the market today. For the first time, band-interleaving and incoherent undersampling techniques are combined to form a low-cost solution for waveform reconstruction. This is enabled by co-designing the hardware and the back-end signal processing algorithms to compensate for the lack of coherent Nyquist rate sampling hardware. A hardware prototype was built to support this work. Chapter 4 describes a novel test methodology that significantly reduces the required time for crosstalk jitter characterization in parallel channels. This is done by using bit patterns with coprime periods as channel stimuli and using signal processing algorithms to separate multiple crosstalk coupling effects. This proposed test methodology can be applied seamlessly in conjunction with the current test methodology without re-designing the test setup. More importantly, the conclusion derived from the mathematical analysis shows that only such test stimuli give unbiased characterization results, which are critical in all high-precision test setups. Hardware measurement results and analysis are provided to support this methodology. This thesis starts with an overview of the background and a literature review. Three major previously mentioned works are addressed in three separate chapters. Each chapter documents the hardware designs, signal processing algorithms, and associated mathematical analyses. For the purpose of verification, the hardware measurement setups and results are discussed at the end of these three chapters. The last chapter presents conclusions and future directions for work from this thesis.
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Cooksey, Kenneth Daniel. "A portfolio approach to design in the presence of scenario-based uncertainty." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49036.

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Current aircraft conceptual design practices result in the selection of a single (hopefully) Pareto optimal design to be carried forward into preliminary design. This paradigm is based on the assumption that carrying a significant number of concepts forward is too costly and thus early down-selection between competing concepts is necessary. However, this approach requires that key architectural design decisions which drive performance and market success are fixed very early in the design process, sometimes years before the aircraft actually goes to market. In the presence of uncertainty, if the design performance is examined for individual scenarios as opposed to measuring performance of the design with aggregate statistics, the author finds that the single concept approach can lead to less than desirable design outcomes. This thesis proposes an alternate conceptual design paradigm which leverages principles from economics (specifically the Nobel prize-winning modern portfolio theory) to improve design outcomes by intelligently selecting a small well diversified portfolio of concepts to carry forward through preliminary design, thus reducing the risk from external events that are outside of the engineer’s control. This alternate paradigm is expected to result in an increase in the overall profit by increasing the probability that the final design matches market needs at the time it goes to market. This thesis presents a portfolio based design approach, which leverages dynamic programming to enable a stochastic optimization of alternative portfolios of concepts. This optimization returns an optimized portfolio of concepts which are iteratively pruned to improve design outcomes in the presence of scenario-driven uncertainties. While dynamic programming is identified as a means for doing a stochastic portfolio optimization, dynamic programming is an analytical optimization process which suffers heavily from the curse of dimensionality. As a result, a new hybrid stochastic optimization process called the Evolutionary Cooperative Optimization with Simultaneous Independent Sub-optimization (ECOSIS) has been introduced. The ECOSIS algorithm leverages a co-evolutionary algorithm to optimize a multifaceted problem under uncertainty. ECOSIS allows for a stochastic portfolio optimization including the desired benefit-to-cost tradeoff for a well-diversified portfolio at the size and scope required for use in design problems. To demonstrate the applicability and value of a portfolio based design approach, an example application of the approach to the selection of a new 300 passenger aircraft is presented.
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Martelli, Maxime. "Approche haut niveau pour l’accélération d’algorithmes sur des architectures hétérogènes CPU/GPU/FPGA. Application à la qualification des radars et des systèmes d’écoute électromagnétique." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLS581/document.

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A l'heure où l'industrie des semi-conducteurs fait face à des difficultés majeures pour entretenir une croissance en berne, les nouveaux outils de synthèse de haut niveau repositionnent les FPGAs comme une technologie de premier plan pour l'accélération matérielle d'algorithmes face aux clusters à base de CPUs et GPUs. Mais en l’état, pour un ingénieur logiciel, ces outils ne garantissent pas, sans expertise du matériel sous-jacent, l’utilisation de ces technologies à leur plein potentiel. Cette particularité peut alors constituer un frein à leur démocratisation. C'est pourquoi nous proposons une méthodologie d'accélération d'algorithmes sur FPGA. Après avoir présenté un modèle d'architecture haut niveau de cette cible, nous détaillons différentes optimisations possibles en OpenCL, pour finalement définir une stratégie d'exploration pertinente pour l'accélération d'algorithmes sur FPGA. Appliquée sur différents cas d'étude, de la reconstruction tomographique à la modélisation d'un brouillage aéroporté radar, nous évaluons notre méthodologie suivant trois principaux critères de performance : le temps de développement, le temps d'exécution, et l'efficacité énergétique
As the semiconductor industry faces major challenges in sustaining its growth, new High-Level Synthesis tools are repositioning FPGAs as a leading technology for algorithm acceleration in the face of CPU and GPU-based clusters. But as it stands, for a software engineer, these tools do not guarantee, without expertise of the underlying hardware, that these technologies will be harnessed to their full potential. This can be a game breaker for their democratization. From this observation, we propose a methodology for algorithm acceleration on FPGAs. After presenting a high-level model of this architecture, we detail possible optimizations in OpenCL, and finally define a relevant exploration strategy for accelerating algorithms on FPGA. Applied to different case studies, from tomographic reconstruction to the modelling of an airborne radar jammer, we evaluate our methodology according to three main performance criteria: development time, execution time, and energy efficiency
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Bahri, Imen. "Contribution des systèmes sur puce basés sur FPGA pour les applications embarquées d’entraînement électrique." Thesis, Cergy-Pontoise, 2011. http://www.theses.fr/2011CERG0529/document.

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La conception des systèmes de contrôle embarqués devient de plus en plus complexe en raison des algorithmes utilisés, de l'augmentation des besoins industriels et de la nature des domaines d'applications. Une façon de gérer cette complexité est de concevoir les contrôleurs correspondant en se basant sur des plateformes numériques puissantes et ouvertes. Plus précisément, cette thèse s'intéresse à l'utilisation des plateformes FPGA System-on-Chip (SoC) pour la mise en œuvre des algorithmes d'entraînement électrique pour des applications avioniques. Ces dernières sont caractérisées par des difficultés techniques telles que leur environnement de travail (pression, température élevée) et les exigences de performance (le haut degré d'intégration, la flexibilité). Durant cette thèse, l'auteur a contribué à concevoir et à tester un contrôleur numérique pour un variateur de vitesse synchrone qui doit fonctionner à 200 °C de température ambiante. Il s'agit d'une commande par flux orienté (FOC) pour une Machine Synchrone à Aimants Permanents (MSAP) associée à un capteur de type résolveur. Une méthode de conception et de validation a été proposée et testée en utilisant une carte FPGA ProAsicPlus de la société Actel/Microsemi. L'impact de la température sur la fréquence de fonctionnement a également été analysé. Un état de l'art des technologies basées sur les SoC sur FPGA a été également présenté. Une description détaillée des plateformes numériques récentes et les contraintes en lien avec les applications embarquées a été également fourni. Ainsi, l'intérêt d'une approche basée sur SoC pour des applications d'entrainements électriques a été démontré. D'un autre coté et pour profiter pleinement des avantages offertes par les SoC, une méthodologie de Co-conception matériel-logiciel (hardware-software (HW-SW)) pour le contrôle d'entraînement électrique a été proposée. Cette méthode couvre l'ensemble des étapes de développement de l'application de contrôle à partir des spécifications jusqu'à la validation expérimentale. Une des principales étapes de cette méthode est le partitionnement HW-SW. Le but est de trouver une combinaison optimale entre les modules à mettre en œuvre dans la partie logiciel et celles qui doivent être mis en œuvre dans la partie matériel. Ce problème d'optimisation multi-objectif a été réalisé en utilisant l'algorithme de génétique, Non-Dominated Sorting Genetic Algorithm (NSGA-II). Ainsi, un Front de Pareto des solutions optimales peut être déduit. L'illustration de la méthodologie proposée a été effectuée en se basant sur l'exemple du régulateur de vitesse sans capteur utilisant le filtre de Kalman étendu (EKF). Le choix de cet exemple correspond à une tendance majeure dans le domaine des contrôleurs embraqués pour entrainements électriques. Par ailleurs, la gestion de l'architecture du contrôleur embarqué basée sur une approche SoC a été effectuée en utilisant un système d'exploitation temps réel. Afin d'accélérer les services de ce système d'exploitation, une unité temps réel a été développée en VHDL et associée au système d'exploitation. Il s'agit de placer les services d'ordonnanceur et des processus de communication du système d'exploitation logiciel au matériel. Ceci a permis une accélération significative du traitement. La validation expérimentale d'un contrôleur du courant a été effectuée en utilisant un banc de test du laboratoire. Les résultats obtenus prouvent l'intérêt de l'approche proposée
Designing embedded control systems becomes increasingly complex due to the growing of algorithm complexity, the rising of industrials requirements and the nature of application domains. One way to handle with this complexity is to design the corresponding controllers on performing powerful and open digital platforms. More specifically, this PhD deals with the use of FPGA System-on-Chip (SoC) platforms for the implementation of complex AC drive controllers for avionic applications. These latters are characterized by stringent technical issues such as environment conditions (pressure, high temperature) and high performance requirements (high integration, flexibility and efficiency). During this thesis, the author has contributed to design and to test a digital controller for a high temperature synchronous drive that must operate at 200°C ambient. It consists on the Flux Oriented Controller (FOC) for a Permanent Magnet Synchronous Machine (PMSM) associated with a Resolver sensor. A design and validation method has been proposed and tested using a FPGA ProAsicPlus board from Actel-Microsemi Company. The impact of the temperature on the operating frequency has been also analyzed. A state of the art FPGA SoC technology has been also presented. A detailed description of the recent digital platforms and constraints in link with embedded applications was investigated. Thus, the interest of a SoC-based approach for AC drives applications was also established. Additionally and to have full advantages of a SoC based approach, an appropriate HW-SW Co-design methodology for electrical AC drive has been proposed. This method covers the whole development steps of the control application from the specifications to the final experimental validation. One of the main important steps of this method is the HW-SW partitioning. The goal is to find an optimal combination between modules to be implemented in software and those to be implemented in hardware. This multi-objective optimization problem was performed with the Non-Dominated Sorting Genetic Algorithm (NSGA-II). Thus, the Pareto-Front of optimal solution can be deduced. The illustration of the proposed Co-design methodology was made based on the sensorless speed controller using the Extended Kalman Filter (EKF). The choice of this benchmark corresponds to a major trend in embedded control of AC drives. Besides, the management of SoC-based architecture of the embedded controller was allowed using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration has been achieved. The experimentation tests based on digital current controller were also carried out using a laboratory set-up. The obtained results prove the interest of the proposed approach
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Trindade, Alessandro Bezerra. "Aplicando verificação de modelos baseada nas teorias do módulo da satisfabilidade para o particionamento de hardware/software em sistemas embarcados." Universidade Federal do Amazonas, 2015. http://tede.ufam.edu.br/handle/tede/4091.

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When performing hardware/software co-design for embedded systems, does emerge the problem of allocating properly which functions of the system should be implemented in hardware (HW) or in software (SW). This problem is known as HW/SW partitioning and in the last ten years, a significant research effort has been carried out in this area. In this proposed project, we present two new approaches to solve the HW/SW partitioning problem by using SMT-based verification techniques, and comparing the results using the traditional technique of Integer Linear Programming (ILP) and a modern method of optimization by Genetic Algorithm (GA). The goal is to show with experimental results that model checking techniques can be effective, in particular cases, to find the optimal solution of the HW/SW partitioning problem using a state-of-the-art model checker based on Satisfiability Modulo Theories (SMT) solvers, when compared to the traditional techniques.
Quando se realiza um coprojeto de hardware/software para sistemas embarcados, emerge o problema de se decidir qual função do sistema deve ser implementada em hardware (HW) ou em software (SW). Este tipo de problema recebe o nome de particionamento de HW/SW. Na última década, um esforço significante de pesquisa tem sido empregado nesta área. Neste trabalho, são apresentadas duas novas abordagens para resolver o problema de particionamento de HW/SW usando técnicas de verificação formal baseadas nas teorias do módulo da satisfabilidade (SMT). São comparados os resultados obtidos com a tradicional técnica de programação linear inteira (ILP) e com o método moderno de otimização por algoritmo genético (GA). O objetivo é demonstrar, com os resultados empíricos, que as técnicas de verificação de modelos podem ser efetivas, em casos particulares, para encontrar a solução ótima do problema de particionamento de HW/SW usando um verificador de modelos baseado no solucionador SMT, quando comparado com técnicas tradicionais.
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Zhang, Yuanzhi. "Algorithms and Hardware Co-Design of HEVC Intra Encoders." OpenSIUC, 2019. https://opensiuc.lib.siu.edu/dissertations/1769.

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Digital video is becoming extremely important nowadays and its importance has greatly increased in the last two decades. Due to the rapid development of information and communication technologies, the demand for Ultra-High Definition (UHD) video applications is becoming stronger. However, the most prevalent video compression standard H.264/AVC released in 2003 is inefficient when it comes to UHD videos. The increasing desire for superior compression efficiency to H.264/AVC leads to the standardization of High Efficiency Video Coding (HEVC). Compared with the H.264/AVC standard, HEVC offers a double compression ratio at the same level of video quality or substantial improvement of video quality at the same video bitrate. Yet, HE-VC/H.265 possesses superior compression efficiency, its complexity is several times more than H.264/AVC, impeding its high throughput implementation. Currently, most of the researchers have focused merely on algorithm level adaptations of HEVC/H.265 standard to reduce computational intensity without considering the hardware feasibility. What’s more, the exploration of efficient hardware architecture design is not exhaustive. Only a few research works have been conducted to explore efficient hardware architectures of HEVC/H.265 standard. In this dissertation, we investigate efficient algorithm adaptations and hardware architecture design of HEVC intra encoders. We also explore the deep learning approach in mode prediction. From the algorithm point of view, we propose three efficient hardware-oriented algorithm adaptations, including mode reduction, fast coding unit (CU) cost estimation, and group-based CABAC (context-adaptive binary arithmetic coding) rate estimation. Mode reduction aims to reduce mode candidates of each prediction unit (PU) in the rate-distortion optimization (RDO) process, which is both computation-intensive and time-consuming. Fast CU cost estimation is applied to reduce the complexity in rate-distortion (RD) calculation of each CU. Group-based CABAC rate estimation is proposed to parallelize syntax elements processing to greatly improve rate estimation throughput. From the hardware design perspective, a fully parallel hardware architecture of HEVC intra encoder is developed to sustain UHD video compression at 4K@30fps. The fully parallel architecture introduces four prediction engines (PE) and each PE performs the full cycle of mode prediction, transform, quantization, inverse quantization, inverse transform, reconstruction, rate-distortion estimation independently. PU blocks with different PU sizes will be processed by the different prediction engines (PE) simultaneously. Also, an efficient hardware implementation of a group-based CABAC rate estimator is incorporated into the proposed HEVC intra encoder for accurate and high-throughput rate estimation. To take advantage of the deep learning approach, we also propose a fully connected layer based neural network (FCLNN) mode preselection scheme to reduce the number of RDO modes of luma prediction blocks. All angular prediction modes are classified into 7 prediction groups. Each group contains 3-5 prediction modes that exhibit a similar prediction angle. A rough angle detection algorithm is designed to determine the prediction direction of the current block, then a small scale FCLNN is exploited to refine the mode prediction.
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Books on the topic "Algorithm co-design"

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Mazumder, Pinaki, and Nanchuan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Limited, John, 2020.

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Mazumder, Pinaki, and Nan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Incorporated, John, 2019.

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Mazumder, Pinaki, and Nan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Incorporated, John, 2019.

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Mazumder, Pinaki, and Nan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Limited, John, 2019.

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Li, Huanglong, J. Joshua Yang, and Hongsik Jeong, eds. Memristive Neuromorphics: Materials, Devices, Circuits, Architectures, Algorithms and their Co-Design. Frontiers Media SA, 2022. http://dx.doi.org/10.3389/978-2-88974-460-2.

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Book chapters on the topic "Algorithm co-design"

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Vuduc, Richard, and Kenneth Czechowski. "Toward a Theory of Algorithm-Architecture Co-design." In Lecture Notes in Computer Science, 4–8. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38718-0_2.

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Selvabala, B., and D. Devaraj. "Co-ordinated Design of AVR-PSS Using Multi Objective Genetic Algorithm." In Swarm, Evolutionary, and Memetic Computing, 481–93. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-17563-3_57.

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Parras-Gutierrez, Elisabet, Víctor M. Rivas, and Maria Jose del Jesus. "Automatic Neural Net Design by Means of a Symbiotic Co-evolutionary Algorithm." In Lecture Notes in Computer Science, 140–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-87656-4_18.

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Ghimire, Manisha, Emma Regentova, and Venkatesan Muthukumar. "A -SLIC: Acceleration of SLIC Superpixel Segmentation Algorithm in a Co-Design Framework." In Advances in Intelligent Systems and Computing, 663–67. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-43020-7_90.

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Lodha, Nupur, Nivesh Rai, Rahul Dubey, and Hrishikesh Venkataraman. "Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor." In Information Systems, Technology and Management, 197–207. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00405-6_23.

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Patil, Vilabha S., Shraddha S. Deshpande, and Yashwant B. Mane. "FPGA Based Acceleration of Security Algorithm Using Co-design Approach for WSN Applications." In Advances in Intelligent Systems and Computing, 592–603. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30465-2_66.

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Merchant, Farhad, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, and Ranjani Narayan. "Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 119–31. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_10.

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Lai, Kok Choong, M. L. Dennis Wong, and Syed Zahidul Islam. "A HW/SW Co-Design Implementation of Viola-Jones Algorithm for Driver Drowsiness Detection." In Lecture Notes in Electrical Engineering, 427–35. Dordrecht: Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6516-0_46.

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Ramteke, Pradnya G., Meghana Hasamnis, and S. S. Limaye. "Co-design Approach for Implementation of Decryption Block of Rijndael’s Algorithm Using Soft Core Processor." In Communications in Computer and Information Science, 721–29. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36321-4_67.

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Wolf, Wayne. "Hardware/Software Co-Synthesis Algorithms." In Hardware/Software Co-Design: Principles and Practice, 47–73. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2649-7_2.

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Conference papers on the topic "Algorithm co-design"

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Batarseh, Fadi, Uwe Paul Schroeder, Jeff Nelson, Ya-Chieh Lai, Piyush Pathak, Sriram Madhavan, and Philippe Hurat. "Pattern similarity profiling using semi-supervised learning algorithm." In Design-Technology Co-optimization XV, edited by Chi-Min Yuan and Ryoung-Han Kim. SPIE, 2021. http://dx.doi.org/10.1117/12.2586112.

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Ji, Hao, Masha Sosonkina, and Yaohang Li. "An Implementation of Block Conjugate Gradient Algorithm on CPU-GPU Processors." In 2014 Hardware-Software Co-Design for High Performance Computing (Co-HPC). IEEE, 2014. http://dx.doi.org/10.1109/co-hpc.2014.10.

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Tramm, John R., Kazutomo Yoshii, and Andrew R. Siegel. "Power Profiling of a Reduced Data Movement Algorithm for Neutron Cross Section Data in Monte Carlo Simulations." In 2014 Hardware-Software Co-Design for High Performance Computing (Co-HPC). IEEE, 2014. http://dx.doi.org/10.1109/co-hpc.2014.9.

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Schroeder, Uwe Paul, Ahmed Shalabi, Janam Bakshi, Mohamed Ismail, and Ahmed M. Elsemary. "Optimizing DFM scores by using a genetic evolution algorithm." In Design-Process-Technology Co-optimization for Manufacturability XIII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2019. http://dx.doi.org/10.1117/12.2515094.

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Huang, Qijing, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, and John Wawrzynek. "Algorithm-hardware Co-design for Deformable Convolution." In 2019 Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing - NeurIPS Edition (EMC2-NIPS). IEEE, 2019. http://dx.doi.org/10.1109/emc2-nips53020.2019.00019.

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Lucarz, Christophe, Marco Mattavelli, and Julien Dubois. "A co-design platform for algorithm/architecture design exploration." In 2008 IEEE International Conference on Multimedia and Expo (ICME). IEEE, 2008. http://dx.doi.org/10.1109/icme.2008.4607623.

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Dick, Gregory J., Abhishek Asthana, Liang Cao, Jing Cheng, and David Power. "Optimization of optical proximity correction to reduce mask write time using genetic algorithm." In Design-Process-Technology Co-optimization for Manufacturability XII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2018. http://dx.doi.org/10.1117/12.2297400.

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Gai, Tianyang, Ying Chen, Pengzheng Gao, Xiaojing Su, Lisong Dong, Yajuan Su, Yayi Wei, and Tianchun Ye. "Sample patterns extraction from layout automatically based on hierarchical cluster algorithm for lithography process optimization." In Design-Process-Technology Co-optimization for Manufacturability XIII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2019. http://dx.doi.org/10.1117/12.2514177.

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"Session TP7a: Algorithm/architecture co-design [breaker page]." In 2013 Asilomar Conference on Signals, Systems and Computers. IEEE, 2013. http://dx.doi.org/10.1109/acssc.2013.6810531.

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Czechowski, Kenneth, and Richard Vuduc. "A Theoretical Framework for Algorithm-Architecture Co-design." In 2013 IEEE International Symposium on Parallel & Distributed Processing (IPDPS). IEEE, 2013. http://dx.doi.org/10.1109/ipdps.2013.99.

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Reports on the topic "Algorithm co-design"

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Daudelin, Francois, Lina Taing, Lucy Chen, Claudia Abreu Lopes, Adeniyi Francis Fagbamigbe, and Hamid Mehmood. Mapping WASH-related disease risk: A review of risk concepts and methods. United Nations University Institute for Water, Environment and Health, December 2021. http://dx.doi.org/10.53328/uxuo4751.

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The report provides a review of how risk is conceived of, modelled, and mapped in studies of infectious water, sanitation, and hygiene (WASH) related diseases. It focuses on spatial epidemiology of cholera, malaria and dengue to offer recommendations for the field of WASH-related disease risk mapping. The report notes a lack of consensus on the definition of disease risk in the literature, which limits the interpretability of the resulting analyses and could affect the quality of the design and direction of public health interventions. In addition, existing risk frameworks that consider disease incidence separately from community vulnerability have conceptual overlap in their components and conflate the probability and severity of disease risk into a single component. The report identifies four methods used to develop risk maps, i) observational, ii) index-based, iii) associative modelling and iv) mechanistic modelling. Observational methods are limited by a lack of historical data sets and their assumption that historical outcomes are representative of current and future risks. The more general index-based methods offer a highly flexible approach based on observed and modelled risks and can be used for partially qualitative or difficult-to-measure indicators, such as socioeconomic vulnerability. For multidimensional risk measures, indices representing different dimensions can be aggregated to form a composite index or be considered jointly without aggregation. The latter approach can distinguish between different types of disease risk such as outbreaks of high frequency/low intensity and low frequency/high intensity. Associative models, including machine learning and artificial intelligence (AI), are commonly used to measure current risk, future risk (short-term for early warning systems) or risk in areas with low data availability, but concerns about bias, privacy, trust, and accountability in algorithms can limit their application. In addition, they typically do not account for gender and demographic variables that allow risk analyses for different vulnerable groups. As an alternative, mechanistic models can be used for similar purposes as well as to create spatial measures of disease transmission efficiency or to model risk outcomes from hypothetical scenarios. Mechanistic models, however, are limited by their inability to capture locally specific transmission dynamics. The report recommends that future WASH-related disease risk mapping research: - Conceptualise risk as a function of the probability and severity of a disease risk event. Probability and severity can be disaggregated into sub-components. For outbreak-prone diseases, probability can be represented by a likelihood component while severity can be disaggregated into transmission and sensitivity sub-components, where sensitivity represents factors affecting health and socioeconomic outcomes of infection. -Employ jointly considered unaggregated indices to map multidimensional risk. Individual indices representing multiple dimensions of risk should be developed using a range of methods to take advantage of their relative strengths. -Develop and apply collaborative approaches with public health officials, development organizations and relevant stakeholders to identify appropriate interventions and priority levels for different types of risk, while ensuring the needs and values of users are met in an ethical and socially responsible manner. -Enhance identification of vulnerable populations by further disaggregating risk estimates and accounting for demographic and behavioural variables and using novel data sources such as big data and citizen science. This review is the first to focus solely on WASH-related disease risk mapping and modelling. The recommendations can be used as a guide for developing spatial epidemiology models in tandem with public health officials and to help detect and develop tailored responses to WASH-related disease outbreaks that meet the needs of vulnerable populations. The report’s main target audience is modellers, public health authorities and partners responsible for co-designing and implementing multi-sectoral health interventions, with a particular emphasis on facilitating the integration of health and WASH services delivery contributing to Sustainable Development Goals (SDG) 3 (good health and well-being) and 6 (clean water and sanitation).
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