Journal articles: 'AGC CIRCUITS'

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Gao, Zhi Qiang, Fu Xiang Huang, Jing Li, Liang Yin, and Xiao Wei Liu. "A CMOS Automatic Gain Control Circuit for Biomedical Applications." Key Engineering Materials 645-646 (May 2015): 1308–13. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.1308.

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In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.

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Pandey, Rajeshwari, Neeta Pandey, Mayank Bothra, and Sajal K. Paul. "Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators." Journal of Electrical and Computer Engineering 2011 (2011): 1–8. http://dx.doi.org/10.1155/2011/586853.

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Multiphase sinusoidal oscillator circuits are presented which utilize Operational Transresistance Amplifier (OTRA) as the active element. The first circuit producesnodd-phase oscillations of equal amplitudes and equally spaced in phase. The second circuit is capable of producingnodd- or even- phase oscillations equally spaced in phase. An alternative approach is discussed in the third circuit, which utilizes a single-phase tunable oscillator circuit which is used to inject signals into a phase shifter circuits. An automatic gain control (AGC) circuit has been implemented for the second and third circuit. The circuits are simple to realize and have a low component count. PSPICE simulations have been given to verify the theoretical analysis. The experimental outcome corroborates the theoretical propositions and simulated results.

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Badger, D. M. "Stability of AGC circuits containing peak detectors." IEEE Transactions on Consumer Electronics 38, no. 3 (1992): 377–83. http://dx.doi.org/10.1109/30.156710.

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Sotner, Roman, Lukas Langhammer, Jan Jerabek, Peter A. Ushakov, and Tomas Dostal. "Fractional-Order Phase Shifters with Constant Magnitude Frequency Responses." Elektronika ir Elektrotechnika 25, no. 5 (October 6, 2019): 25–30. http://dx.doi.org/10.5755/j01.eie.25.5.24352.

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This contribution presents and experimentally analyzes the idea how to reach the constant magnitude as well as the phase response in the fractional-order (FO) phase when shifting two-ports. The straightforward method employing the automatic gain control circuit (AGC) in a cascade after so-called constant phase block approximating FO integrator or differentiator is studied. The variable gain amplifier utilized in AGC and simple RC-based FO constant phase elements (approximating capacitors with order alpha = 1/4 and alpha = 1/2 as an example) connected in the feedback of operational amplifier-based integrator are established in the experimental setup. The operation indicated in three decades (between 100 Hz and 100 kHz) is evaluated. The known solutions of the standard FO phase shifting circuits are discussed and generally compared with the features obtained in this paper, together with the supposed effects of AGC on their performances.

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Fuada, Syifaul, Angga Pratama Putra, Yulian Aska, and Trio Adiono. "A First Approach to Design Mobility Function and Noise Filter in VLC System Utilizing Low-cost Analog Circuits." International Journal of Recent Contributions from Engineering, Science & IT (iJES) 5, no. 2 (July 6, 2017): 14. http://dx.doi.org/10.3991/ijes.v5i2.6700.

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Visible Light Communication (VLC) as one of wireless technology must be able to offer a good capability as mobile communication system. The signal will be faded when the distance and angle of LED to photo-detector become higher at a certain distance. Other problem at VLC system is light interference noise which is caused by flicker effect from other light sources such as incandescent, fluorescent, DC-lamp (i.e. flashlight) and the sunlight. Each of lights have specific carried signal characteristics and it can influences the VLC system. In this paper we offer design of mobile VLC system based on analog domain. We use Automatic Gain Controller (AGC) circuit using commercially available IC and it will be placed at analog front-end receiver side. AGC can self-adjust its gain according to the input signal amplitude. We also design analog filter to eliminate all interferences noise spectrum which is existed under 50 KHz. We design both circuits, analog filter and AGC in VLC receiver system with low-cost. The test data are obtained through the simulation and achieved good results in ideal condition.

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Khoury, J. M. "On the design of constant settling time AGC circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 3 (March 1998): 283–94. http://dx.doi.org/10.1109/82.664234.

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Yu, Min Li, Yan Jun Bi, and Hong Xiu Meng. "Design of Digital Storage Oscilloscope Based on FPGA." Applied Mechanics and Materials 333-335 (July 2013): 2323–26. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.2323.

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A kind of portable digital storage oscilloscope (DSO) is developed in this paper. It builds trigger, storage, measurement module for embedded system with programmable logic resource of FPGA chip. The external digital circuits of a digital oscilloscope is achieved. And it saves a lot of cost by implanting NIOS II soft-core processor as the control unit of the system in the FPGA. This system has the function of automatic frequency control (AFC) and automatic gain control (AGC), and it can measure the signal conveniently.

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MASUDA, T., N. SHIRAMIZU, E. OHUE, K. ODA, R. HAYAMI, M. KONDO, T. ONAI, et al. "A SiGe HBT IC CHIPSET for40-Gb/s OPTICAL TRANSMISSION SYSTEMS." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 239–63. http://dx.doi.org/10.1142/s0129156403001594.

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Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifier, a common-base input stage is introduced. In order to have high gain and wide bandwidth simultaneously, active load circuits composed of a differential transimpedance amplifier are used for the AGC amplifier, the limiting amplifier, and the decision circuit. Full-rate clocking is employed to reduce the influence caused by clock-duty variation in digital circuits such as the decision circuit, the demultiplexer, and the multiplexer. All ICs were characterized by using on-wafer probes, and some of them were built in brass-packages for bit-error rate measurement.

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Plyushch, O. H., and V. I. Kravchenko. "Utilization of AGC circuits in signal processing algorithms in adaptive antenna arrays." Connectivity 142, no. 6 (2019): 52–57. http://dx.doi.org/10.31673/2412-9070.2019.065257.

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Bentler, Ruth A., and John A. Nelson. "Assessing Release-Time Options in a Two-Channel AGC Hearing Aid." American Journal of Audiology 6, no. 1 (March 1997): 43–51. http://dx.doi.org/10.1044/1059-0889.0601.43.

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The purpose of this study was to determine whether different release times, as implemented in a commercial two-channel AGC hearing aid, would result in differing speech intelligibility performance, user preference, or use time. In experiment one, 14 subjects were fitted with a two-channel multi-memory AGC hearing aid. Four memories were programmed to have identical frequency responses and output limitation characteristics. Only the release times were varied, with the low channel/high channel set as follows (in ms): 20/35, 20/150, 100/35, 500/7. Results obtained from the NST (+5 S/N), magnitude estimations of intelligibility, and data-logging of use time did not show any release-time pair to be superior to any other. In experiment two, 10 subjects participated in a forced-choice, paired-comparison procedure using the same release-time pairs from experiment one. Auditory stimuli consisted of three input levels, consisting of speech, speech in noise, and music. Results indicated no release-time pair to be superior in any listening condition. Results may be explained, in part, by the use of a curvilinear compression circuit and the milder hearing loss exhibited by the subjects. Future investigation of the effect of release-time variation should be carried out on circuits with adjustable compression parameters (and fixed compression ratios) with listeners exhibiting different degrees of hearing loss.

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Stojanovic, Nebojsa, and Theodor Kupfer. "On the Design of AGC Circuits in IM-DD NRZ Optical Transmission Systems." Journal of Lightwave Technology 26, no. 20 (October 2008): 3426–33. http://dx.doi.org/10.1109/jlt.2008.927797.

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Wang, Xiao Fei, Bo Quan Li, and Hai Bin Pan. "Design of Signal Processing System for Doppler Speed Radar Based on SOPC." Key Engineering Materials 464 (January 2011): 237–40. http://dx.doi.org/10.4028/www.scientific.net/kem.464.237.

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Doppler speed radar is a high precision velocity measuring instrument based on Doppler Effect, which has widely applications in measuring moving target’s velocity. In this paper, a novel design of Doppler signal processing system was presented to perform projectile’s speed measurement tasks. The system architecture is based on an Altera Cyclone II chip and designed as a System-on-a-Programmable-Chip (SOPC) with the help of an embedded Nios II software processor. And the SOPC system integrates CPU, memory, I/O interface and some other reconfigured modules required in system. According to the proposed scheme, the peripheral circuits were designed in this system, such as signal condition, A/D conversion and auto gain control (AGC) circuit. We also proposed to use spectral analysis method based on windowed FFT to deal with the measured target’s Doppler signal. Further, the signal source of simulating targets was used to testify the system feasibility. In addition, future work can include the further study on frequency estimation algorithms or comparisons of the proposed architecture with traditional design.

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Dominikowski, Bartosz. "Measuring Current in a Power Converter Using Fuzzy Automatic Gain Control." Applied Sciences 11, no. 13 (June 22, 2021): 5793. http://dx.doi.org/10.3390/app11135793.

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The accuracy of current measurements can be increased by appropriate amplification of the signal to within the measurement range. Accurate current measurement is important for energy monitoring and in power converter control systems. Resistance and inductive current transducers are used to measure the major current in AC/DC power converters. The output value of the current transducer depends on the load motor, and changes across the whole measurement range. Modern current measurement circuits are equipped with operational amplifiers with constant or programmable gain. These circuits are not able to measure small input currents with high resolution. This article proposes a precise loop gain system that can be implemented with various algorithms. Computer analysis of various automatic gain control (AGC) systems proved the effectiveness of the Mamdani controller, which was implemented in an MCU (microprocessor). The proposed fuzzy controller continuously determines the value of the conversion factor. The system also enables high resolution measurements of the current emitted from small electric loads (≥1 A) when the electric motor is stationary.

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Gu, Youzhi, Xinjie Feng, Runze Chi, Jiangfeng Wu, and Yongzhen Chen. "A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver." Electronics 11, no. 21 (October 27, 2022): 3489. http://dx.doi.org/10.3390/electronics11213489.

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With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and more attention due to their flexible and powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock and data recovery (MM-CDR) circuits are widely used in ADC-based wireline receivers since MM-CDR circuits only need one sample signal per unit interval (UI). However, MM-CDR circuits need to set an additional Vref voltage to match the size of the main tap of the channel. If the Vref matching is not appropriate or the signal quality is good as a square wave, MM-CDR circuits cannot accurately lock on to a certain phase and instead drift within a phase range. Therefore, MM-CDR circuits are not as robust and stable as oversampled CDR circuits. In this study, a digital bang-bang clock and data recovery (DBB-CDR) circuit combined with an ADC-based wireline receiver was proposed. The DBB-CDR circuit could eliminate various unstable factors of MM-CDR circuits and achieve fast and robust phase locking without excessively increasing power consumption. A model of the DBB-CDR circuit was combined with an actual 32 Gb/s ADC-based wireline receiver, which was implemented in 28 nm CMOS technology to analyze the performance of the DBB-CDR circuit. The simulation results showed that the DBB-CDR circuit could achieve 0.42 UIpp JTOL@10MHz, and that the minimum JTOL value was 0.362 UIpp under a 0.04 UI variance of Gaussian jitter. The area and power consumption of the DBB-CDR circuit were only 64 μm2 and 0.02 mW, respectively; and the DBB-CDR circuit could also obtain very stable phase locking and demonstrated a fast frequency offset tracking ability when there was a frequency offset.

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Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

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Strle, Drago, and Janez Trontelj. "On Self-Aware Mixed-Signal Systems Based on S-Δ ADC." International Journal of Embedded and Real-Time Communication Systems 3, no. 2 (April 2012): 92–110. http://dx.doi.org/10.4018/jertcs.2012040105.

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In this paper the authors discuss the issues related to the self-awareness of high-resolution, mixed-signal circuits and systems, based on S-? ADC, which is the most important and sensitive module and the key element for analogue to digital conversion. The basic methodology and framework for improving the self-awareness of such systems are presented. The methodology is based on efficient real-time measurements of a high-resolution, mixed-signal system using pseudo random signal source, real-time calculation of a distance between responses, the possibility to adapt measured circuit to minimize the distance, and changing the parameters of a reference system according to learning rules. The use of pseudo-random noise as a signal source leads to efficient and cost-effective measurements that run in parallel to the main signal processing. The calculation of the distance between the system and its reference are theoretically analysed and verified using Matlab model. The response of a system together with the response of high precision analogue to digital converter (ADC) is compared to the response of a bit-true model of a reference digital circuit. The differences are calculated using simple area-efficient cross-correlation algorithm. Together with adaptation strategy and tuning circuitry it forms the basis for self-awareness of mixed-signal circuits.

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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (May 28, 2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.

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Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.

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Bulucea, Cornelia A., Constantin Brindusa, Doru A. Nicola, Nikos E. Mastorakis, Carmen A. Bulucea, and Philippe Dondon. "Evaluating through mathematical modelling the power equipment busbars electrodynamic strength under sudden short-circuit conditions." MATEC Web of Conferences 210 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201821002004.

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The electrodynamic strength, as forces acting between the current-carrying electric circuits are exerted as long as the currents exist, and have the tendency of deformation and displacement of the circuits. In short-circuit regimes the strength in electrical equipment becomes severe. For instance, short-circuits highly affect power transformers connected to power transmission lines. The effects are also strong because of mechanical deformations occurring in the power transformer connection part. In line with this idea, in this paper it is made an analytical study upon the a.c. single-phase and a.c. three-phase electric circuits, taking into account the current instantaneous maximum value. The paper also entails numerical simulations of electrodynamic strength in power transformer busbars under short-circuit conditions. MATLAB software, with its specific extensions, enable simulation models to generate the charts of the electrodynamic forces in the power transformer connection bars.

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Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

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Reed, Lynn, John Hoenig, and Vema Reddy. "The Design and Characterization of an 8-bit ADC for 250°C Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000027–32. http://dx.doi.org/10.4071/hiten-session1-paper1_5.

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Many high temperature applications require the measurement of analog voltages. This usually requires the integration of an ADC into the design. While the temperature degradation in performance of digital circuits is well known, the effects of temperature on analog circuitry are much harder to predict. Analog design is often an iterative process in which the characterization knowledge of a fabricated design is used to improve the next iteration of the design. This paper presents the results of the most recent iteration. This paper describes how the design of an existing 8-bit ADC was optimized for the SOI process. It also presents the characterization of the ADC at various temperatures up to 250°C and shows the effects of increased leakage on the ADC parameters of linearity, accuracy, and conversion speed. The ADC discussed is a successive approximation design which uses a resistive DAC. The design was modified to take advantage of the resistive characteristics inherent in the SOI process. Specifically, the DAC resistors were formed using N-type diffusion because of their superior matching as compared to using poly. The analog circuitry in the DAC switching and in the comparator required carefully choosing where to use “A” type versus “H” type transistor geometries to prevent inadvertent SCR failures. The ADC design also included a serial interface circuit that facilitates measurements within an oven by minimizing the number of connections required for operation. The measurements were taken using a 12-bit DAC to generate the analog input voltages to the 8-bit ADC under test. The ADC digital output was compared to the digital input to the DAC. All 4096 measurement points were taken at each voltage and temperature step. The results of these measurements were post-processed to extract the characterization data. There is a discussion of the results, the effects of leakage on those results, and how these effects might be overcome to produce more accurate ADC circuits in the future.

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (June 30, 2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more designing than digital circuit design and Kobayashi and Kuwana firmly believe that 'beautiful' mathematics can facilitate truly great circuit design. Additional mathematics techniques employed by Kobayashi and the team are statistics, coding theory, modulation and signal processing algorithms and pairing pure mathematics theorems with electrical engineering is a key feature of the researchers' work. The team utilises theoretical analysis and simulations such as the circuit simulator (SPICE) and system simulator (MATLAB) to test its work and collaborates with semiconductor companies and electronic measurement instrument companies in Japan for smart circuit design and effective circuit testing. So far, results include that using SAR ADC configurations with Fibonacci sequence weights can improve the speeds and reliability of the SAR ADC. Also several new DAC architecutures and waveform sampling methods are derived based on mathematics.

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Matrosova, Angela Yu, Victor A. Provkin, and Valentina V. Andreeva. "Masking of Internal Nodes Faults Based on Applying of Incompletely Specified Boolean Functions." Izvestiya of Saratov University. New Series. Series: Mathematics. Mechanics. Informatics 20, no. 4 (2020): 517–26. http://dx.doi.org/10.18500/1816-9791-2020-20-4-517-526.

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Combinational circuits (combinational parts of sequential circuits) are considered. Masking of internal nodes faults with applying sub-circuit, inputs of which are connected to the circuit inputs and outputs — to the circuit proper internal nodes, is suggested. The algorithm of deriving incompletely specified Boolean function for an internal node of the circuit based on using operations on ROBDDs is described. Masking circuit (patch circuit) design for the given internal fault nodes is reduced to covering of the system of incompletely specified Boolean functions corresponding to the fault nodes by the proper SoP system. Then the obtained system of completely specified Boolean functions is applied to derive masking circuit by using ABC system (A System for Sequential Synthesis and Verification). Experiments on bench marks show essential cutting of overhead in the frame of the suggested approach.

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Marcinkevičius, Albinas J., and V. Jasonis. "The Calculation of Dynamic Errors in Signal Transformation Circuits of Analog-to-Digital Converters for Mechatronic Systems." Solid State Phenomena 113 (June 2006): 131–36. http://dx.doi.org/10.4028/www.scientific.net/ssp.113.131.

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Precision and wide-band analog-to-digital converters (ADC) are used for information processing in mechatronic systems. The analog signal transformation circuits, such as sample, and hold circuit (SHC) and an analog signal interpolation circuit (ASIC), are applied with the aim of increasing the precision of converters. These circuits allow for reducing the quantity of comparators in the converter and increase their dynamic stability. The models of SHC and ASIC as well as the results of the calculation precision and dynamic parameters of such circuits are presented in this paper. Equations for the calculation of the aperture error in the Gaussian and a sinusoidal input signal were derived. The structural model, proposed for SHC, evaluates the nonlinearity of a transfer characteristic, and the influence of noise in the signal and strobe channels. The results of the theoretical research and analytical equations for the evaluation of the number of signal interpolation block differential amplifiers, which depends on the analog signal’s maximal frequency and the number of segments of the converter, are presented. The results of this work allow one to estimate the main precision and dynamic parameters of ADC transformation circuits.

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Amril, Muhammad, Panangian Mahadi Sihombing, and Sukarwoto Sukarwoto. "DESAIGN AND SIMULATION OF ADC CIRCUITS COMPILED BY IC ADC0804 AND IC ADC0809." JURTEKSI (Jurnal Teknologi dan Sistem Informasi) 9, no. 2 (March 24, 2023): 207–14. http://dx.doi.org/10.33330/jurteksi.v9i2.1957.

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Abstract: Medan Aviation Polytechnic is one of the campuses under the ministry of transportation which has a major in telecommunication and air navigation engineering in Indonesia. Based on field surveys, an Analog to Digital Converter (ADC) practicum kit is needed to improve the ability of cadets. Based on this background, this study aims to design and simulate two ADC circuits, each of which is compiled by the integrated circuit (IC) ADC0804 and IC ADC0809 respectively. Three statistical formulas, namely mean error (ME), standard deviation error (SDE), and root mean square error (RMSE) are used to measure the performance of the two ADC circuits. Both ADC circuits are simulated using a Proteus 8.11 Simulator with 255 analog input voltages. Based on the result of the study, it is known that the ADC circuit compiled by IC ADC0809 is more accurate than the ADC circuit compiled by IC ADC0804. This is evidenced by a smaller error value, which is based on the simulation results of the ME, SDE, and RMSE values were 0.4210, 0.3410, and 0.5110, respectively. And, based on the measurement results, it has ME, SDE, RMSE respectively, namely 0.8510, 0.8110, and 0.9310. Keywords: ADC; Proteus 8.11 Simulator; IC ADC0804; IC ADC0809; ME; SDE; RMSE Abstrak: Politeknik Penerbangan Medan adalah salah satu kampus di bawah Kementerian Perhubungan yang memiliki jurusan teknik telekomunikasi dan navigasi udara di Indonesia. Berdasarkan survei di lapangan, kit praktikum konverter analog ke digital diperlukan untuk meningkatkan kemampuat taruna. Berdasarkan latar belakang tersebut, penelitian ini bertujuan merancang dan mensimulasi dua rangkaian ADC yang masing-masing disusun oleh IC ADC0804 dan IC ADC0809. Tiga formula statistik, yaitu mean error (ME), standard deviation error (SDE), and root mean square error (RMSE) digunakan untuk mengukur kinerja kedua rangkaian ADC tersebut. Kedua rangkaian ADC tersebut disimulasi menggunakan Simulator Proteus 8.11 dengan 255 tegangan masukan analog. Berdasarkan hasil penelitian diketahui bahwa rangkaian ADC yang disusun oleh IC ADC0809 lebih akurat dibandingkan dengan rangkaian ADC yang disusun oleh IC ADC0804. Hal tersebut dibuktikan dengan nilai kesalahan yang lebih kecil, yaitu berdasarkan hasil simulasi memiliki ME, SDE, RMSE masing-masing adalah 0,4210, 0,3410 dan 0,5110. Dan berdasarkan hasil pengukuran memiliki ME, SDE, dan RMSE masing-masing adalah 0,8510, 0,8110, dan 0,9310. Kata kunci: ADC; Simulator Proteus 8.11; IC ADC0804; IC ADC0809; ME; SDE; RMSE

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Gibson, A. A. P. "Stationary Power Method of Circuit Analysis." International Journal of Electrical Engineering & Education 31, no. 3 (July 1994): 230–36. http://dx.doi.org/10.1177/002072099403100305.

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Stationary power method of circuit analysis In the steady state, electrical LCR circuits with d.c. or a.c. signal sources can be studied using a stationary power principle. A straightforward analytic approach based on this principle is enunciated here. Some simple examples are provided for illustration.

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Zhang, Huan, Weiping Chen, Liang Yin, and Qiang Fu. "An Interface ASIC Design of MEMS Gyroscope with Analog Closed Loop Driving." Sensors 23, no. 5 (February 27, 2023): 2615. http://dx.doi.org/10.3390/s23052615.

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This paper introduces a digital interface application-specific integrated circuit (ASIC) for a micro-electromechanical systems (MEMS) vibratory gyroscope. The driving circuit of the interface ASIC uses an automatic gain circuit (AGC) module instead of a phase-locked loop to realize a self-excited vibration, which gives the gyroscope system good robustness. In order to realize the co-simulation of the mechanically sensitive structure and interface circuit of the gyroscope, the equivalent electrical model analysis and modeling of the mechanically sensitive structure of the gyro are carried out by Verilog-A. According to the design scheme of the MEMS gyroscope interface circuit, a system-level simulation model including mechanically sensitive structure and measurement and control circuit is established by SIMULINK. A digital-to-analog converter (ADC) is designed for the digital processing and temperature compensation of the angular velocity in the MEMS gyroscope digital circuit system. Using the positive and negative diode temperature characteristics, the function of the on-chip temperature sensor is realized, and the temperature compensation and zero bias correction are carried out simultaneously. The MEMS interface ASIC is designed using a standard 0.18 μM CMOS BCD process. The experimental results show that the signal-to-noise ratio (SNR) of sigma-delta (ΣΔ) ADC is 111.56 dB. The nonlinearity of the MEMS gyroscope system is 0.03% over the full-scale range.

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Sankar, P. A. Gowri, and G. Sathiyabama. "A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application." International Journal of Engineering Research in Africa 19 (October 2015): 19–36. http://dx.doi.org/10.4028/www.scientific.net/jera.19.19.

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The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

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Wang, Ming Fei, Peng Cao, Hui Yong Sun, and Ming Jin Xu. "Optimal Design of Broadband and Large Dynamic Range IF AGC Circuit." Advanced Materials Research 722 (July 2013): 194–97. http://dx.doi.org/10.4028/www.scientific.net/amr.722.194.

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The bandwidth and the dynamic range is the critical performance parameter of IF AGC (Intermediate Frequency Automatic Gain Control) in wireless receiver. In order to design broadband and large dynamic range IF AGC circuit, the main functions and performance of the VGA (Variable Gain Amplifier) AD8367 and the logarithmic amplifier AD8318 are analyzed. A kind of a broadband large dynamic range IF AGC module is designed by using these two chips. Detail circuit is provided; key technology of AGC module is analyzed and the actual testing results are offered. Compared to the traditional AGC circuit, the module is simple; it has small size and obvious advantages in broadband and large dynamic range.

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Ning, Yongkai, Jiangfei Guo, Yangchen Jia, Duosheng Li, and Guiliang Guo. "A Fast Interface Circuit for the Measurement of 10 Ω to 1 GΩ Resistance." Electronics 12, no. 18 (September 8, 2023): 3796. http://dx.doi.org/10.3390/electronics12183796.

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In this work, an interface circuit applied to resistive gas or chemical sensors is proposed. The interface circuit includes a detection front-end, a single-end to differential circuit, a successive approximation analog-to-digital converter (SAR ADC), and some reference auxiliary circuits. In detection front-end circuits, mirrored currents in a current mirror usually differ by several orders of magnitude. In order to ensure that the current mirror can be copied accurately, this work uses a negative feedback structure consisting of an operational amplifier and an NMOS tube to ensure that the VDS of the current mirroring tube remains consistent. Simulation results show that the replication error of the current mirror is 0.015%. The proposed interface circuit has a detection range of 10 Ω to 1 GΩ with a relative error of 0.55%. The current multiplication or divided technique allows the interface circuit to have a high sampling frequency of up to 10 kHz. The proposed circuit is based on a 180 nm CMOS process with a chip area of 0.308 mm2 (723 μm ∗ 426 μm). The power consumption of the whole interface circuit is 3.66 mW when the power supply voltage is 1.8 V.

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Yadav, Nandakishor, Youngbae Kim, Mahmoud Alashi, and Kyuwon Ken Choi. "Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application." Electronics 9, no. 3 (March 16, 2020): 490. http://dx.doi.org/10.3390/electronics9030490.

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Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.

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Ni, Haiyan, Jianping Hu, Xuqiang Zhang, and Haotian Zhu. "BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits." Active and Passive Electronic Components 2019 (July 18, 2019): 1–9. http://dx.doi.org/10.1155/2019/8292653.

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This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.

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Zhang, Yi, Qiao Meng, Changchun Zhang, Ying Zhang, Yufeng Guo, Youtao Zhang, Xiaopeng Li, and Lei Yang. "A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology." Journal of Sensors 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/3984526.

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A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

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Sutkovyi, P., Yu Minov, P. Shpylovyi, Ye Melnyk, and M. Mudrenko. "Optimization of low-pass filters in a flux transformer of a SQUID magnetometer for MCG studies." Low Temperature Physics 48, no. 7 (July 2022): 515–19. http://dx.doi.org/10.1063/10.0011597.

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Research and optimization of a passive low-pass filter (LPF) for a magnetic flux transformer of superconducting quantum interferometric detector (SQUID) operating in a magnetocardiographic (MCG) system, in an unshielded room, under the influence of electromagnetic interference of significant intensity have been carried out. The amplitude-frequency characteristics (AFC) of the LPF in the SQUID magnetic flux transformer are calculated for various shunt circuits, including the LPF circuit recommended by “Supracon” group for its CE2 blue model of the SQUID. The analysis of LPF circuits and their frequency response are carried out in order to ensure maximum protection of the input circuits of the SQUID from the effects of electromagnetic interference. It is shown that the optimal LPF for the MCG system is a filter with an active resistance of about 1 Ω in the shunt circuit of magnetic flux transformer. The performed calculations of the LPF intrinsic noise in the SQUID magnetic flux transformer showed that the additional noise of the shunt circuit with a 1 Ω resistor is significantly less than external noise for MCG system operating in unshielded rooms in the industrial city.

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Lepla, Keith C., and Gary Horlick. "Photodiode Array Systems for Inductively Coupled Plasma-Atomic Emission Spectrometry." Applied Spectroscopy 43, no. 7 (September 1989): 1187–95. http://dx.doi.org/10.1366/0003702894203462.

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Details are presented for the construction of photodiode array (PDA) measurement systems from commercial components. The PDA systems described include the Hamamatsu S2304–1024Q, a Reticon 1024S using the RC1000 and RC1001 circuit boards, and a Reticon 1024S using the RC1024S circuit board. Detals are presented for computer-controlled clocking and timing circuits, ADC sub-systems, and Peltier cooling subsystems. The measurement characteristics (sensitivity and detection limits) for all arrays are intercompared with the use of analyte emission signals from an inductively coupled plasma.

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Setiabudi, Agung, Hiroki Tamura, and Koichi Tanno. "High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4148. http://dx.doi.org/10.11591/ijece.v8i6.pp4148-4156.

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A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.

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Li, Dong, Mengxia Liu, QianCheng Zhao, and Jian Cui. "Phase noise modelling of MEMS resonant accelerometer with non-AGC-driven circuit." Journal of Micromechanics and Microengineering 32, no. 6 (April 13, 2022): 064001. http://dx.doi.org/10.1088/1361-6439/ac628f.

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Abstract Phase noise is an essential performance indicator for microelectromechanical system (MEMS) resonant accelerometers. The optimal resolution achievable is limited by the close-to-the carrier phase noise resulting from the modulation of noise sources by the mechanical resonator and driving circuit. Compared with the frequently used automatic gain control (AGC) circuit, the non-AGC scheme is more concise and can avoid the additional frequency flicker noise and 1/f 5 phase noise introduced by the AGC module. Although the mechanisms of these two kind of control loops are well-known by the communities, the phase noise modelling study on the non-AGC loop, especially compared with that of AGC loop is insufficient. This paper established a phase noise model for the AGC and non-AGC closed loop circuit of MEMS resonant accelerometer. The model includes the effects of resonator thermal noise, random loading noise of proof masses, front-circuit noise, comparator noise, AGC noise and amplitude stiffness coupling on the output noise spectrum of the resonant accelerometer. This paper carries the noise analysis through a behaviour level simulation with Simulink. The measured frequency power spectral density and Allan variance are very close to the theoretical predictions, which verifies the effectiveness of the phase noise model. The test results show that the white noise and the bias instability of the silicon resonant accelerometer are 837 ng (√Hz)−1 and 140 ng respectively, which are in good agreement with the model prediction results.

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Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Bhargava, Bhanupriya, Pradeep Kumar Sharma, and Shyam Akashe. "High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime." International Journal of Nanoscience 13, no. 01 (February 2014): 1450003. http://dx.doi.org/10.1142/s0219581x14500033.

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In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

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Faheem, Muhammad Yasir, Shun'an Zhong, Xinghua Wang, and Muhammad Basit Azeem. "Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology." Circuit World 46, no. 3 (February 3, 2020): 183–92. http://dx.doi.org/10.1108/cw-09-2019-0127.

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Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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Suszyński, Robert, and Krzysztof Wawryn. "Rapid Prototyping of Third-Order Sigma-Delta A/D Converters." International Journal of Electronics and Telecommunications 59, no. 1 (March 1, 2013): 99–104. http://dx.doi.org/10.2478/eletel-2013-0012.

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Abstract Prototyping of third-order sigma-delta analog to digital converters (ΣΔ ADCs) has been presented in the paper. The method is based on implementation of field programmable analog arrays (FPAA) to configure and reconfigure proposed circuits. Three third-order ΣΔ ADC structures have been considered. The circuit characteristics have been measured and then the structure of the converters have been reconfigured to satisfy input specifications.

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Zhang, Zheng Ping, Yong Lu Wang, and Ming Liu. "A High Speed Open-Loop Track/Hold Circuit in CMOS Process." Advanced Materials Research 756-759 (September 2013): 4302–5. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4302.

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A high speed open-loop track/hold circuit in 0.18um CMOS process is presented. Open-loop and differential architecture are adopted to obtain high bandwidth and high speed;time-interleaved structure is used to reach a high sampling rate;source negative feedback and offset compensation are used to improve the linearity of the circuit.Simulation results show that with 396.875MHz input, 1.6GSPS sampling rate, driving the pre-amplifier of ADC, the thack/hold circuits SFDR(spurious-free dynamic range) is 75.8dB,satisfying the demand of 12 bits ADC.The circuit features high sampling rate,wide bandwidth,high SFDR and universal.

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Cam Taskiran, Zehra Gulru, Murat Taşkıran, Mehmet Kıllıoğlu, Nihan Kahraman, and Herman Sedef. "A novel memristive true random number generator design." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 6 (October 24, 2019): 1931–47. http://dx.doi.org/10.1108/compel-11-2018-0463.

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Purpose In this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals. Methodology A Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results. Originality It is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators. Findings Two new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

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VASUDEVA, G., and B. V. UMA. "Low Voltage Low Power And High Speed OPAMP Design using High-K FinFET Device." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 20 (June 28, 2021): 80–87. http://dx.doi.org/10.37394/23201.2021.20.11.

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In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

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Liu, Hui Zhi, Xu Hong Wang, Kun Yang Wang, and Ju Xiang Feng. "An Induction Motor Stator Core Fault Model Based on Stator Negative Sequence Current." Applied Mechanics and Materials 203 (October 2012): 406–10. http://dx.doi.org/10.4028/www.scientific.net/amm.203.406.

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An on-line method is proposed in this work to detect induction motor stator core fault by using stator negative sequence current. According to the existing abc coordinate model, a new equivalent circuit is obtained. In this circuit, the stator core loss each phase in normal state is modeled as core loss resistance symmetrically distributed among the three phases. The stator core loss is increased and is asymmetrically distributed among the three phases when a stator fault happens. The positive, negative and zero sequence equivalent circuits are drawn by a series of analysis of the circuit put forward above. It is demonstrated that there is a good correlation between stator core fault severity and the magnitude of the negative sequence current.

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Zhao, Zuoqin, Yufei Nai, Zhiguo Yu, Xin Xu, Xiaoyang Cao, and Xiaofeng Gu. "Design of Low-Power ECG Sampling and Compression Circuit." Applied Sciences 13, no. 5 (March 6, 2023): 3350. http://dx.doi.org/10.3390/app13053350.

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Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm2 and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm2, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality.

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Li, Yuekai, Lei Yang, Lefu Yu, Boyang Liao, and Pengfei Xu. "Digital AGC Circuit Design based on FPGA." Journal of Physics: Conference Series 1654 (October 2020): 012030. http://dx.doi.org/10.1088/1742-6596/1654/1/012030.

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Zayer, Salam, Marwah Muneer Al-bayati, György Györök, and Ahmed Bouzid. "Pragmatic Implementation of the Front-End of an N-bit/V ADC based on FPGA and FPAA." Carpathian Journal of Electronic and Computer Engineering 13, no. 2 (December 1, 2020): 12–15. http://dx.doi.org/10.2478/cjece-2020-0008.

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Abstract Reconfigurability has made it possible, among other benefits, to replace traditional discrete components with chips, whose internal components can be programmed in this case FPAAs (Field Programmable Analog Arrays). This paper presents a design and implementation of FPAA of the analog front end dedicated to a new ADC architecture called “N-bit/V”. After validation of the algorithm in simulation, the experimentation results show that the obtained reconfigurable circuit can replace the traditional discrete components-based circuits.

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Sharga, Miss Rashi. "Outline and Testing of Portable Solar Inverter." International Journal for Research in Applied Science and Engineering Technology 9, no. 10 (October 31, 2021): 1699–704. http://dx.doi.org/10.22214/ijraset.2021.38677.

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Abstract: In this study we talk about ,a simulacrum of one phase inverter using solar energy, The main aim is use of solar energy for electricity to study about Portable inverter, to use solar energy for electricity . Inverter circuits consists of Ups , battery module and battery charger. The main work of Inverter is to convert D.C voltage to A.C voltage .Inverter circuit are divided into 3 parts Bjt switch ,control circuit which is use for generate pluses thorough micro controller ,filter part consists of capacitor, Resistor which is use to overcome of harmonics. The main purpose of this work, to be simple such as for as assessing knowledge about solar movable inverter with minimum cost and uses. Keywords: Solar panel, Regulator, battery charger, Inverter circuit, switching device, Transformer.

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Karmakar, Supriya, John A. Chandy, and Faquir C. Jain. "Implementation of Membership Function using Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 23, no. 01n02 (March 2014): 1450007. http://dx.doi.org/10.1142/s0129156414500074.

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Spatial wave-function switched field effect transistor (SWSFET) switches the current flow between different channels inside the FET based on the applied voltage in its gate terminal. SWSFET can be used to implement multi-valued logic circuit with less number of circuit elements. Recently we presented unipolar inverter circuit using SWSFET. In this paper we develop a circuit model of SWSFET based on BSIM 3.2.0 and BSIM 3.2.4 and implement membership function using that circuit model of SWSFET. The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the SWSFET, switches the charge carrier concentration in different channels from source to drain region. A circuit model of SWSFET is developed in BSIM 3.2.0. Membership function is implemented using the circuit model of the SWSFET. Membership function implementation using less number of SWSFET will reduce the device count in future analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits.

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Kakarla, Deepti. "An optimized design approach for 8-bit pipelined ADC using high gain amplifier." i-manager’s Journal on Electronics Engineering 12, no. 2 (2022): 23. http://dx.doi.org/10.26634/jele.12.2.18529.

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Demand of high-performance converters with integrated circuits with combined features and specifications of power consumption, resolution and speed have become very dominant in many emerging applications. Pipelined ADC mixed signal system consists of Sample and Hold, Flash ADC, DAC and Gain amplifier in all the stages. In the present work, a pipeline ADC architecture has 3-stages, with each stage of 3-bits with 3-bit flash ADC followed by a 3-bit binary weighted DAC at each stage. A novel approach to design a 8-bit ADC is implemented, and this design offers less number of comparators compared to flash ADC with less circuit complexity, and 8-bit ADC is designed with improvement in resolution. It is simulated first in MATLAB, but applying 1.8Volts sinusoidal and sampling time of 40 MSPS and clock frequency 10MHz the individual blocks are implemented in LT-spice 180 nm technology with bandwidth of 40 MHz. Then a high gain amplifier is implemented by using Diode connected load differential amplifier with 10mv input voltage and 18Mhz input frequency.

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Journal articles on the topic 'AGC CIRCUITS'

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